Renesas M16C/64A Series User Manual page 524

M16C/64A Group
(1) IICM2 = 0 (ACK and NACK interrupts), CKPH = 1 (clock delay)
1st bit
SCLi
D7
SDAi
(2) IICM2 = 1 (UART transmit / receive interrupt), CKPH = 1
1st bit
SCLi
D7
SDAi
i = 0 to 2, 5 to 7
IICM2: Bit in the UiSMR2 register
CKPH: Bit in the UiSMR3 register
The above diagram assumes the CKDIR bit in the UiMR register is 1 (slave selected).
Figure 23.20 Transfer to UiRB Register and Interrupt Timing
R01UH0136EJ0210 Rev.2.10
Jul 31, 2012
2nd bit 3rd bit 4th bit 5th bit
D6 D5 D4 D3
2nd bit 3rd bit 4th bit 5th bit
D6 D5 D4 D3
Receive interrupt (DMA1, DMA3 request)
b15 b9
...
(read by reception interrupt)
23. Serial Interface UARTi (i = 0 to 2, 5 to 7)
6th bit 7th bit 8th bit 9th bit
D2 D1 D0 D8 (ACK, NACK)
ACK interrupt (DMA1, DMA3 request), NACK interrupt
Transfer to UiRB register
b15
6th bit 7th bit 8th bit 9th bit
D2 D1 D0 D8 (ACK, NACK)
Transfer to UiRB register
b8 b7 b0
D0 D7 D6 D5 D4 D3 D2 D1
UiRB register
Initial value and
end value are low.
b9 b8 b7
...
D8 D7 D6 D5 D4 D3 D2 D1 D0
UiRB register
Initial value and
end value are low.
Transmit interrupt
Transfer to UiRB register
b15 b9 b8 b7
...
D8 D7 D6 D5 D4 D3 D2 D1 D0
UiRB register
(read by transmission interrupt)
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b0
b0