Renesas M16C/64A Series User Manual page 610

M16C/64A Group
2
Table 25.16 I C-bus Interrupts
Interrupt
Completion of data transmit/receive
When the ACKCLK bit in the S20 register is 0:
Detection of the falling edge of the last clock of
transmit/receive data through the SCLMM pin
When the ACKCLK bit is 1:
Detection of the falling edge of ACK clock
through the SCLMM pin
Data reception (before ACK clock)
Detection of the falling edge of the last clock of
transmit/receive data through the SCLMM pin
Detection of slave address match
Received slave address matches bits SAD6 to
SAD0 in registers S0D0 to S0D2 in slave
receive mode with addressing format
(AAS bit in the S10 register = 1)
Detection of general call
General call in slave receive mode with
addressing format
(ADR0 bit in the S10 register = 1)
Completion of receiving slave address in slave
receive mode with free data format
Stop condition detected
Timeout detected
Detection of the falling edge or rising edge of
input/output signal for the SCLMM or SDAMM
pin
Refer to 14.7 "Interrupt Control". Table 25.17 lists Registers Associated with I
R01UH0136EJ0210 Rev.2.10
Jul 31, 2012
Interrupt Source
25. Multi-master I
Associated Bits (Register)
Interrupt Interrupt
enabled request
—
WIT (S3D0)
PIN (S10)
—
SIM (S3D0) SCPIN (S4D0)
TOE (S4D0) TOF (S4D0)
— —
2
C Interface Interrupts.
2
C-bus Interface
Interrupt
Control
Register
IICIC
SCLDAIC
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