18. Timer B; Introduction - Renesas M16C/64A Series User Manual

M16C/64A Group

18. Timer B

18.1

Introduction

Timer B consists of timers B0 to B5. Each timer operates independently of the others. Table 18.1 lists
Timer B Specifications, Figure 18.1 shows Timer A and B Count Sources, Figure 18.2 shows the Timer B
Configuration, Figure 18.3 shows the Timer B Block Diagram, and Table 18.2 lists the I/O Ports.
Table 18.1 Timer B Specifications
Item
Configuration 16-bit timer × 6
Operating modes
Interrupt source Overflow/underflow/active edge of measurement pulse × 6
Clock Generator
Main clock
oscillator
or PLL frequency
synthesizer
125 kHz
fOCO-S
on-chip
oscillator
fC
Sub clock
oscillator
Figure 18.1 Timer A and B Count Sources
R01UH0136EJ0210 Rev.2.10
Jul 31, 2012
•
Timer mode
The timer counts an internal count source.
•
Event counter mode
The timer counts pulses from an external device, or overflows and underflows of other timers.
•
Pulse period/pulse width measurement modes
The timer measures pulse periods or pulse widths of an external signal.
CM21
0
1
1/32
Reset
Set the CPSR bit in the CPSRF
register to 1 (prescaler reset).
Specification
f1TIMAB
f2TIMAB
1/2
1/8
f1
0
Timer AB divider
fOCO-S
fC32
CM21
PCLK0
18. Timer B
PCLK0
f1TIMAB
1
or
0
f2TIMAB
f8TIMAB
f32TIMAB
1/4
f64TIMAB
1/2
fOCO-S
fC32
: Bit in the CM2 register
: Bit in the PCLKR register
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