Data Bank Register (Dbr) - Renesas M16C/64A Series User Manual

M16C/64A Group
12.2.1

Data Bank Register (DBR)

Data Bank Register
b7 b6 b5 b4 b3 b2 b1
The DBR register is enabled when bits PM01 to PM00 in the PM0 register are 01b (memory expansion
mode) or 11b (microprocessor mode).
This register becomes write enabled when bits PM15 to PM14 in the PM1 register are 11b (4-MB
mode).
R01UH0136EJ0210 Rev.2.10
Jul 31, 2012
b0
Symbol
DBR
Bit Symbol Bit Name
—
No register bits. If necessary, set to 0. The read value is 0.
(b1-b0)
OFS Offset bit
BSR0
Bank select bit
BSR1
BSR2
—
No register bits. If necessary, set to 0. The read value is 0.
(b7-b6)
Address
000Bh
0 : No offset
1 : Offset
b5 b4 b3
0 0 0 : Bank 0
0 0 1 : Bank 1
0 1 0 : Bank 2
0 1 1 : Bank 3
12. Memory Space Expansion Function
Reset Value
00h
Function
b5 b4 b3
1 0 0 : Bank 4
1 0 1 : Bank 5
1 1 0 : Bank 6
1 1 1 : Bank 7
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RW
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RW
RW
RW
RW
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