Uarti Special Mode Register 3 (Uismr3) (I = 0 To 2, 5 To 7) - Renesas M16C/64A Series User Manual

M16C/64A Group

23.2.10 UARTi Special Mode Register 3 (UiSMR3) (i = 0 to 2, 5 to 7)

UARTi Special Mode Register 3 (i = 0 to 2, 5 to 7)
b7 b6 b5 b4 b3 b2 b1
NODC (Clock output select bit) (b3)
This function is used to set P-channel transistor of the CMOS output buffer always off, but not to
change the CLKi pin to open drain output completely.
Refer to the electrical characteristics for the input voltage range.
DL2-DL0 (SDAi digital delay setup bit) (b7-b5)
Bits DL2 to DL0 are used to generate a digital delay in SDAi output in I
set these bits to 000b (no delay).
The delay length varies with the load on pins SCLi and SDAi. Also, when using an external clock, the
delay length increases by about 100 ns.
R01UH0136EJ0210 Rev.2.10
Jul 31, 2012
Symbol
b0
U0SMR3, U1SMR3, U2SMR3
U5SMR3, U6SMR3, U7SMR3
Bit Symbol Bit Name
—
No register bit. If necessary, set to 0. Read as undefined value
(b0)
Clock phase set bit
CKPH
—
No register bit. If necessary, set to 0. Read as undefined value
(b2)
NODC Clock output select bit
—
No register bit. If necessary, set to 0. Read as undefined value
(b4)
DL0
SDAi digital delay
DL1
setup bit
DL2
23. Serial Interface UARTi (i = 0 to 2, 5 to 7)
Address
0245h, 0255h, 0265h
0285h, 0295h, 02A5h
Function
0 : No clock delay
1 : With clock delay
0 : CLKi is CMOS output
1 : CLKi is N-channel open drain output
b7 b6 b5
0 0 0 : No delay
0 0 1 : 1 to 2 cycles of UiBRG count source
0 1 0 : 2 to 3 cycles of UiBRG count source
0 1 1 : 3 to 4 cycles of UiBRG count source
1 0 0 : 4 to 5 cycles of UiBRG count source
1 0 1 : 5 to 6 cycles of UiBRG count source
1 1 0 : 6 to 7 cycles of UiBRG count source
1 1 1 : 7 to 8 cycles of UiBRG count source
2
C mode. Except in I
Reset Value
000X 0X0Xb
000X 0X0Xb
RW
—
RW
—
RW
—
RW
RW
RW
2
C mode,
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