Renesas M16C/64A Series User Manual page 602

M16C/64A Group
25.3.8 Operation after Transmitting/Receiving a Slave Address or Data
After a slave address or 1-byte data has been transmitted/received, the PIN bit in the S10 register
becomes 0 (interrupt requested) at the falling edge of the ACK clock. The IR bit in the IICIC register
becomes 1 (interrupt requested) at the same time. The value in the S10 register or other register
changes depending on the state of the transmit/receive data, and the level of pins SCLMM and
SDAMM. Figure 25.15 shows Operation When Transmitted/Received a Slave Address or Data.
SCLMM
SDAMM
PIN bit in the
S10 register
Bits BC2 to BC0 in
the S1D0 register
MST bit in the
S10 register
TRX bit in the
S10 register
TRX bit in the
S10 register
ADR0 bit in the
S10 register
AAS bit in the
S10 register
IR bit in the IICIC
register
Figure 25.15 Operation When Transmitted/Received a Slave Address or Data
R01UH0136EJ0210 Rev.2.10
Jul 31, 2012
SCLMM pin outputs low
when PIN bit is 0
ACK clock
A/A
25. Multi-master I
000b
(When arbitration is lost)
(When no ACK is returned in
slave transmit mode)
2 fVIIC cycles
(When received a slave address
and R/W bit is set to 1)
(General call when received a
slave address)
1 fVIIC cycles
(General call or address matches
when received a slave address)
Set to 0 by an interrupt request acceptance
or by a program
2
C-bus Interface
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