Renesas M16C/64A Series User Manual page 542

M16C/64A Group
(1) Transmit Timing
Transmit/receive clock
1
TE bit in
U2C1 register
0
1
TI bit in
U2C1 register
0
TXD2
Parity error signal
returned from receiver
(2)
RXD2 pin level
1
TXEPT bit in
U2C0 register
0
1
IR bit in
S2TIC register
0
The above timing diagram applies when data is
transmitted in the direct format.
• The STPS bit in the U2MR register = 0 (1 stop bit)
• The PRY bit in the U2MR register = 1 (even parity)
• The UFORM bit in the U2C0 register
• The U2LCH bit in the U2C1 register
• The U2IRS bit in the U2C1 register = 1 (transmit completed)
(2) Receive Timing
Transmit/receive clock
1
RE bit in
U2C1 register
0
Transmit waveform
from transmitter
TXD2
(3)
RXD2 pin level
RI bit in 1
U2C1 register
0
1
IR bit in
S2RIC register
0
The above timing diagram applies when data is
received in the direct format.
• The STPS bit in the U2MR register = 0 (1 stop bit)
• The PRY bit in the U2MR register = 1 (even parity)
• The UFORM bit in the U2C0 register
• The U2LCH bit in the U2C1 register
• The U2IRS bit in the U2C1 register= 1 (transmit completed)
Notes:
1. Data transmission starts when BRG overflows after a value is set in the U2TB register on the rising edge of the TI bit.
2. Because pins TXD2 and RXD2 are connected, a composite waveform, consisting of the transmit waveform from the
TXD2 pin and parity error signal from the receiver, is generated.
3. Because pins TXD2 and RXD2 are connected, a composite waveform, consisting of the transmit waveform from the
transmitter and parity error signal from the TXD2 pin, is generated.
Figure 23.35 Transmit/Receive Timing in SIM Mode
R01UH0136EJ0210 Rev.2.10
Jul 31, 2012
Tc
Data is written to the U2TB register.
Start
bit
ST D0 D1 D2 D3 D4 D5 D6
ST D0 D1 D2 D3 D4 D5 D6
Set to 0 by a program.
= 0 (LSB first)
= 0 (not inverted)
Tc
Start
bit
ST D0 D1 D2 D3 D4 D5 D6
ST D0 D1 D2 D3 D4 D5 D6
= 0 (LSB first)
= 0 (not inverted)
23. Serial Interface UARTi (i = 0 to 2, 5 to 7)
(Note 1)
Data is transferred from the U2TB
register to the UART2 transmit
Stop
Parity
register
bit
bit
D7 P SP ST D0 D1
A low-level signal is applied from
the SIM card due to a parity error.
D7 P SP ST D0 D1
An interrupt
routine
detects the level.
Set to 0 by an interrupt request acknowledgment or by a program.
TC = 16 (n + 1) / fi or 16 (n + 1) / fEXT
fi : Frequency of U2BRG count source (f1SIO, f2SIO, f8SIO,
f32SIO)
fEXT : Frequency of U2BRG count source (external clock)
n : Value set to U2BRG
Parity Stop
bit
bit
D7 P SP ST D0 D1
output due to a parity error.
D7 P SP ST D0 D1
Read the U2RB register.
Set to 0 by an interrupt request acknowledgment or by a program.
TC = 16 (n + 1) / fi or 16 (n + 1) / fEXT
fi : Frequency of U2BRG count source (f1SIO, f2SIO,
f8SIO, f32SIO)
fEXT : Frequency of U2BRG count source (external clock)
n : Value set to U2BRG
D2 D3 D4 D5 D6 D7 P SP
D2 D3 D4 D5 D6 D7 P
An interrupt routine detects
the level.
SP
D2 D3 D4 D5 D6 D7 P
TXD2 provides low-level
D2 D3 D4 D5 D6 D7 P
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SP
SP