Renesas M16C/64A Series User Manual page 605

M16C/64A Group
25.3.10.2 Master Transmission
Master transmission is described in this section. The initial settings described in 25.3.10.1 "Initial
Settings" are assumed to be completed. Figure 21.17 shows master transmission operation.
The following programs (A) to (C) are executed at (A) to (C) in Figure 25.17, respectively.
SCLMM
SDAMM
IR bit in the IICIC
register
Figure 25.17 Example of Master Transmission
(A) Slave address transmission
(1) The BB bit in the S10 register must be 0 (bus free).
(2) Write E0h to the S10 register (start condition standby).
(3) Write a slave address to the upper 7 bits and set the least significant bit (LSB) to 0 (start
condition generated, then slave address transmitted).
(B) Data transmission
2
(in I C-bus interrupt routine)
(1) Write transmit data to the S00 register (data transmission).
(C) Completion of Master transmission
2
(in I C-bus interrupt routine)
(1) Write C0h to the S10 register (stop condition standby state)
(2) Write dummy data to the S00 register (stop condition generated).
When transmission is completed or ACK is not returned from a slave device (NACK returned), master
transmission should be completed as shown in the example above.
R01UH0136EJ0210 Rev.2.10
Jul 31, 2012
S: Start condition
P: Stop condition
m
Slave address
S
W
(7 bits)
(A) Slave address transmission
A: ACK R: Read
A: NACK W: Write
s m s
Data
A A
(8 bits)
Set to 0 by interrupt request acceptance or by program
(B) Data transmission
2
25. Multi-master I C-bus Interface
m: Master outputs to SDA
s: Slave outputs to SDA
m s
m
Data
A/A P
(8 bits)
(C) Completion of master
transmission
Stop condition
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