Uart Transmit/Receive Control Register 2 (Ucon) - Renesas M16C/64A Series User Manual

M16C/64A Group
23.2.8

UART Transmit/Receive Control Register 2 (UCON)

UART Transmit/Receive Control Register 2
b7 b6 b5 b4 b3 b2 b1
Bits UiIRS and UiRRM of UART2 and UART5 to UART7 are bits in the UiC1 register.
CLKMD1 (UART1CLK, CLKS select bit 1) (b5)
When using multiple transmit/receive clock output pins, make sure that the CKDIR bit in the U1MR
register is 0 (internal clock).
R01UH0136EJ0210 Rev.2.10
Jul 31, 2012
b0
Symbol
UCON
Bit symbol Bit Name
UART0 transmit interrupt
U0IRS
source select bit
UART1 transmit interrupt
U1IRS
source select bit
UART0 continuous receive
U0RRM
mode enable bit
UART1 continuous receive
U1RRM
mode enable bit
CLKMD0 UART1CLK, CLKS select bit 0
CLKMD1 UART1CLK, CLKS select bit 1
Separate UART0
RCSP
CTS/RTS bit
—
No register bit. If necessary, set to 0. Read as undefined value
(b7)
23. Serial Interface UARTi (i = 0 to 2, 5 to 7)
Address
0250h
Function
0 : Transmit buffer empty (Tl = 1)
1 : Transmission completed (TXEPT = 1)
0 : Transmit buffer empty (Tl = 1)
1 : Transmission completed (TXEPT = 1)
0 : Continuous receive mode disabled
1 : Continuous receive mode enabled
0 : Continuous receive mode disabled
1 : Continuous receive mode enabled
Enabled when CLKMD1 is 1
0 : Clock output from CLK1
1 : Clock output from CLKS1
0 : CLK output is only from CLK1
1 : Transmit/receive clock output from
multiple-pin output function selected
0 : CTS/RTS shared pin
1 : CTS/RTS separated
After Reset
X000 0000b
RW
RW
RW
RW
RW
RW
RW
RW
—
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