Renesas M16C/64A Series User Manual page 275

M16C/64A Group
Table 16.5 Sources of DMA Request (DMA2)
DSEL4 to DSEL0 DMS is 0 (Basic Source of Request) DMS is 1 (Expanded Source of Request)
Falling edge of the INT2 pin
0 0 0 0 0 b
0 0 0 0 1 b Software trigger
0 0 0 1 0 b Timer A0
0 0 0 1 1 b Timer A1
0 0 1 0 0 b Timer A2
0 0 1 0 1 b Timer A3
0 0 1 1 0 b Timer A4
0 0 1 1 1 b Timer B0
0 1 0 0 0 b Timer B1
0 1 0 0 1 b Timer B2
0 1 0 1 0 b UART0 transmission
0 1 0 1 1 b UART0 reception
0 1 1 0 0 b UART2 transmission
0 1 1 0 1 b UART2 reception
0 1 1 1 0 b A/D converter
0 1 1 1 1 b UART1 transmission
1 0 0 0 0 b UART1 reception
1 0 0 0 1 b UART5 transmission
1 0 0 1 0 b UART5 reception
1 0 0 1 1 b UART6 transmission
1 0 1 0 0 b UART6 reception
1 0 1 0 1 b UART7 transmission
1 0 1 1 0 b UART7 reception
1 0 1 1 1 b –
1 1 X X X b –
X: 0 or 1 – Do not set.
Table 16.6 Source of DMA Request (DMA3)
DSEL4 to DSEL0 DMS is 0 (Basic Source of Request) DMS is 1 (Expanded Source of Request)
Falling edge of the INT3 pin
0 0 0 0 0 b
0 0 0 0 1 b Software trigger
0 0 0 1 0 b Timer A0
0 0 0 1 1 b Timer A1
0 0 1 0 0 b Timer A2
0 0 1 0 1 b Timer A3
0 0 1 1 0 b Timer A4
0 0 1 1 1 b Timer B0
0 1 0 0 0 b Timer B1
0 1 0 0 1 b Timer B2
0 1 0 1 0 b UART0 transmission
0 1 0 1 1 b UART0 reception/ACK0
0 1 1 0 0 b UART2 transmission
0 1 1 0 1 b UART2 reception/ACK2
0 1 1 1 0 b A/D converter
0 1 1 1 1 b UART1 reception/ACK1
1 0 0 0 0 b UART1 transmission
1 0 0 0 1 b UART5 transmission
1 0 0 1 0 b UART5 reception/ACK5
1 0 0 1 1 b UART6 transmission
1 0 1 0 0 b UART6 reception/ACK6
1 0 1 0 1 b UART7 transmission
1 0 1 1 0 b UART7 reception/ACK7
1 0 1 1 1 b –
1 1 X X X b –
X: 0 or 1 – Do not set.
R01UH0136EJ0210 Rev.2.10
Jul 31, 2012
–
–
–
–
–
–
Both edges of the INT2 pin
Timer B3
Timer B4
Timer B5
–
–
–
–
–
–
Falling edge of the INT6 pin
Both edges of the INT6 pin
–
–
–
–
–
–
–
–
–
–
–
–
SI/O3
SI/O4
Both edges of the INT3 pin
–
–
–
–
–
–
–
–
Falling edge of the INT7 pin
Both edges of the INT7 pin
–
–
–
–
–
–
–
16. DMAC
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