Renesas V850ES/IE2 User Manual

32-bit single-chip microcontrollers

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Page 1 Chipsmall Limited consists of a professional team with an average of over 10 year of expertise in the distribution of electronic components. Based in Hongkong, we have already established firm and mutual-benefit business relationships with customers from,Europe,America and south Asia,supplying obsolete and hard-to-find components to meet their specific needs.
Page 2 On April 1 , 2010, NEC Electronics Corporation merged with Renesas Technology Corporation, and Renesas Electronics Corporation took over all the business of both companies. Therefore, although the old company name remains in this document, it is a valid Renesas Electronics document. We appreciate your understanding.
Page 3 Renesas Electronics. Renesas Electronics shall not be in any way liable for any damages or losses incurred by you or third parties arising from the use of any Renesas Electronics product for an application categorized as “Specific”...
Page 4 User’s Manual V850ES/IE2 32-bit Single-Chip Microcontrollers Hardware μ PD70F3713 μ PD70F3714 Document No. U17716EJ2V0UD00 (2nd edition) Date Published February 2008 N 2005 Printed in Japan...
Page 5 [MEMO] User’s Manual U17716EJ2V0UD...
Page 6 NOTES FOR CMOS DEVICES VOLTAGE APPLICATION WAVEFORM AT INPUT PIN Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the CMOS device stays in the area between V (MAX) and V (MIN) due to noise, etc., the device may malfunction.
Page 7 The information in this document is current as of January, 2008. The information is subject to • change without notice. For actual design-in, refer to the latest publications of NEC Electronics data sheets or data books, etc., for the most up-to-date specifications of NEC Electronics products. Not all products and/or types are available in every country.
Page 8 This manual is intended to give users an understanding of the hardware functions. Organization The V850ES/IE2 User’s Manual is divided into two parts: Hardware (this manual) and Architecture (V850ES Architecture User’s Manual). The organization of each manual is as follows:...
Page 9 Conventions Data significance: Higher digits on the left and lower digits on the right Active low representation: xxx (overscore over pin or signal name) Memory map address: Higher addresses on the top and lower addresses on the bottom Note: Footnote for item marked with Note in the text Caution: Information requiring particular attention Remark:...
Page 10 Related Documents The related documents indicated in this publication may include preliminary versions. However, preliminary versions are not marked as such. Documents related to V850ES/IE2 Document Name Document No. V850ES Architecture User’s Manual U15943E V850ES/IE2 Hardware User’s Manual This manual Documents related to development tools (user’s manuals)
Page 11 CONTENTS CHAPTER 1 INTRODUCTION......................... 14 General ............................14 Features .............................15 Applications..........................16 Ordering Information ........................16 Pin Configuration ........................17 Function Blocks ........................19 CHAPTER 2 PIN FUNCTIONS ....................... 22 List of Pin Functions.........................22 Pin I/O Circuits and Recommended Connection of Unused Pins........26 Pin I/O Circuits...........................28 CHAPTER 3 CPU FUNCTION ........................
Page 12 4.7.2 Cautions on bit manipulation instruction for port n register (Pn) ..........120 CHAPTER 5 CLOCK GENERATOR .....................121 Overview ..........................121 Configuration ..........................122 Control Registers........................124 PLL Function ...........................130 5.4.1 Overview............................. 130 5.4.2 PLL mode ........................... 130 5.4.3 Clock-through mode ........................130 Operation ..........................131 5.5.1 Operation of each clock ......................
Page 13 Configuration.......................... 352 Control Register ........................353 Operation ..........................354 8.4.1 Interval timer mode ........................354 Cautions ..........................358 CHAPTER 9 MOTOR CONTROL FUNCTION ..................359 Functional Overview ......................359 Configuration.......................... 360 Control Registers ........................364 Operation ..........................377 9.4.1 System outline ..........................377 9.4.2 Dead-time control (generation of negative-phase wave signal) ..........382 9.4.3...
Page 14 11.9.4 Timer interrupt request signal in timer trigger mode ..............468 11.9.5 Re-conversion start trigger input during stabilization time ............468 11.9.6 Variation of A/D conversion results..................... 468 11.9.7 A/D conversion result hysteresis characteristics................. 468 11.9.8 Restrictions on setting one-shot mode and software trigger mode ..........469 11.10 How to Read A/D Converter Characteristics Table .............470 CHAPTER 12 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) ..........474 12.1 Features ...........................474...
Page 15 14.2.2 Restore ............................550 14.2.3 Non-maskable interrupt status flag (NP) ..................551 14.3 Maskable Interrupts ....................... 552 14.3.1 Operation ............................552 14.3.2 Restore ............................554 14.3.3 Priorities of maskable interrupts....................555 14.3.4 Interrupt control registers (xxICn) ....................559 14.3.5 Interrupt mask registers 0 to 3 (IMR0 to IMR3)................562 14.3.6 In-service priority register (ISPR) ....................564 14.3.7 Maskable interrupt status flag (ID) ....................565 14.4 External Interrupt Request Input Pins (INTP0 to INTP6) ............
Page 16 CHAPTER 17 REGULATOR ........................605 17.1 Overview ..........................605 17.2 Operation ..........................606 CHAPTER 18 FLASH MEMORY......................607 18.1 Features ...........................607 18.2 Memory Configuration......................608 18.3 Functional Overview.......................609 18.4 Rewriting by Dedicated Flash Memory Programmer ............613 18.4.1 Programming environment ......................613 18.4.2 Communication mode......................... 614 18.4.3 Flash memory control .........................
Page 17 CHAPTER 1 INTRODUCTION The V850ES/IE2 is one of the low-power operation products in the NEC Electronics V850 Series of single-chip microcontrollers designed for real-time control applications. 1.1 General The V850ES/IE2 is a 32-bit single-chip microcontroller that includes the V850ES CPU core and peripheral functions such as ROM/RAM, a timer/counter, serial interfaces, a watchdog timer, and an A/D converter.
Page 18 CHAPTER 1 INTRODUCTION 1.2 Features Minimum instruction execution time: 50 ns (at internal 20 MHz operation) General-purpose registers: 32 bits × 32 Signed multiplication (16 × 16 → 32): 1 to 2 clocks CPU features: Signed multiplication (32 × 32 → 64): 1 to 5 clocks Saturated operation instructions (with overflow/underflow detection function) 32-bit shift instructions: 1 clock Bit manipulation instructions...
Page 19 CHAPTER 1 INTRODUCTION Clock generator: 2.5 MHz resonator connectable (external clock input prohibited) Multiplication function by PLL clock synthesizer (fixed to multiplication by eight, f 20 MHz) CPU clock division function (f /2, f /4, f Power-save function: HALT/IDLE/ STOP mode Power-on-clear function Low-voltage detection function μ...
Page 20 CHAPTER 1 INTRODUCTION 1.5 Pin Configuration • 64-pin plastic LQFP (14 × 14) μ PD70F3713GC-8BS-A μ PD70F3714GC-8BS-A Top View P25/TOQ1B3 PDL3 P24/TOQ1T3 PDL4 P23/TOQ1B2 PDL5/FLMD1 P22/TOQ1T2 PDL6 P21/TOQ1B1 PDL7 P20/TOQ1T1 ANI13 ANI12 FLMD0 ANI11 P10/TOQH01/TIQ01/TOQ01 ANI10 P11/TIQ02/TOQ02 P12/TOQH02/TIQ03/TOQ03 REF1 P13/TIQ00 P14/TOQH03/EVTQ0 Note Note...
Page 21 CHAPTER 1 INTRODUCTION Pin Identification ADTRG0, ADTRG1: A/D trigger input SCKB0: Serial clock ANI00 to ANI03, SIB0: Serial input ANI10 to ANI13: Analog input SOB0: Serial output , AV Analog power supply TIP00, TIP01, , AV Analog reference voltage TIP20, TIP21, REF0 REF1 , AV...
Page 22 CHAPTER 1 INTRODUCTION 1.6 Function Blocks (1) Internal block diagram INTC INTP0 to INTP6 Instruction queue Multiplier × 1 ch (16 × 16 → 32) 32-bit barrel shifter TIQ00 to TIQ03, EVTQ0, TOQ1OFF, TOQH0OFF System TOQ00 to TOQ03, TOQ10, TOQH01 to TOQH03, ×...
Page 23 CHAPTER 1 INTRODUCTION (2) Internal units (a) CPU The CPU uses five-stage pipeline control to enable single-clock execution of address calculations, arithmetic logic operations, data transfers, and almost all other instruction processing. Other dedicated on-chip hardware, such as a multiplier (16 bits × 16 bits → 32 bits) and a barrel shifter (32 bits), help accelerate complex processing.
Page 24 CHAPTER 1 INTRODUCTION (i) Serial interface The V850ES/IE2 includes two asynchronous serial interface A (UARTA) channels and one 3-wire variable length serial I/O (CSIB) channel as the serial interface. For UARTA, data is transferred via the TXDAn and RXDAn pins (n = 0, 1).
Page 25 CHAPTER 2 PIN FUNCTIONS 2.1 List of Pin Functions The names and functions of the pins in the V850ES/IE2 are listed below. These pins can be divided into port pins and non-port pins according to their function. There are two power supplies for the I/O buffer of a pin: power supply for A/D converter (AV...
Page 26 CHAPTER 2 PIN FUNCTIONS (2/2) Pin Name Pin No. Function Alternate Function Port 2 TOQ1T1 8-bit I/O port TOQ1B1 Input data read/output data write is enabled in 1-bit units. TOQ1T2 Use of an on-chip pull-up resistor can be specified in 1-bit units (the on-chip pull-up resistor can be connected only in TOQ1B2 the input mode of the port mode, or when TOQ1T1 to...

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