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M16C/64A Group
27.7
Notes on A/D Converter
27.7.1
Analog Input Voltage
Set the analog input voltage as follows:
analog input voltage (AN_0 to AN_7, ANEX0, and ANEX1) ≤ VCC1
analog input voltage (AN0_0 to AN0_7 and AN2_7 to AN2_7) ≤ VCC2
27.7.2
Analog Input Pin
Do not use any pin from AN4 to AN7 as analog input pin if any pin from KI0 to KI3 is used as a key input
interrupt.
27.7.3
Pin Configuration
To prevent operation errors due to noise or latchup, and to reduce conversion errors, place capacitors
between the AVSS pin and the AVCC pin, the VREF pin, and analog inputs (ANi (i = 0 to 7), ANEXi,
AN0_i, and AN2_i). Also, place a capacitor between the VCC1 pin and VSS pin.
VCC1
C4
VCC2
C5
Notes:
1. Reference values: C1
2. The traces for the capacitor and MCU should be short and wide as much as physically possible.
Figure 27.17 Example of Pin Configuration
27.7.4
Register Access
Write registers ADCON0 (excluding the ADST bit), ADCON1, and ADCON2 when A/D conversion
stops (before a trigger is generated).
After A/D conversion stops, set the ADSTBY bit in the ADCON1 register from 1 to 0.
27.7.5
A/D Conversion Start
When rewriting the ADSTBY bit in the ADCON1 register from 0 (A/D operation stopped) to 1 (A/D
operation enabled), wait for one φ AD cycle or more before starting A/D conversion.
27.7.6
A/D Operation Mode Change
When the A/D operation mode has been changed, reselect analog input pins by using bits CH2 to CH0
in the ADCON0 register or bits SCAN1 to SCAN0 in the ADCON1 register.
R01UH0136EJ0210 Rev.2.10
Jul 31, 2012
MCU
AVCC
VCC1
VREF
VSS
C1
AVSS
VCC2
ANi
VSS
ANi: ANi (i = 0 to 7), AN0_i, AN2_i, ANEXi
≥
≥
0.1 μ F, C2
VCC1
C2
C3
≥
≥
0.1 μ F, C3
100 pF, C4
27. A/D Converter
≥
0.1 μ F, C5
0.1 μ F.
Page 645 of 800
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