Renesas M16C/64A Series User Manual page 539

M16C/64A Group
(1) ABSCS bit in UiSMR register (bus collision detect sampling clock select)
Transmit/receive clock
TXDi
RXDi
Timer Aj
(2) ACSE bit in UiSMR register (transmit enable bit automatically cleared)
Transmit/receive clock
TXDi
RXDi
IR bit in registers
UiBCNIC and BCNIC
TE bit in the UiC1
register
(3) SSS bit in the UiSMR register (transmit start condition select)
When the SSS bit is 0, the serial interface starts sending data one transmit/receive clock cycle after the transmission
start condition is met.
Transmit/receive clock
TXDi
Transmit enable conditions are met.
When the SSS bit is 1, the serial interface starts sending data at the rising edge of RXDi.
CLKi
TXDi
RXDi
i = 0 to 2, 5 to 7
The above diagram applies when IOPOL is 1 (reversed).
Notes:
1. The falling edge of RXDi when the IOPOL bit in the UiMR register is 0; the rising edge of RXDi when the IOPOL bit is 1.
2. The transmit conditions must be met before the falling edge of RXD.
Figure 23.34 Bus Collision Detect Function-Related Bits
R01UH0136EJ0210 Rev.2.10
Jul 31, 2012
When ABSCS is 0, bus collision is determined at the rising edge of the transmit/receive clock.
ST D0 D1
Trigger signal is applied to the TAjIN pin
When ABSCS is 1, bus collision is determined when timer Aj (one-shot timer mode) underflows.
Timer Aj: Timer A3 in UART0; timer A4 in UART1; timer A0 in UART2
timer A0 in UART5; timer A3 in UART6; timer A4 in UART7
ST D0 D1
ST D0
ST D0
(2)
23. Serial Interface UARTi (i = 0 to 2, 5 to 7)
D2 D3 D4 D5
D2 D3 D4 D5
D1 D2 D3 D4
D1 D2 D3 D4
(i = 0 to 2, 5 to 7)
D6 D7 D8 SP
D6 D7 D8 SP
When the ACSE bit is 1 (auto
clear at bus collision), the TE bit
is cleared to 0.
(transmission disabled) when the
IR bit in the UiBCNIC register is 1
(unmatching detected).
D5 D6 D7 D8
(1)
D5 D6 D7 D8
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