Renesas M16C/64A Series User Manual page 635

M16C/64A Group
CEC input
(input data: 0)
CEC input
(input data: 1)
Figure 26.7 Data Bit Acceptable Range (CRRNG Bit = 1)
26.3.5.3 Error Determination
If the data bit is out of the acceptable range, a receive error occurs. The operations when the receive
error occurs are as follows:
•
The CRERRFLG bit in the CECFLG register becomes 1 (receive error)
•
A 3.6 ms low-level pulse is output when the CABTEN bit in the CECC4 register is 1 (low pulse
output enabled in receive error). However, this pulse is not output if an error occurs in the start bit.
Low pulse output timing can be selected by setting the CABTWEN bit in the CECC4 register when
the CABTEN bit is 1 (low pulse output enabled in receive error).
R01UH0136EJ0210 Rev.2.10
Jul 31, 2012
When the CDATRNG bit is 0: ±200 µs
When the CDATRNG bit is 1: ±300 µs
0 ms
Acceptable range
When the CDATRNG bit is 0: ±200 µs
When the CDATRNG bit is 1: ±300 µs
0 ms
CRRNG, CDATRNG: Bits in the CECC2 register
26. Consumer Electronics Control (CEC) Function
Both edges are detected
Acceptable range
1.5 ms
Both edges are detected
0.6 ms
Acceptable range
±350 µs
±500 µs
2.4 ms
Acceptable range
±350 µs
±500 µs
2.4 ms
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