Notes On Programmable I/O Ports; Influence Of Sd; Influence Of Si/O3 And Si/O4 - Renesas M16C/64A Series User Manual

M16C/64A Group
13.6

Notes on Programmable I/O Ports

Influence of SD

13.6.1
When a low-level signal is applied to the SD pin while the IVPCR1 bit in the TB2SC register is 1 (three-
phase output forcible cutoff by input on SD pin enabled), the following pins become high-impedance:
P7_2/CLK2/TA1OUT/V, P7_3/ CTS2 / RTS2 /TA1IN/ V , P7_4/TA2OUT/W,
P7_5/TA2IN/ W , P8_0/TA4OUT/RXD5/SCL5/U, P8_1/TA4IN/ CTS5 / RTS5 / U
13.6.2

Influence of SI/O3 and SI/O4

When the SMi2 bit in the SiC register is set to 1 (SOUTi output disabled), the target pin becomes high-
impedance regardless of which pin function being used.
R01UH0136EJ0210 Rev.2.10
Jul 31, 2012
13. Programmable I/O Ports
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