Channel Priority And Dma Transfer Timing - Renesas M16C/64A Series User Manual

M16C/64A Group
16.3.7

Channel Priority and DMA Transfer Timing

If multiple channels among DMA0 to DMA3 are enabled and DMA transfer request signals are detected
as active in the same sampling period (one period from a falling edge to the next falling edge of BCLK),
the DMAS bit on each channel becomes 1 (DMA requested) at the same time. In this case, the DMA
requests are arbitrated according to the following channel priority: DMA0 > DMA1 > DMA2 > DMA3.
DMAC operation when DMA0 and DMA1 requests are detected as active in the same sampling period
is described below. Figure 16.5 shows an example of DMA Transfer Initiated by External Sources.
In Figure 14.5, as DMA0 and DMA1 requests are generated simultaneously, the higher channel
prioritized DMA0 is received first, and data transfer starts. After one DMA0 transfer is completed, the
bus access privilege is returned to the CPU. When the CPU has completed one bus access, a DMA1
transfer starts. After one DMA1 transfer is completed, the bus access privilege is again returned to the
CPU.
In addition, DMA requests cannot increment since each channel has one DMAS bit. Therefore, when
DMA requests, such as DMA1 in Figure 16.5, occur more than once, the DMAS bit is set to 0 after
receiving the bus access privilege. The bus access privilege is returned to the CPU when one transfer
is completed.
Example when DMA requests from external sources are detected active at the same
time and a DMA transfer is executed in the shortest cycle
BCLK
DMA0
DMA1
CPU
INT0
DMAS bit in the
DM0CON register
INT1
DMAS bit in the
DM1CON register
Figure 16.5 DMA Transfer Initiated by External Sources
R01UH0136EJ0210 Rev.2.10
Jul 31, 2012
16. DMAC
Bus
access
privilege
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