Nmi/Sd Digital Filter; Cnvss Pin - Renesas M16C/64A Series User Manual

M16C/64A Group

NMI/SD Digital Filter

13.4.3
The NMI / SD input function includes a digital filter. A sampling clock can be selected by bits NMIDF2 to
NMIDF0 in the NMIDF register. The NMI level is sampled for every sampling clock. When the same
sampled level is detected three times in a row, the level is transferred to the internal circuit.
When using the NMI / SD digital filter, do not enter wait mode or stop mode.
Port P8_5 is not affected by the digital filter.
Figure 13.13 shows NMI / SD Digital Filter, and Figure 13.14 shows NMI / SD Digital Filter Operation
Example.
CPU clock
P8_5/ NMI / SD /CEC
PM24: Bit in the PM2 register
NMIDF2 to NMIDF0: Bits in the NMIDF register
Figure 13.13 NMI/SD Digital Filter
Sampling timing
NMI/SD input
The above diagram assumes bits NMIDF2 to NMIDF0 in the NMIDF register are set to a value
other than 000b (NMI/SD filter enabled).
Figure 13.14 NMI/SD Digital Filter Operation Example
13.4.4

CNVSS Pin

The built-in pull-up resistor of the CNVSS pin is activated after watchdog timer reset, hardware reset,
power-on reset, or voltage monitor 0 reset. Thus, the CNVSS pin outputs a high-level signal up to two
cycles of fOCO-S. Connect the CNVSS pin to VSS via a resistor to use it in single-chip mode.
R01UH0136EJ0210 Rev.2.10
Jul 31, 2012
NMIDF2 to NMIDF0
Sampling clock
Divider
Digital Filter
NMI/SD pin
Level matches three times
NMIDF2 to NMIDF0
Other than 000b
000b
An NMI interrupt is generated when the PM24 bit in
the PM2 register is 1 (NMI interrupt enabled).
13. Programmable I/O Ports
PM24
NMI interrupt
SD input
CEC input
P8_5 input
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