Renesas M16C/60 Series Hardware Manual
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Renesas M16C/60 Series Hardware Manual

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REJ09B0011-0100Z
16
Before using this material, please visit our website to confirm that this is the most
current document available.
Rev. 1.00
Revision date: May 30, 2003
M16C/6N5 Group
RENESAS 16-BIT SINGLE-CHIP MICROCOMPUTER
M16C FAMILY / M16C/60 SERIES
Hardware Manual
www.renesas.com

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  • Page 1 REJ09B0011-0100Z M16C/6N5 Group Hardware Manual RENESAS 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/60 SERIES Before using this material, please visit our website to confirm that this is the most current document available. Rev. 1.00 Revision date: May 30, 2003 www.renesas.com...
  • Page 2 • The prior written approval of Renesas Technology Corporation is necessary to reprint or reproduce in whole or in part these materials.

  • Page 3: How To Use This Manual

    How to Use This Manual This hardware manual provides detailed information on features in the M16C/6N5 Group microcomputer. Users are expected to have basic knowledge of electric circuits, logical circuits and microcomputer. Each register diagram contains bit functions with the following symbols and descriptions. XXX register Symbol Address...
  • Page 4 M16C Family Documents The following document is prepared with the M16C family. Document Contents Short Sheet Hardware overview Data Sheet Hardware overview and electrical characteristics Hardware Manual Hardware specifications (pin assignments, memory maps, specifications of peripheral functions, electrical characteristics, timing charts) Software Manual Detailed description about instructions and microcomputer performance by each instruction...

  • Page 5: Table Of Contents

    Table of Contents Quick Reference to Pages Classified by Address Overview ........................... 1 Applications ................................ 1 Performance Outline ............................2 Block Diagram ..............................3 Product List ................................ 4 Pin Configuration ............................... 5 Pin Description ..............................6 Memory ............................. 8 Central Processing Unit (CPU) ....................9 (1) Data Registers (R0, R1, R2, and R3) ......................
  • Page 6 Clock Generation Circuit ......................42 (1) Main Clock ............................. 50 (2) Sub Clock .............................. 51 (3) Ring Oscillator Clock ..........................52 (4) PLL Clock .............................. 52 CPU Clock and Peripheral Function Clock ...................... 54 (1) CPU Clock and BCLK ..........................54 (2) Peripheral Function Clock (f ) ...........
  • Page 7 Serial I/O ..........................133 UARTi (i = 0 to 2) ............................133 Clock Synchronous Serial I/O Mode ......................142 Clock Asynchronous Serial I/O (UART) Mode ..................149 Special Mode 1 (I C Mode) ........................156 Special Mode 2 ............................165 Special Mode 3 (IE Mode) ........................
  • Page 8 Package Dimension ......................288 Register Index ........................289 M16C/6N5 Group Usage Note Reference Book For the most current Usage Notes Reference Book, please visit our website. Specifications written in this manual are believed to be accurate, but are not guaranteed to be entirely free of error.

  • Page 9: Quick Reference To Pages Classified By Address

    Quick Reference to Pages Classified by Address Address Register Symbol Page Address Register Symbol Page 0000 0040 0001 0041 CAN0 wake up interrupt control register C01WKIC 0002 0042 CAN0 successful reception interrupt control register C0RECIC 0003 0043 CAN0 successful transmission interrupt control register C0TRMIC 0004 Processor mode register 0...
  • Page 10 Address Register Symbol Page Address Register Symbol Page 0080 00C0 0081 00C1 0082 00C2 CAN0 message box 6: Identifier / DLC CAN0 message box 2: Identifier / DLC 0083 00C3 0084 00C4 0085 00C5 0086 00C6 0087 00C7 0088 00C8 0089 00C9 CAN0 message box 6: Data field...
  • Page 11 Address Register Symbol Page Address Register Symbol Page 0100 0140 0101 0141 0102 0142 CAN0 message box 14: Identifier /DLC CAN0 message box 10: Identifier / DLC 0103 0143 0104 0144 0105 0145 0106 0146 0107 0147 0108 0148 0109 0149 CAN0 message box 14: Data field CAN0 message box 10: Data field...
  • Page 12 Address Register Symbol Page Address Register Symbol Page 0180 01C0 Timer B3,4,5 count start flag TBSR 0181 01C1 0182 01C2 Timer A1-1 register TA11 0183 01C3 0184 01C4 Timer A2-1 register TA21 0185 01C5 0186 01C6 Timer A4-1 register TA41 0187 01C7 Three-phase PWM control register 0...
  • Page 13 Address Register Symbol Page Address Register Symbol Page 0200 CAN0 message control register 0 0240 C0MCTL0 CAN0 message control register 1 0201 C0MCTL1 0241 CAN0 message control register 2 0202 C0MCTL2 0242 CAN0 acceptance filter support register C0AFS CAN0 message control register 3 0203 C0MCTL3 0243...
  • Page 14 Address Register Symbol Page Address Register Symbol Page 0380 Count start flag TABSR 101,116,129 03C0 A-D register 0 Clock prescaler reset flag 0381 CPSRF 102,116 03C1 One-shot start flag 0382 ONSF 03C2 A-D register 1 Trigger select register 0383 TRGSR 102,129 03C3 Up-down flag...

  • Page 15: Overview

    The M16C/6N5 group of single-chip microcomputers are built using the high-performance silicon gate CMOS process using an M16C/60 Series CPU core and are packaged in a 100-pin plastic molded QFP. These single-chip microcomputers operate using sophisticated instructions featuring a high level of instruction efficiency.

  • Page 16: Performance Outline

    Under development This document is under development and its contents are subject to change. M16C/6N5 Group Overview Performance Outline Table 1.1.1 lists a performance outline of M16C/6N5 group. Table 1.1.1 Performance outline of M16C/6N5 Group Item Performance Number of basic instructions 91 instructions Shortest instruction execution time 50.0 ns (f(BCLK)=20MHz, 1/1 prescaler, without software wait)

  • Page 17: Block Diagram

    Input (timer B): 6 (8 bits ✕ 1 channel) CAN module CRC arithmetic circuit (CCITT) Three-phase motor control circuit (1 channel) (Polynomial: X Watchdog timer M16C/60 series CPU core Memory (15 bits) (128 Kbytes) DMAC (5 Kbytes) (2 channels) INTB Multiplier D-A converter (8 bits ✕...

  • Page 18: Product List

    Under development This document is under development and its contents are subject to change. M16C/6N5 Group Overview Product List Table 1.1.2 lists the M16C/6N5 group products and Figure 1.1.2 shows the type numbers, memory sizes and packages. As of May 2003 Table 1.1.2 Product List Type No.

  • Page 19: Pin Configuration

    Under development This document is under development and its contents are subject to change. M16C/6N5 Group Overview Pin Configuration Figures 1.1.3 shows the pin configuration (top view). PIN CONFIGURATION (top view) /CS0 /CS1 /CS2 /CS3 /WRL/WR /WRH/BHE /BCLK /HLDA M16C/6N5 Group /HOLD /ALE /RDY/CLK...

  • Page 20: Pin Description

    Under development This document is under development and its contents are subject to change. M16C/6N5 Group Overview Pin Description Tables 1.1.3 and 1.1.4 list the pin descriptions. Table 1.1.3 Pin Description (1) Pin name Signal name I/O type Function Power supply Apply 4.2 V to 5.5 V to the V and V pins and 0 V to the V...
  • Page 21 Under development This document is under development and its contents are subject to change. M16C/6N5 Group Overview Table 1.1.4 Pin Description (2) Pin name Signal name I/O type Function to P5 I/O port P5 Input/output This is an 8-bit I/O port equivalent to P0. In single-chip mode, P5 in this port outputs a divide-by-8 or divide-by-32 clock of X or a clock of the...

  • Page 22: Memory

    Under development This document is under development and its contents are subject to change. M16C/6N5 Group Memory Memory Figure 1.2.1 shows a memory map of the M16C/6N5 group. The address space extends the 1 Mbyte from address 00000 to FFFFF The internal ROM is allocated in a lower address direction beginning with address FFFFF .

  • Page 23: Central Processing Unit (Cpu)

    Under development This document is under development and its contents are subject to change. M16C/6N5 Group Central Processing Unit (CPU) Figure 1.3.1 shows the CPU registers. The CPU has 13 registers. Of these, R0, R1, R2, R3, A0, A1 and FB comprise a register bank.

  • Page 24: Frame Base Register (Fb)

    Under development This document is under development and its contents are subject to change. M16C/6N5 Group (3) Frame Base Register (FB) FB is configured with 16 bits, and is used for FB relative addressing. (4) Interrupt Table Register (INTB) INTB is configured with 20 bits, indicating the start address of an interrupt vector table. (5) Program Counter (PC) PC is configured with 20 bits, indicating the address of an instruction to be executed.

  • Page 25: Sfr

    Under development This document is under development and its contents are subject to change. M16C/6N5 Group Figures 1.4.1 to 1.4.12 show the location of peripheral function control registers and the value after reset. Address Register Symbol After reset 0000 0001 0002 0003 00000000...
  • Page 26 Under development This document is under development and its contents are subject to change. M16C/6N5 Group Address Register Symbol After reset 0040 CAN0 wake up interrupt control register C01WKIC XXXXX000 0041 CAN0 successful reception interrupt control register C0RECIC XXXXX000 0042 CAN0 successful transmission interrupt control register C0TRMIC XXXXX000...
  • Page 27 Under development This document is under development and its contents are subject to change. M16C/6N5 Group Address Register Symbol After reset 0080 0081 0082 CAN0 message box 2: Identifier / DLC 0083 0084 0085 0086 0087 0088 0089 CAN0 message box 2: Data field 008A 008B 008C...
  • Page 28 Under development This document is under development and its contents are subject to change. M16C/6N5 Group Address Register Symbol After reset 00C0 00C1 00C2 CAN0 message box 6: Identifier / DLC 00C3 00C4 00C5 00C6 00C7 00C8 00C9 CAN0 message box 6: Data field 00CA 00CB 00CC...
  • Page 29 Under development This document is under development and its contents are subject to change. M16C/6N5 Group Address Register Symbol After reset 0100 0101 0102 CAN0 message box 10: Identifier / DLC 0103 0104 0105 0106 0107 0108 0109 CAN0 message box 10: Data field 010A 010B 010C...
  • Page 30 Under development This document is under development and its contents are subject to change. M16C/6N5 Group Address Register Symbol After reset 0140 0141 0142 CAN0 message box 14: Identifier /DLC 0143 0144 0145 0146 0147 0148 0149 CAN0 message box 14: Data field 014A 014B 014C...
  • Page 31 Under development This document is under development and its contents are subject to change. M16C/6N5 Group Address Register Symbol After reset 0180 0181 0182 0183 0184 0185 0186 0187 0188 0189 018A 018B 018C 018D 018E 018F 0190 0191 0192 0193 0194 0195...
  • Page 32 Under development This document is under development and its contents are subject to change. M16C/6N5 Group Address Register Symbol After reset 000XXXXX 01C0 Timer B3,4,5 count start flag TBSR 01C1 01C2 Timer A1-1 register TA11 01C3 01C4 Timer A2-1 register TA21 01C5 01C6...
  • Page 33 Under development This document is under development and its contents are subject to change. M16C/6N5 Group Address Register Symbol After reset 0200 CAN0 message control register 0 C0MCTL0 CAN0 message control register 1 C0MCTL1 0201 CAN0 message control register 2 C0MCTL2 0202 CAN0 message control register 3...
  • Page 34 Under development This document is under development and its contents are subject to change. M16C/6N5 Group Address Register Symbol After reset 0240 0241 0242 CAN0 acceptance filter support register C0AFS 0243 0244 0245 0246 0247 0248 0249 024A 024B 024C 024D 024E 024F...
  • Page 35 Under development This document is under development and its contents are subject to change. M16C/6N5 Group Address Register Symbol After reset 0380 Count start flag TABSR 0XXXXXXX 0381 Clock prescaler reset flag CPSRF One-shot start flag 0382 ONSF Trigger select register 0383 TRGSR Up-down flag...
  • Page 36 Under development This document is under development and its contents are subject to change. M16C/6N5 Group Address Register Symbol After reset 03C0 A-D register 0 03C1 03C2 A-D register 1 03C3 03C4 A-D register 2 03C5 03C6 A-D register 3 03C7 03C8 A-D register 4...

  • Page 37: Reset

    Under development This document is under development and its contents are subject to change. M16C/6N5 Group Reset Reset There are four types of resets: a hardware reset, a software reset, an watchdog timer reset, and an oscillation stop detection reset. Hardware Reset ____________ ____________...
  • Page 38 Under development This document is under development and its contents are subject to change. M16C/6N5 Group Reset Re c o m m e n d e d o p e r a t i n g v o l t a g e C C 1 R E S E T R E S E T...
  • Page 39 Under development This document is under development and its contents are subject to change. M16C/6N5 Group Reset ____________ Table 1.5.1 Pin Status When RESET Pin Level is “L” Status Pin name (Note) BYTE = V BYTE = V Input port Data input Data input Input port...

  • Page 40: Processor Mode

    Under development This document is under development and its contents are subject to change. M16C/6N5 Group Processor Mode Processor Mode (1) Types of Processor Mode Three processor modes are available to choose from: single-chip mode, memory expansion mode, and microprocessor mode. Table 1.6.1 shows the features of these processor modes. Table 1.6.1 Features of Processor Modes Processor mode Access space...
  • Page 41 Under development This document is under development and its contents are subject to change. M16C/6N5 Group Processor Mode Processor mode register 0 (Note 1) Symbol Address After reset (Note 2) 0004 00000000 (CNV pin = L) 00000011 (CNV pin = H) Bit symbol Bit name Function...
  • Page 42 Under development This document is under development and its contents are subject to change. M16C/6N5 Group Processor Mode Processor mode register 1 (Note 1) Symbol Address After reset 0005 0XXX1000 Bit symbol Bit name Function (block A disable) area switch bit 0 : 08000 to 26FFF (block A enable)
  • Page 43 Under development This document is under development and its contents are subject to change. M16C/6N5 Group Processor Mode Single-chip mode 00000 00400 Internal RAM XXXXX Can not use PM13 = 0 YYYYY Internal RAM Internal ROM Internal ROM Capacity Address XXXXX Capacity Address YYYYY 5 Kbytes...
  • Page 44 Under development This document is under development and its contents are subject to change. M16C/6N5 Group Processor Mode When PM13 = 0 and PM10 = 0 (A memory space of 1MB) Memory expansion mode Microprocessor mode 00000 00400 Internal RAM Internal RAM XXXXX Reserved area...

  • Page 45: Bus

    Under development This document is under development and its contents are subject to change. M16C/6N5 Group During memory expansion or microprocessor mode, some pins serve as the bus control pins to perform _______ data input/output to and from external devices. These bus control pins include A to A to D , CS...

  • Page 46: Bus Control

    Under development This document is under development and its contents are subject to change. M16C/6N5 Group Bus Control Bus Control The following describes the signals needed for accessing external devices and the functionality of software wait. Table 1.7.1 PM06 and PM11 Bits Set Value and (1) Address Bus Address Bus Width The address bus consists of 20 lines, A...
  • Page 47 Under development This document is under development and its contents are subject to change. M16C/6N5 Group Bus Control Example 1 Example 2 To access the external area indicated by CS in the next cycle To access the internal ROM or internal RAM in the next cycle after accessing the external area indicated by CS after accessing the external area indicated by CS The address bus and the chip select signal both change state...

  • Page 48: Read And Write Signals

    Under development This document is under development and its contents are subject to change. M16C/6N5 Group Bus Control (4) Read and Write Signals _____ When the data bus is 16-bit width, the read and write signals can be chosen to be a combination of RD, ______ ________ _____...

  • Page 49: The Rdy Signal

    Under development This document is under development and its contents are subject to change. M16C/6N5 Group Bus Control ________ (6) The RDY Signal This signal is provided for accessing external devices which need to be accessed at low speed. If input on ________ the RDY pin is asserted low at the last falling edge of BCLK of the bus cycle, one wait state is inserted in ________...

  • Page 50: Hold Signal

    Under development This document is under development and its contents are subject to change. M16C/6N5 Group Bus Control __________ (7) HOLD Signal This signal is used to transfer control of the bus from CPU or DMAC to an external circuit. When the input __________ on HOLD pin is pulled low, the microcomputer is placed in a hold state after the bus access then in __________...
  • Page 51 Under development This document is under development and its contents are subject to change. M16C/6N5 Group Bus Control Table 1.7.5 Pin Functions for Each Processor Mode Processor mode Memory expansion mode or microprocessor mode Memory expansion mode ______ is for multiplexed bus and 11 (multiplexed bus others are for separate bus) for the entire space)

  • Page 52: External Bus Status When Internal Area Accessed

    Under development This document is under development and its contents are subject to change. M16C/6N5 Group Bus Control (9) External Bus Status When Internal Area Accessed Table 1.7.6 shows the external bus status when the internal area is accessed. Table 1.7.6 External Bus Status When Internal Area Accessed Item SFR accessed Internal ROM, internal RAM accessed...
  • Page 53 Under development This document is under development and its contents are subject to change. M16C/6N5 Group Bus Control Table 1.7.7 Software Wait Related Bits and Bus Cycles CSR register CSE register CS3W bit (Note 1) CS31W to CS30W bits PM2 Register PM1 Register Software Area...
  • Page 54 Under development This document is under development and its contents are subject to change. M16C/6N5 Group Bus Control (1) Separate bus, No wait setting Bus cycle (Note) Bus cycle (Note) BCLK Write signal Read signal Data bus Output Input Address bus Address Address (2) Separate bus, 1-wait setting...
  • Page 55 Under development This document is under development and its contents are subject to change. M16C/6N5 Group Bus Control (1) Separate bus, 3-wait setting Bus cycle (Note) Bus cycle (Note) BCLK Write signal Read signal Data bus Input Output Address Address Address bus (2)Multiplexed bus, 1- or 2-wait setting Bus cycle (Note)

  • Page 56: Clock Generation Circuit

    Under development This document is under development and its contents are subject to change. M16C/6N5 Group Clock Generation Circuit Clock Generation Circuit The clock generation circuit contains four oscillator circuits as follows: (1) Main clock oscillation circuit (2) Sub clock oscillation circuit (3) Ring oscillator (4) PLL frequency synthesizer Table 1.8.1 lists the clock generation circuit specifications.
  • Page 57 Under development This document is under development and its contents are subject to change. M16C/6N5 Group Clock Generation Circuit CM01-CM00=00 Sub clock oscillation circuit I/O ports PM01-PM00=00 , CM01-CM00=01 COUT PM01-PM00=00 , CM01-CM00=10 PM01-PM00=00 CM01-CM00=11 CM04 1/32 Sub clock CAN0 By CCLK0,1 and 2 PCLK0=1 PCLK0=0...
  • Page 58 Under development This document is under development and its contents are subject to change. M16C/6N5 Group Clock Generation Circuit System clock control register 0 (Note 1) Symbol Address After reset 0006 01001000 Bit symbol Bit name Function b1 b0 Clock output function CM00 0 0 : I/O port P5 select bit...
  • Page 59 Under development This document is under development and its contents are subject to change. M16C/6N5 Group Clock Generation Circuit System clock control register 1 (Note 1) Symbol Address After reset 0007 00100000 Bit symbol Bit name Function All clock stop control bit 0 : Clock on CM10 (Notes 2, 3)
  • Page 60 Under development This document is under development and its contents are subject to change. M16C/6N5 Group Clock Generation Circuit Oscillation stop detection register (Note 1) Symbol Address After reset 000C 0X00X000 (Note 2) Bit symbol Bit name Function 0 : Oscillation stop, re-oscillation Oscillation stop, re-oscillation detection function disabled detection enable bit...
  • Page 61 Under development This document is under development and its contents are subject to change. M16C/6N5 Group Clock Generation Circuit Peripheral clock select register (Note) Symbol Address After reset PCLKR 025E Bit name Function Bit symbol 0 : Divide-by-2 of f Timers A, B, and A-D clock select bit 1 : f PCLK0...
  • Page 62 Under development This document is under development and its contents are subject to change. M16C/6N5 Group Clock Generation Circuit Processor mode register 2 (Note 1) Symbol Address After reset 001E XXX00000 Bit symbol Bit name Function Specifying wait when 0 : 2 waits accessing SFR at PLL 1 : 1 wait PM20...
  • Page 63 Under development This document is under development and its contents are subject to change. M16C/6N5 Group Clock Generation Circuit PLL control register 0 (Note 1) Symbol Address After reset PLC0 001C 0001X010 Bit symbol Bit name Function b2 b1 b0 0 0 0 : Must not be set PLC00 0 0 1 : Multiply by 2...

  • Page 64: Main Clock

    Under development This document is under development and its contents are subject to change. M16C/6N5 Group Clock Generation Circuit The following describes the clocks generated by the clock generation circuit. (1) Main Clock This clock is used as the clock source for the CPU and peripheral function clocks. The main clock oscilla- tor circuit is configured by connecting a resonator between the X and X pins.

  • Page 65: Sub Clock

    Under development This document is under development and its contents are subject to change. M16C/6N5 Group Clock Generation Circuit (2) Sub Clock The sub clock is generated by the sub clock oscillation circuit. This clock is used as the clock source for the CPU clock, as well as the timer A and timer B count sources.

  • Page 66: Ring Oscillator Clock

    Under development This document is under development and its contents are subject to change. M16C/6N5 Group Clock Generation Circuit (3) Ring Oscillator Clock This clock, approximately 1 MHz, is supplied by a ring oscillator. This clock is used as the clock source for the CPU and peripheral function clocks.
  • Page 67 Under development This document is under development and its contents are subject to change. M16C/6N5 Group Clock Generation Circuit Using the PLL clock as the clock source for the CPU Set the CM07 bit to "0" (main clock), the CM17 to CM16 bits to "00 "...

  • Page 68: Cpu Clock And Peripheral Function Clock

    Under development This document is under development and its contents are subject to change. M16C/6N5 Group Clock Generation Circuit CPU Clock and Peripheral Function Clock There are existing two type clocks: The CPU clock to operate the CPU and the peripheral function clocks to operate the peripheral functions.

  • Page 69: Power Control

    Under development This document is under development and its contents are subject to change. M16C/6N5 Group Clock Generation Circuit Power Control There are three power control modes. For convenience’ sake, all modes other than wait and stop modes are referred to as normal operation mode here. (1) Normal Operation Mode Normal operation mode is further classified into seven sub modes.
  • Page 70 Under development This document is under development and its contents are subject to change. M16C/6N5 Group Clock Generation Circuit • Ring Oscillator Mode The ring oscillator clock divided by 1 (undivided), 2, 4, 8 or 16 provides the CPU clock. The ring oscillator clock is also the clock source for the peripheral function clocks.

  • Page 71: Wait Mode

    Under development This document is under development and its contents are subject to change. M16C/6N5 Group Clock Generation Circuit (2) Wait Mode In wait mode, the CPU clock is turned off, so are the CPU (because operated by the CPU clock) and the watchdog timer.
  • Page 72 Under development This document is under development and its contents are subject to change. M16C/6N5 Group Clock Generation Circuit Table 1.8.5 Interrupts to Exit Wait Mode Interrupt CM02 = 0 CM02 = 1 _______ NMI interrupt Can be used Can be used Serial I/O interrupt Can be used when operating with Can be used when operating with...

  • Page 73: Stop Mode

    Under development This document is under development and its contents are subject to change. M16C/6N5 Group Clock Generation Circuit (3) Stop Mode In stop mode, all oscillator circuits are turned off, so are the CPU clock and the peripheral function clocks. Therefore, the CPU and the peripheral functions clocked by these clocks stop operating.
  • Page 74 Under development This document is under development and its contents are subject to change. M16C/6N5 Group Clock Generation Circuit • Exiting Stop Mode ______ The microcomputer is moved out of stop mode by a hardware reset, NMI interrupt or peripheral function interrupt.

  • Page 75: Normal Mode

    Under development This document is under development and its contents are subject to change. M16C/6N5 Group Clock Generation Circuit Figure 1.8.12 shows the state transition from normal operation mode to stop mode and wait mode. Figure 1.8.13 shows the state transition in normal operation mode. Table 1.8.7 shows a state transition matrix describing allowed transition and setting.
  • Page 76 Under development This document is under development and its contents are subject to change. M16C/6N5 Group Clock Generation Circuit Main clock oscillation Ring oscillator clock oscillation Ring oscillator low power Middle-speed mode Middle-speed mode Middle-speed mode PLL operation mode Middle-speed mode Ring oscillator mode PLC07=1 dissipation mode...
  • Page 77 Under development This document is under development and its contents are subject to change. M16C/6N5 Group Clock Generation Circuit Table 1.8.7 Allowed Transition and Setting State after transition High-speed mode, Low-speed Low power PLL operation Ring oscillator Ring oscillator Stop Wait middle-speed mode...

  • Page 78: Oscillation Stop And Re-Oscillation Detection Function

    Under development This document is under development and its contents are subject to change. M16C/6N5 Group Clock Generation Circuit Oscillation Stop and Re-oscillation Detection Function The oscillation stop and re-oscillation detection function is such that main clock oscillation circuit stop and re-oscillation are detected.
  • Page 79 Under development This document is under development and its contents are subject to change. M16C/6N5 Group Clock Generation Circuit How to Use Oscillation Stop and Re-oscillation Detection Function • The oscillation stop, re-oscillation detection interrupt shares the vector with the watchdog timer interrupt. If the oscillation stop, re-oscillation detection and watchdog timer interrupts both are used, read the CM22 bit in an interrupt routine to determine which interrupt source is requesting the interrupt.

  • Page 80: Protection

    Under development This document is under development and its contents are subject to change. M16C/6N5 Group Protection Protection In the event that a program runs out of control, this function protects the important registers so that they will not be rewritten easily. Figure 1.9.1 shows the PRCR register. The following lists the registers protected by the PRCR register.

  • Page 81: Interrupts

    Under development This document is under development and its contents are subject to change. M16C/6N5 Group Interrupts Interrupts Type of Interrupts Figure 1.10.1 shows the types of interrupts. Undefined instruction (UND instruction) Overflow (INTO instruction) Software BRK instruction (Non-maskable interrupt) INT instruction _______ Interrupt...

  • Page 82: Software Interrupts

    Under development This document is under development and its contents are subject to change. M16C/6N5 Group Interrupts Software Interrupts A software interrupt occurs when executing certain instructions. Software interrupts are non-maskable interrupts. • Undefined Instruction Interrupt An undefined instruction interrupt occurs when executing the UND instruction. •...

  • Page 83: Hardware Interrupts

    Under development This document is under development and its contents are subject to change. M16C/6N5 Group Interrupts Hardware Interrupts Hardware interrupts are classified into two types — special interrupts and peripheral function interrupts. (1) Special Interrupts Special interrupts are non-maskable interrupts. _______ •...

  • Page 84: Interrupts And Interrupt Vector

    Under development This document is under development and its contents are subject to change. M16C/6N5 Group Interrupts Interrupts and Interrupt Vector One interrupt vector consists of 4 bytes. Set the start address of each interrupt routine in the respective interrupt vectors. When an interrupt request is accepted, the CPU branches to the address set in the corresponding interrupt vector.
  • Page 85 Under development This document is under development and its contents are subject to change. M16C/6N5 Group Interrupts • Relocatable Vector Tables The 256 bytes beginning with the start address set in the INTB register comprise a relocatable vector table area. Table 1.10.2 lists the relocatable vector tables. Setting an even address in the INTB register results in the interrupt sequence being executed faster than in the case of odd addresses.

  • Page 86: Interrupt Control

    Under development This document is under development and its contents are subject to change. M16C/6N5 Group Interrupts Interrupt Control The following describes how to enable/disable the maskable interrupts, and how to set the priority in which order they are accepted. What is explained here does not apply to non-maskable interrupts. Use the FLG register’s I flag, IPL, and each interrupt control register’s ILVL2 to ILVL0 bits to enable/disable the maskable interrupts.
  • Page 87 Under development This document is under development and its contents are subject to change. M16C/6N5 Group Interrupts Interrupt control register (Note 1) Symbol Address After reset INT3IC (Note 2) 0044 XX00X000 INT5IC 0048 XX00X000 S3IC/INT4IC 0049 XX00X000 INT0IC to INT2IC 005D to 005F XX00X000...
  • Page 88 Under development This document is under development and its contents are subject to change. M16C/6N5 Group Interrupts I Flag The I flag enables or disables the maskable interrupt. Setting the I flag to “1” (enabled) enables the maskable interrupt. Setting the I flag to “0” (disabled) disables all maskable interrupts. IR Bit The IR bit is set to “1”...

  • Page 89: Interrupt Sequence

    Under development This document is under development and its contents are subject to change. M16C/6N5 Group Interrupts Interrupt Sequence An interrupt sequence — what are performed over a period from the instant an interrupt is accepted to the instant the interrupt routine is executed — is described here. If an interrupt occurs during execution of an instruction, the processor determines its priority when the execution of the instruction is completed, and transfers control to the interrupt sequence from the next cycle.

  • Page 90: Interrupt Response Time

    Under development This document is under development and its contents are subject to change. M16C/6N5 Group Interrupts Interrupt Response Time Figure 1.10.6 shows the interrupt response time. The interrupt response or interrupt acknowledge time denotes a time from when an interrupt request is generated till when the first instruction in the interrupt routine is executed.
  • Page 91 Under development This document is under development and its contents are subject to change. M16C/6N5 Group Interrupts Saving Registers In the interrupt sequence, the FLG register and PC are saved to the stack. At this time, the 4 high-order bits of the PC and the 4 high-order (IPL) and 8 low-order bits of the FLG register, 16 bits in total, are saved to the stack first.

  • Page 92: Interrupt Priority

    Under development This document is under development and its contents are subject to change. M16C/6N5 Group Interrupts Returning from an Interrupt Routine The FLG register and PC in the state in which they were immediately before entering the interrupt sequence are restored from the stack by executing the REIT instruction at the end of the interrupt routine. Thereafter the CPU returns to the program which was being executed before accepting the interrupt request.
  • Page 93 Under development This document is under development and its contents are subject to change. M16C/6N5 Group Interrupts Level 0 Priority level of each interrupt (initial value) Highest INT1 Timer B2 Timer B0 Timer A3 Timer A1 UART1 reception, ACK1 UART0 reception, ACK0 UART2 reception, ACK2 INT2 INT0...

  • Page 94: Int Interrupt

    Under development This document is under development and its contents are subject to change. M16C/6N5 Group Interrupts ______ INT Interrupt ________ INTi interrupt (i = 0 to 5) is triggered by the edges of external inputs. The edge polarity is selected using the IFSR1 register's IFSR1i bit.
  • Page 95 Under development This document is under development and its contents are subject to change. M16C/6N5 Group Interrupts Interrupt request cause select register 0 Symbol Address After reset IFSR0 01DE 00XXX000 Bit name Function Bit symbol 0 : Inhibited IFSR00 Interrupt request cause select bit 1 : SI/O3 0 : A-D conversion IFSR01...

  • Page 96: Key Input Interrupt

    Under development This document is under development and its contents are subject to change. M16C/6N5 Group Interrupts ______ NMI Interrupt _______ _______ ______ An NMI interrupt request is generated when input on the NMI pin changes state from high to low. The NMI interrupt is a non-maskable interrupt.

  • Page 97: Address Match Interrupt

    Under development This document is under development and its contents are subject to change. M16C/6N5 Group Interrupts Address Match Interrupt An address match interrupt request is generated immediately before executing the instruction at the address indicated by the RMADi register (i = 0 to 3). Set the start address of any instruction in the RMADi register.
  • Page 98 Under development This document is under development and its contents are subject to change. M16C/6N5 Group Interrupts Address match interrupt enable register Symbol Address After reset AIER 0009 XXXXXX00 Bit symbol Bit name Function Address match interrupt 0 0 : Interrupt disabled AIER0 enable bit 1 : Interrupt enabled...

  • Page 99: Watchdog Timer

    Under development This document is under development and its contents are subject to change. M16C/6N5 Group Watchdog Timer Watchdog Timer The watchdog timer is the function of detecting when the program is out of control. Therefore, we recommend using the watchdog timer to improve reliability of a system. The watchdog timer contains a 15-bit counter which counts down the clock derived by dividing the CPU clock using the prescaler.
  • Page 100 Under development This document is under development and its contents are subject to change. M16C/6N5 Group Watchdog Timer Setting the PM22 bit to “1” results in the following conditions: • The ring oscillator starts oscillating, and the ring oscillator clock becomes the watchdog timer count source. Watchdog timer count (32768) Watchdog timer period = ring oscillator clock...

  • Page 101: Dmac

    Under development This document is under development and its contents are subject to change. M16C/6N5 Group DMAC DMAC The DMAC (Direct Memory Access Controller) allows data to be transferred without the CPU intervention. Two DMAC channels are included. Each time a DMA request occurs, the DMAC transfers one (8- or 16-bit) data from the source address to the destination address.
  • Page 102 Under development This document is under development and its contents are subject to change. M16C/6N5 Group DMAC Table 1.12.1 DMAC Specifications Item Specification No. of channels 2 (cycle steal method) Transfer memory space • From any address in the 1 Mbyte space to a fixed address •...
  • Page 103 Under development This document is under development and its contents are subject to change. M16C/6N5 Group DMAC DMA0 request cause select register Symbol Address After reset DM0SL 03B8 Bit symbol Bit name Function DSEL0 DSEL1 DMA request cause Refer to note select bit DSEL2 DSEL3...
  • Page 104 Under development This document is under development and its contents are subject to change. M16C/6N5 Group DMAC DMA1 request cause select register Symbol Address After reset DM1SL 03BA Bit symbol Bit name Function DSEL0 DSEL1 DMA request cause Refer to note select bit DSEL2 DSEL3...
  • Page 105 Under development This document is under development and its contents are subject to change. M16C/6N5 Group DMAC DMAi source pointer (i = 0, 1) (Note) (b23) (b19) (b16) (b15) (b8) Symbol Address After reset b0 b7 SAR0 0022 to 0020 Indeterminate SAR1 0032...

  • Page 106: Transfer Cycle

    Under development This document is under development and its contents are subject to change. M16C/6N5 Group DMAC 1. Transfer Cycle The transfer cycle consists of a memory or SFR read (source read) bus cycle and a write (destination write) bus cycle. The number of read and write bus cycles is affected by the source and destination addresses of transfer.
  • Page 107 Under development This document is under development and its contents are subject to change. M16C/6N5 Group DMAC (1) When the transfer unit is 8 or 16 bits and the source of transfer is an even address BCLK Address Dummy CPU use Source Destination CPU use...

  • Page 108: Dma Transfer Cycles

    Under development This document is under development and its contents are subject to change. M16C/6N5 Group DMAC 2. DMA Transfer Cycles Any combination of even or odd transfer read and write addresses is possible. Table 1.12.2 shows the number of DMA transfer cycles. Table 1.12.3 shows the coefficient j, k. The number of DMAC transfer cycles can be calculated as follows: No.

  • Page 109: Dma Enable

    Under development This document is under development and its contents are subject to change. M16C/6N5 Group DMAC 3. DMA Enable When a data transfer starts after setting the DMAE bit of the DMiCON register (i = 0, 1) to “1” (enabled), the DMAC operates as follows: (1) Reload the forward address pointer with the SARi register value when the DSD bit of the DMiCON register is “1”...

  • Page 110: Channel Priority And Dma Transfer Timing

    Under development This document is under development and its contents are subject to change. M16C/6N5 Group DMAC 5. Channel Priority and DMA Transfer Timing If both DMA0 and DMA1 are enabled and DMA transfer request signals from DMA0 and DMA1 are detected active in the same sampling period (one period from a falling edge to the next falling edge of BCLK), the DMAS bit on each channel is set to “1”...

  • Page 111: Timers

    Under development This document is under development and its contents are subject to change. M16C/6N5 Group Timers Timers Eleven 16-bit timers, each capable of operating independently of the others, can be classified by function as either timer A (five) and timer B (six). The count source for each timer acts as a clock, to control such timer operations as counting, reloading, etc.
  • Page 112 Under development This document is under development and its contents are subject to change. M16C/6N5 Group Timers PCLK0 bit = 0 Clock prescaler Main clock 1 or PLL clock 1/32 PCLK0 bit = 1 Ring oscillator Reset clock Set the CPSR bit of CPSRF register to "1"...

  • Page 113: Timer A

    Under development This document is under development and its contents are subject to change. M16C/6N5 Group Timer A Timer A Figure 1.13.3 shows a block diagram of the timer A. Figures 1.13.4 to 1.13.6 show the timer A-related registers. The timer A supports the following four modes. Except in event counter mode, timers A0 to A4 all have the same function.
  • Page 114 Under development This document is under development and its contents are subject to change. M16C/6N5 Group Timer A Timer Ai mode register (i = 0 to 4) Symbol Address After reset TA0MR to TA4MR 0396 to 039A Bit symbol Bit name Function b1 b0 0 0 : Timer mode...
  • Page 115 Under development This document is under development and its contents are subject to change. M16C/6N5 Group Timer A Count start flag Symbol Address After reset TABSR 0380 Bit symbol Bit name Function TA0S Timer A0 count start flag 0 : Stops counting 1 : Starts counting TA1S Timer A1 count start flag...
  • Page 116 Under development This document is under development and its contents are subject to change. M16C/6N5 Group Timer A One-shot start flag Symbol Address After reset ONSF 0382 Bit symbol Bit name Function TA0OS Timer A0 one-shot start flag The timer starts counting by setting this bit to "1"...

  • Page 117: Timer Mode

    Under development This document is under development and its contents are subject to change. M16C/6N5 Group Timer A 1. Timer Mode In timer mode, the timer counts a count source generated internally. Table 1.13.1 lists specifications in timer mode. Figure 1.13.7 shows TAiMR register in timer mode. Table 1.13.1.

  • Page 118: Event Counter Mode

    Under development This document is under development and its contents are subject to change. M16C/6N5 Group Timer A 2. Event Counter Mode In event counter mode, the timer counts pulses from an external device or overflows and underflows of other timers. Timers A2, A3 and A4 can count two-phase external signals. Table 1.13.2 lists specifications in event counter mode (when not processing two-phase pulse signal).
  • Page 119 Under development This document is under development and its contents are subject to change. M16C/6N5 Group Timer A Timer Ai mode register (i = 0 to 4) (When not using two-phase pulse signal processing) Symbol Address After reset TA0MR to TA4MR 0396 to 039A Bit symbol...
  • Page 120 Under development This document is under development and its contents are subject to change. M16C/6N5 Group Timer A Table 1.13.3 Specifications in Event Counter Mode (when processing two-phase pulse signal with timers A2, A3 and A4) Item Specification Count source •...
  • Page 121 Under development This document is under development and its contents are subject to change. M16C/6N5 Group Timer A Timer Ai mode register (i = 2 to 4) (When using two-phase pulse signal processing) Symbol Address After reset TA2MR to TA4MR 0398 to 039A Bit name...
  • Page 122 Under development This document is under development and its contents are subject to change. M16C/6N5 Group Timer A • Counter Initialization by Two-Phase Pulse Signal Processing This function initializes the timer count value to “0” by Z-phase (counter initialization) input during two- phase pulse signal processing.

  • Page 123: One-Shot Timer Mode

    Under development This document is under development and its contents are subject to change. M16C/6N5 Group Timer A 3. One-shot Timer Mode In one-shot timer mode, the timer is activated only once by one trigger. When the trigger occurs, the timer starts up and continues operating for a given period.
  • Page 124 Under development This document is under development and its contents are subject to change. M16C/6N5 Group Timer A Timer Ai mode register (i = 0 to 4) Symbol Address After reset TA0MR to TA4MR 0396 to 039A Bit symbol Bit name Function TMOD0 b1 b0...

  • Page 125: Pulse Width Modulation (Pwm) Mode

    Under development This document is under development and its contents are subject to change. M16C/6N5 Group Timer A 4. Pulse Width Modulation (PWM) Mode In PWM mode, the timer outputs pulses of a given width in succession. The counter functions as either 16-bit pulse width modulator or 8-bit pulse width modulator.
  • Page 126 Under development This document is under development and its contents are subject to change. M16C/6N5 Group Timer A Timer Ai mode register (i = 0 to 4) Symbol Address After reset TA0MR to TA4MR 0396 to 039A Bit symbol Bit name Function TMOD0 b1 b0...
  • Page 127 Under development This document is under development and its contents are subject to change. M16C/6N5 Group Timer A ✕ 1 / f — 1) Count source "H" Input signal to "L" Trigger is not generated by this signal ✕ 1 / f "H"...

  • Page 128: Timer B

    Under development This document is under development and its contents are subject to change. M16C/6N5 Group Timer B Timer B Figure 1.13.15 shows a block diagram of the timer B. Figures 1.13.16 and 1.13.17 show the timer B-related registers. Timer B supports the following three modes. Use the TMOD1 and TMOD0 bits of TBiMR register (i = 0 to 5) to select the desired mode.
  • Page 129 Under development This document is under development and its contents are subject to change. M16C/6N5 Group Timer B Timer Bi mode register (i = 0 to 5) Symbol Address After reset TB0MR to TB2MR 039B to 039D 00XX0000 TB3MR to TB5MR 01DB to 01DD 00XX0000...
  • Page 130 Under development This document is under development and its contents are subject to change. M16C/6N5 Group Timer B Count start flag Symbol Address After reset TABSR 0380 Bit name Function Bit symbol TA0S Timer A0 count start flag 0 : Stops counting 1 : Starts counting TA1S Timer A1 count start flag...

  • Page 131: Timer Mode

    Under development This document is under development and its contents are subject to change. M16C/6N5 Group Timer B 1. Timer Mode In timer mode, the timer counts a count source generated internally. Table 1.13.6 lists specifications in timer mode. Figure 1.13.18 shows TBiMR register in timer mode. Table 1.13.6 Specifications in Timer Mode Item Specification...

  • Page 132: Event Counter Mode

    Under development This document is under development and its contents are subject to change. M16C/6N5 Group Timer B 2. Event Counter Mode In event counter mode, the timer counts pulses from an external device or overflows and underflows of other timers. Table 1.13.7 lists specifications in event counter mode. Figure 1.13.19 shows TBiMR register in event counter mode.

  • Page 133: Pulse Period And Pulse Width Measurement Mode

    Under development This document is under development and its contents are subject to change. M16C/6N5 Group Timer B 3. Pulse Period and Pulse Width Measurement Mode In pulse period and pulse width measurement mode, the timer measures pulse period or pulse width of an external signal.
  • Page 134 Under development This document is under development and its contents are subject to change. M16C/6N5 Group Timer B Timer Bi mode register (i = 0 to 5) Symbol Address After reset TB0MR to TB2MR 039B to 039D 00XX0000 TB3MR to TB5MR 01DB to 01DD 00XX0000...
  • Page 135 Under development This document is under development and its contents are subject to change. M16C/6N5 Group Timer B Count source "H" Measurement pulse "L" Transfer Transfer (indeterminate value) (measured value) Reload register counter transfer timing (Note 1) (Note 1) (Note 2) Timing at which counter reaches "0000 "...

  • Page 136: Three-Phase Motor Control Timer Function

    Under development This document is under development and its contents are subject to change. M16C/6N5 Group Three-phase Motor Control Timer Function Three-phase Motor Control Timer Function Timers A1, A2, A4 and B2 can be used to output three-phase motor drive waveforms. Table 1.14.1 lists the specifications of the three-phase motor control timer function.
  • Page 137 Under development This document is under development and its contents are subject to change. M16C/6N5 Group Three-phase Motor Control Timer Function Figure 1.14.1 Three-phase Motor Control Timer Function Block Diagram Rev.1.00 2003.05.30 page 123...
  • Page 138 Under development This document is under development and its contents are subject to change. M16C/6N5 Group Three-phase Motor Control Timer Function Three-phase PWM control register 0 (Note 1) b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address After reset INVC0 01C8 Bit symbol...
  • Page 139 Under development This document is under development and its contents are subject to change. M16C/6N5 Group Three-phase Motor Control Timer Function Three-phase PWM control register 1 (Note 1) b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address After reset INVC1 01C9 Bit symbol...
  • Page 140 Under development This document is under development and its contents are subject to change. M16C/6N5 Group Three-phase Motor Control Timer Function Three-phase output buffer register i (i = 0, 1) (Note) b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address After reset IDB0...
  • Page 141 Under development This document is under development and its contents are subject to change. M16C/6N5 Group Three-phase Motor Control Timer Function Timer Ai, Ai-1 register (i = 1, 2, 4) (Notes 1 to 6) Symbol Address After reset 0389 -0388 Indeterminate 038B -038A...
  • Page 142 Under development This document is under development and its contents are subject to change. M16C/6N5 Group Three-phase Motor Control Timer Function Timer B2 interrupt occurrences frequency set counter Symbol Address After reset ICTB2 01CD Indeterminate Function Setting range If the INV01 bit is "0" (ICTB2 counter counted every 1 to 15 time timer B2 underflows), assuming the set value = n, a timer B2 interrupt is generated at every n’th...
  • Page 143 Under development This document is under development and its contents are subject to change. M16C/6N5 Group Three-phase Motor Control Timer Function Trigger select register b7 b6 b5 b4 b3 b2 b1 Symbol Address After reset TRGSR 0383 Bit symbol Bit name Function To use the V-phase output control TA1TGL...
  • Page 144 Under development This document is under development and its contents are subject to change. M16C/6N5 Group Three-phase Motor Control Timer Function Timer Ai mode register (i = 1, 2, 4) Symbol Address After reset b7 b6 b5 b4 b3 b2 b1 b0 TA1MR 0397 TA2MR...
  • Page 145 Under development This document is under development and its contents are subject to change. M16C/6N5 Group Three-phase Motor Control Timer Function The three-phase motor control timer function is enabled by setting the INV02 bit of INVC0 register to “1”. When this function is selected, timer B2 is used to control the carrier wave, and timers A4, A1 and A2 are used to control three-phase PWM outputs (U, U, V, V, W and W).
  • Page 146 Under development This document is under development and its contents are subject to change. M16C/6N5 Group Three-phase Motor Control Timer Function Carrier wave: sawtooth waveform Carrier wave Signal wave Timer B2 Start trigger signal for timer A4* Timer A4 one-shot pulse* Rewriting IDB0, IDB1 registers Transfer to three-phase output shift register...

  • Page 147: Serial I/O

    Under development This document is under development and its contents are subject to change. M16C/6N5 Group Serial I/O Serial I/O Serial I/O is configured with four channels: UART0 to UART2 and SI/O3. UARTi (i = 0 to 2) Each UARTi has an exclusive timer to generate a transfer clock, so they operate independently of each other.
  • Page 148 Under development This document is under development and its contents are subject to change. M16C/6N5 Group Serial I/O PCLK1=0 2SIO 1SIO or 2SIO 1SIO Main clock, PLL clock, or ring oscillator clock PCLK1=1 8SIO (UART0) 32SIO RxD polarity polarity reversing circuit reversing circuit Clock source selection...
  • Page 149 Under development This document is under development and its contents are subject to change. M16C/6N5 Group Serial I/O No reverse IOPOL=0 RxD data RxDi reverse circuit Reverse IOPOL=1 Clock synchronous type UART (7 bits) disabled UART Clock UARTi receive register UART(7 bits) (8 bits) synchronous...
  • Page 150 Under development This document is under development and its contents are subject to change. M16C/6N5 Group Serial I/O UARTi transmit buffer register (i = 0 to 2)(Note) Symbol Address After reset (b15) (b8) U0TB 03A3 -03A2 Indeterminate U1TB 03AB -03AA Indeterminate U2TB 01FB...
  • Page 151 Under development This document is under development and its contents are subject to change. M16C/6N5 Group Serial I/O UARTi transmit/receive mode register (i = 0 to 2) Symbol Address After reset U0MR to U2MR 03A0 , 03A8 , 01F8 Function Bit name symbol b2 b1 b0...
  • Page 152 Under development This document is under development and its contents are subject to change. M16C/6N5 Group Serial I/O UARTj transmit/receive control register 1 (j = 0, 1) Symbol Address After reset U0C1, U1C1 03A5 ,03AD 00000010 Function Bit name symbol 0 : Transmission disabled Transmit enable bit 1 : Transmission enabled...
  • Page 153 Under development This document is under development and its contents are subject to change. M16C/6N5 Group Serial I/O UART transmit/receive control register 2 Symbol Address After reset UCON 03B0 X0000000 Function Bit name symbol 0 : Transmit buffer empty (Tl = 1) UART0 transmit U0IRS 1 : Transmission completed (TXEPT = 1)
  • Page 154 Under development This document is under development and its contents are subject to change. M16C/6N5 Group Serial I/O UARTi special mode register 2 (i = 0 to 2) b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address After reset U0SMR2 to U2SMR2 01EE , 01F2 , 01F6...
  • Page 155 Under development This document is under development and its contents are subject to change. M16C/6N5 Group Serial I/O UARTi special mode register 4 (i = 0 to 2) b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address After reset U0SMR4 to U2SMR4 01EC , 01F0...

  • Page 156: Clock Synchronous Serial I/O Mode

    Under development This document is under development and its contents are subject to change. M16C/6N5 Group Serial I/O (Clock Synchronous Serial I/O Mode) Clock Synchronous Serial I/O Mode The clock synchronous serial I/O mode uses a transfer clock to transmit and receive data. Table 1.15.1 lists the specifications of the clock synchronous serial I/O mode.
  • Page 157 Under development This document is under development and its contents are subject to change. M16C/6N5 Group Serial I/O (Clock Synchronous Serial I/O Mode) Table 1.15.2 Registers to Be Used and Settings in Clock Synchronous Serial I/O Mode Register Function UiTB (Note 1) 0 to 7 Set transmission data UiRB (Note 1) 0 to 7 Reception data can be read...
  • Page 158 Under development This document is under development and its contents are subject to change. M16C/6N5 Group Serial I/O (Clock Synchronous Serial I/O Mode) Table 1.15.3 lists the functions of the input/output pins during clock synchronous serial I/O mode. Table 1.15.3 shows pin functions for the case where the multiple transfer clock output pin select function is deselected.
  • Page 159 Under development This document is under development and its contents are subject to change. M16C/6N5 Group Serial I/O (Clock Synchronous Serial I/O Mode) (1) Example of transmit timing (when internal clock is selected) Transfer clock "1" UiC1 register "0" Write data to the UiTB register TE bit "1"...
  • Page 160 Under development This document is under development and its contents are subject to change. M16C/6N5 Group Serial I/O (Clock Synchronous Serial I/O Mode) (a) CLK Polarity Select Function Use the UiC0 register (i = 0 to 2)’s CKPOL bit to select the transfer clock polarity. Figure 1.15.10 shows the polarity of the transfer clock.
  • Page 161 Under development This document is under development and its contents are subject to change. M16C/6N5 Group Serial I/O (Clock Synchronous Serial I/O Mode) (c) Continuous Receive Mode When the UiRRM bit (i = 0 to 2) = 1 (continuous receive mode), the UiC1 register’s TI bit is set to “0” (data present in UiTB register) by reading the UiRB register.
  • Page 162 Under development This document is under development and its contents are subject to change. M16C/6N5 Group Serial I/O (Clock Synchronous Serial I/O Mode) _______ _______ (f) CTS/RTS Separate Function (UART0) _______ _______ _______ _______ This function separates CTS /RTS , outputs RTS from the P6 pin, and accepts as input the CTS from the P6...

  • Page 163: Clock Asynchronous Serial I/O (Uart) Mode

    Under development This document is under development and its contents are subject to change. M16C/6N5 Group Serial I/O (UART Mode) Clock Asynchronous Serial I/O (UART) Mode The UART mode allows transmitting and receiving data after setting the desired transfer rate and transfer data format.
  • Page 164 Under development This document is under development and its contents are subject to change. M16C/6N5 Group Serial I/O (UART Mode) Table 1.15.6 Registers to Be Used and Settings in UART Mode Register Function UiTB 0 to 8 Set transmission data (Note 1) UiRB 0 to 8 Reception data can be read (Note 1)
  • Page 165 Under development This document is under development and its contents are subject to change. M16C/6N5 Group Serial I/O (UART Mode) Table 1.15.7 lists the functions of the input/output pins during UART mode. Table 1.15.8 lists the P6 functions during UART mode. Note that for a period from when the UARTi operation mode is selected to when transfer starts, the TxDi pin outputs an “H”.
  • Page 166 Under development This document is under development and its contents are subject to change. M16C/6N5 Group Serial I/O (UART Mode) (1) Example of transmit timing when transfer data is 8-bit long (parity enabled, one stop bit) The transfer clock stops momentarily as CTS is "H"...
  • Page 167 Under development This document is under development and its contents are subject to change. M16C/6N5 Group Serial I/O (UART Mode) • Example of receive timing when transfer data is 8-bit long (parity disabled, one stop bit) UiBRG count source "1" UiC1 register RE bit "0"...
  • Page 168 Under development This document is under development and its contents are subject to change. M16C/6N5 Group Serial I/O (UART Mode) (b) Serial Data Logic Switching Function The data written to the UiTB register has its logic reversed before being transmitted. Similarly, the received data has its logic reversed when read from the UiRB register.
  • Page 169 Under development This document is under development and its contents are subject to change. M16C/6N5 Group Serial I/O (UART Mode) _______ _______ (d) CTS/RTS Separate Function (UART0) ________ ________ ________ ________ This function separates CTS /RTS , outputs RTS from the P6 pin, and accepts as input the CTS from the P6 pin.

  • Page 170: Special Mode 2

    Under development This document is under development and its contents are subject to change. M16C/6N5 Group Serial I/O (Special Modes) Special Mode 1 (I C Mode) C mode is provided for use as a simplified I C interface compatible mode. Table 1.15.9 lists the specifications of the I C mode.
  • Page 171 Under development This document is under development and its contents are subject to change. M16C/6N5 Group Serial I/O (Special Modes) Start and stop condition generation block SDAi DMA0, DMA1 request STSPSEL=1 (UART1: DMA0 only) Delay STSP circuit STSP STSPSEL=0 IICM2=1 Transmission UARTi transmit, register...
  • Page 172 Under development This document is under development and its contents are subject to change. M16C/6N5 Group Serial I/O (Special Modes) Table 1.15.10 Registers to Be Used and Settings in I C Mode Function Register Master Slave UiTB (Note 1) 0 to 7 Set transmission data UiRB (Note 1) 0 to 7 Reception data can be read...
  • Page 173 Under development This document is under development and its contents are subject to change. M16C/6N5 Group Serial I/O (Special Modes) Table 1.15.11 I C Mode Functions C mode (SMD2 to SMD0 = 010 , IICM = 1) Clock IICM2 = 0 IICM2 = 1 synchronous (NACK/ACK interrupt)
  • Page 174 Under development This document is under development and its contents are subject to change. M16C/6N5 Group Serial I/O (Special Modes) (1) IICM2 = 0 (ACK and NACK interrupts), CKPH = 0 (no clock delay) 1st bit 2nd bit 3rd bit 4th bit 5th bit 6th bit...
  • Page 175 Under development This document is under development and its contents are subject to change. M16C/6N5 Group Serial I/O (Special Modes) • Detection of Start and Stop Condition Whether a start or a stop condition has been detected is determined. A start condition-detected interrupt request is generated when the SDAi pin changes state from high to low while the SCLi pin is in the high state.
  • Page 176 Under development This document is under development and its contents are subject to change. M16C/6N5 Group Serial I/O (Special Modes) Table 1.15.12 STSPSEL Bit Functions Function STSPSEL = 0 STSPSEL = 1 Output of SCLi and SDAi pins Output of transfer clock and Output of a start/stop condition data according to the STAREQ,...
  • Page 177 Under development This document is under development and its contents are subject to change. M16C/6N5 Group Serial I/O (Special Modes) • Transfer Clock Data is transmitted/received using a transfer clock like the one shown in Figure 1.15.24. The UiSMR2 register’s CSC bit is used to synchronize the internally generated clock (internal SCLi) and an external clock supplied to the SCLi pin.
  • Page 178 Under development This document is under development and its contents are subject to change. M16C/6N5 Group Serial I/O (Special Modes) • ACK and NACK If the STSPSEL bit in the UiSMR4 register is set to “0” (start and stop conditions not generated) and the ACKC bit in the UiSMR4 register is set to “1”...
  • Page 179 Under development This document is under development and its contents are subject to change. M16C/6N5 Group Serial I/O (Special Modes) Special Mode 2 Multiple slaves can be serially communicated from one master. Transfer clock polarity and phase are selectable. Table 1.15.13 lists the specifications of Special Mode 2. Figure 1.15.25 shows communication control example for Special Mode 2.
  • Page 180 Under development This document is under development and its contents are subject to change. M16C/6N5 Group Serial I/O (Special Modes) Microcomputer Microcomputer (Master) (Slave) Microcomputer (Slave) Figure 1.15.25 Serial Bus Communication Control Example (UART2) Rev.1.00 2003.05.30 page 166...
  • Page 181 Under development This document is under development and its contents are subject to change. M16C/6N5 Group Serial I/O (Special Modes) Table 1.15.14 Registers to Be Used and Settings in Special Mode 2 Register Function UiTB (Note 1) 0 to 7 Set transmission data UiRB (Note 1) 0 to 7 Reception data can be read...
  • Page 182 Under development This document is under development and its contents are subject to change. M16C/6N5 Group Serial I/O (Special Modes) • Clock Phase Setting Function One of four combinations of transfer clock phases and polarities can be selected using the UiSMR3 register’s CKPH bit and the UiC0 register’s CKPOL bit.
  • Page 183 Under development This document is under development and its contents are subject to change. M16C/6N5 Group Serial I/O (Special Modes) "H" Slave control input "L" "H" Clock input "L" (CKPOL=0, CKPH=0) Clock input "H" (CKPOL=1, CKPH=0) "L" "H" Data output timing "L"...

  • Page 184: Special Mode 3 (Ie Mode)

    Under development This document is under development and its contents are subject to change. M16C/6N5 Group Serial I/O (Special Modes) Special Mode 3 (IE Mode) In this mode, one bit of IEBus is approximated with one byte of UART mode waveform. Table 1.15.15 lists the registers used in IE mode and the register values set.
  • Page 185 Under development This document is under development and its contents are subject to change. M16C/6N5 Group Serial I/O (Special Modes) (1) UiSMR register ABSCS bit (bus collision detect sampling clock select) If ABSCS = 0, bus collision is determined at the rising edge of the transfer clock Transfer clock Input to TAj Timer Aj...

  • Page 186: Special Mode 4 (Sim Mode) (Uart2)

    Under development This document is under development and its contents are subject to change. M16C/6N5 Group Serial I/O (Special Modes) Special Mode 4 (SIM Mode) (UART2) Based on UART mode, this is an SIM interface compatible mode. Direct and inverse formats can be implemented, and this mode allows to output a low from the TxD pin when a parity error is detected.
  • Page 187 Under development This document is under development and its contents are subject to change. M16C/6N5 Group Serial I/O (Special Modes) Table 1.15.17 Registers to Be Used and Settings in SIM Mode Register Function U2TB (Note) 0 to 7 Set transmission data U2RB (Note) 0 to 7 Reception data can be read OER,FER,PER,SUM Error flag...
  • Page 188 Under development This document is under development and its contents are subject to change. M16C/6N5 Group Serial I/O (Special Modes) (1) Transmission Transfer clock "1" U2C1 register TE bit Write data to U2TB register "0" "1" U2C1 register TI bit "0"...
  • Page 189 Under development This document is under development and its contents are subject to change. M16C/6N5 Group Serial I/O (Special Modes) Figure 1.15.31 shows the example of connecting the SIM interface. Connect T and R and apply pull-up. Microcomputer SIM card Figure 1.15.31 SIM Interface Connection (a) Parity Error Signal Output The parity error signal is enabled by setting the U2C1 register’s U2ERE bit to “1”.
  • Page 190 Under development This document is under development and its contents are subject to change. M16C/6N5 Group Serial I/O (Special Modes) (b) Format • Direct Format Set the U2MR register's PRY bit to “1”, U2C0 register's UFORM bit to “0” and U2C1 register's U2LCH bit to “0”.

  • Page 191: Si/O3

    Under development This document is under development and its contents are subject to change. M16C/6N5 Group SI/O3 SI/O3 SI/O3 is exclusive clock-synchronous serial I/O. Figure 1.15.34 shows the block diagram of SI/O3, and Figure 1.15.35 shows the SI/O3-related registers. Table 1.15.18 lists the specifications of SI/O3. Clock source select PCLK1=0 SM31 to SM30...
  • Page 192 Under development This document is under development and its contents are subject to change. M16C/6N5 Group SI/O3 SI/O3 control register (Note 1) b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address After reset 01E2 0100000 Bit name Description symbol b1 b0 SM30 0 0 : Selecting f...
  • Page 193 Under development This document is under development and its contents are subject to change. M16C/6N5 Group SI/O3 Table 1.15.18 SI/O3 Specifications Item Specification Transfer data format • Transfer data length: 8 bits Transfer clock • S3C register’s SM36 bit = 1 (internal clock) : fj/ 2(n+1) fj = f .
  • Page 194 Under development This document is under development and its contents are subject to change. M16C/6N5 Group SI/O3 (a) SI/O3 Operation Timing Figure 1.15.36 shows the SI/O3 operation timing. 1.5 cycle (max.) (Note 1) "H" SI/O3 internal clock "L" "H" output "L"...
  • Page 195 Under development This document is under development and its contents are subject to change. M16C/6N5 Group SI/O3 (c) Functions for Setting an S Initial Value OUT3 If the S3C register’s SM36 bit = 0 (external clock), the S pin output can be fixed high or low when OUT3 not transferring.

  • Page 196: A-D Converter

    Under development This document is under development and its contents are subject to change. M16C/6N5 Group A-D Converter A-D Converter The microcomputer contains one A-D converter circuit based on 10-bit successive approximation method configured with a capacitive-coupling amplifier. The analog inputs share the pins with P10 to P10 , P9 _________...
  • Page 197 Under development This document is under development and its contents are subject to change. M16C/6N5 Group A-D Converter A-D conversion rate selection CKS1=1 CKS2=0 φ CKS0=1 CKS1=0 CKS0=0 CKS2=1 TRG=0 Software trigger A-D trigger TRG=1 Resistor ladder VCUT=0 VCUT=1 Successive conversion register ADCON1 register ADCON0 register AD register 0 (16)
  • Page 198 Under development This document is under development and its contents are subject to change. M16C/6N5 Group A-D Converter A-D control register 0 (Note) Symbol Address After reset ADCON0 03D6 00000XXX Bit symbol Bit name Function Function varies Analog input pin select bit with each operation mode b4 b3 0 0 : One-shot mode...
  • Page 199 Under development This document is under development and its contents are subject to change. M16C/6N5 Group A-D Converter A-D control register 2 (Note 1) Symbol Address After reset ADCON2 03D4 Bit symbol Bit name Function A-D conversion method 0 : Without sample and hold select bit 1 : With sample and hold b2 b1...

  • Page 200: One-Shot Mode

    Under development This document is under development and its contents are subject to change. M16C/6N5 Group A-D Converter (1) One-shot Mode In this mode, the input voltage on one selected pin is A-D converted once. Table 1.16.2 lists the specifications of one-shot mode.
  • Page 201 Under development This document is under development and its contents are subject to change. M16C/6N5 Group A-D Converter A-D control register 0 (Note 1) Symbol Address After reset ADCON0 03D6 00000XXX Bit symbol Bit name Function b2 b1 b0 0 0 0 : AN is selected 0 0 1 : AN is selected...

  • Page 202: Repeat Mode

    Under development This document is under development and its contents are subject to change. M16C/6N5 Group A-D Converter (2) Repeat Mode In this mode, the input voltage on one selected pin is A-D converted repeatedly. Table 1.16.3 lists the specifications of repeat mode. Figure 1.16.5 shows the ADCON0 and ADCON1 registers in repeat mode. Table 1.16.3 Repeat Mode Specifications Item Specification...
  • Page 203 Under development This document is under development and its contents are subject to change. M16C/6N5 Group A-D Converter A-D control register 0 (Note 1) Symbol Address After reset ADCON0 03D6 00000XXX Bit symbol Bit name Function b2 b1 b0 0 0 0 : AN is selected 0 0 1 : AN is selected...

  • Page 204: Single Sweep Mode

    Under development This document is under development and its contents are subject to change. M16C/6N5 Group A-D Converter (3) Single Sweep Mode In this mode, the input voltages on selected pins are A-D converted, one pin at a time. Table 1.16.4 lists the specifications of single sweep mode.
  • Page 205 Under development This document is under development and its contents are subject to change. M16C/6N5 Group A-D Converter A-D control register 0 (Note) Symbol Address After reset ADCON0 03D6 00000XXX Bit symbol Bit name Function Analog input pin select bit Invalid in single sweep mode A-D operation mode b4 b3...

  • Page 206: Repeat Sweep Mode 0

    Under development This document is under development and its contents are subject to change. M16C/6N5 Group A-D Converter (4) Repeat Sweep Mode 0 In this mode, the input voltages on selected pins are A-D converted repeatedly. Table 1.16.5 lists the specifications of repeat sweep mode 0.
  • Page 207 Under development This document is under development and its contents are subject to change. M16C/6N5 Group A-D Converter A-D control register 0 (Note) Symbol Address After reset ADCON0 03D6 00000XXX Bit symbol Bit name Function Analog input pin select bit Invalid in repeat sweep mode 0 b4 b3 A-D operation mode...

  • Page 208: Repeat Sweep Mode 1

    Under development This document is under development and its contents are subject to change. M16C/6N5 Group A-D Converter (5) Repeat Sweep Mode 1 In this mode, the input voltages on all pins are A-D converted repeatedly, with priority given to the selected pins.
  • Page 209 Under development This document is under development and its contents are subject to change. M16C/6N5 Group A-D Converter A-D control register 0 (Note) Symbol Address After reset ADCON0 03D6 00000XXX Bit symbol Bit name Function Analog input pin select bit Invalid in repeat sweep mode 1 b4 b3 A-D operation mode...
  • Page 210 Under development This document is under development and its contents are subject to change. M16C/6N5 Group A-D Converter (a) Resolution Select Function The desired resolution can be selected using the ADCON1 register’s BITS bit. If the BITS bit is set to “1” (10-bit conversion accuracy), the A-D conversion result is stored in the ADi register (i = 0 to 7)'s bit 0 to bit 9.
  • Page 211 Under development This document is under development and its contents are subject to change. M16C/6N5 Group A-D Converter (e) Current Consumption Reducing Function When not using the A-D converter, its resistor ladder and reference voltage input pin (V ) can be separated using the ADCON1 register’s VCUT bit.

  • Page 212: D-A Converter

    Under development This document is under development and its contents are subject to change. M16C/6N5 Group D-A Converter D-A Converter This is an 8-bit, R-2R type D-A converter. These are two independent D-A converters. D-A conversion is performed by writing to the DAi register (i = 0, 1). To output the result of conversion, set the DACON register’s DAiE bit to “1”...
  • Page 213 Under development This document is under development and its contents are subject to change. M16C/6N5 Group D-A Converter D-A control register (Note) Symbol Address After reset DACON 03DC Bit symbol Bit name Function 0 : Output disabled DA0E D-A0 output enable bit 1 : Output enabled 0 : Output disabled DA1E...

  • Page 214: Crc Calculation

    Under development This document is under development and its contents are subject to change. M16C/6N5 Group CRC Calculation CRC Calculation The Cyclic Redundancy Check (CRC) operation detects an error in data blocks. The microcomputer uses a generator polynomial of CRC-CCITT (X + 1) to generate CRC code.
  • Page 215 Under development This document is under development and its contents are subject to change. M16C/6N5 Group CRC Calculation Setup procedure and CRC operation when generating CRC code "80C4 " (a) CRC operation performed by the M16C CRC code: Remainder of a division in which the value written to the CRCIN register with its bit positions reversed is divided by the generator polynomial Generator polynomial: X + 1 (1 0001 0000 0010 0001...

  • Page 216: Can Module

    Under development This document is under development and its contents are subject to change. M16C/6N5 Group CAN Module CAN Module The CAN (Controller Area Network) module for the M16C/6N5 group of microcomputers is a communication controller implementing the CAN 2.0B protocol as defined in the BOSCH specification. The M16C/6N5 group contains one CAN module which can transmit and receive messages in both standard (11-bit) ID and extended (29-bit) ID formats.

  • Page 217: Can Module-Related Registers

    Under development This document is under development and its contents are subject to change. M16C/6N5 Group CAN Module CAN Module-Related Registers The CAN0 module has the following registers. (1) CAN Message Box A CAN module is equipped with 16 slots (16 bytes or 8 words each). Slots 14 and 15 can be used as Basic CAN. •...

  • Page 218: Can0 Message Box

    Under development This document is under development and its contents are subject to change. M16C/6N5 Group CAN Module CAN0 Message Box Table 1.19.1 shows the memory mapping of the CAN0 message box. It is possible to access to the message box in byte or word. Mapping of the message contents differs from byte access to word access.
  • Page 219 Under development This document is under development and its contents are subject to change. M16C/6N5 Group CAN Module Figures 1.19.2 and 1.19.3 show the bit mapping in each slot in byte access and word access. The content of each slot remains unchanged unless transmission or reception of a new message is performed. Bit 7 Bit 0 Data Byte 0...

  • Page 220: Acceptance Mask Registers

    Under development This document is under development and its contents are subject to change. M16C/6N5 Group CAN Module Acceptance Mask Registers Figures 1.19.4 and 1.19.5 show the C0GMR register, the C0LMAR register, and the C0LMBR register, in which bit mapping in byte access and word access are shown. Addresses CAN0 Bit 7...

  • Page 221: Can Sfr Registers

    Under development This document is under development and its contents are subject to change. M16C/6N5 Group CAN Module CAN SFR Registers C0MCTLj Register (j = 0 to 15) Figure 1.19.6 shows the C0MCTLj register. CAN0 message control register j (j = 0 to 15) (Note 4) Address After reset Symbol...
  • Page 222 Under development This document is under development and its contents are subject to change. M16C/6N5 Group CAN Module CiCTLR Register (i = 0, 1) Figures 1.19.7 and 1.19.8 show the CiCTLR register. CAN0 control register Symbol Address After reset 0210 C0CTLR X0000001 Bit symbol...
  • Page 223 Under development This document is under development and its contents are subject to change. M16C/6N5 Group CAN Module CAN1 control register Symbol Address After reset C1CTLR (Note) 0230 X0000001 Bit symbol Bit name Function Reserved bit Set to "0" (b4-b0) Reserved bit Set to "1"...
  • Page 224 Under development This document is under development and its contents are subject to change. M16C/6N5 Group CAN Module C0STR Register Figure 1.19.9 shows the C0STR register. CAN0 status register (Note) Symbol Address After reset C0STR 0212 Bit symbol Bit name Function MBOX Active slot bits...
  • Page 225 Under development This document is under development and its contents are subject to change. M16C/6N5 Group CAN Module C0SSTR Register Figure 1.19.10 shows the C0SSTR register. CAN0 slot status register (b15) (b8) b0 b7 Symbol Address After reset C0SSTR 0000 0215 , 0214 Function...
  • Page 226 Under development This document is under development and its contents are subject to change. M16C/6N5 Group CAN Module C0ICR Register Figure 1.19.11 shows the C0ICR register. CAN0 interrupt control register (Note) (b15) (b8) b0 b7 Symbol Address After reset C0ICR 0217 , 0216 0000...
  • Page 227 Under development This document is under development and its contents are subject to change. M16C/6N5 Group CAN Module C0CONR Register Figure 1.19.13 shows the C0CONR register. CAN0 configuration register Symbol Address After reset C0CONR Indeterminate 021A Bit symbol Bit name Function Prescaler division b3 b2 b1 b0...
  • Page 228 Under development This document is under development and its contents are subject to change. M16C/6N5 Group CAN Module C0RECR Register Figure 1.19.14 shows the C0RECR register. CAN0 receive error count register (Note 2) Address Symbol After reset C0RECR 021C Function Counter value Reception error counting function The value is incremented or decremented...
  • Page 229 Under development This document is under development and its contents are subject to change. M16C/6N5 Group CAN Module C0TSR Register Figure 1.19.16 shows the C0TSR register. CAN0 time stamp register (Note) (b15) (b8) b0 b7 Symbol Address After reset C0TSR 021F , 021E 0000...

  • Page 230: Operational Modes

    Under development This document is under development and its contents are subject to change. M16C/6N5 Group CAN Module Operational Modes The CAN module has the following three operational modes. • CAN Reset/Initialization Mode • CAN Sleep Mode • CAN Operation Mode Figure 1.19.18 shows transition between operational modes.
  • Page 231 Under development This document is under development and its contents are subject to change. M16C/6N5 Group CAN Module CAN Operation Mode The CAN operation mode is activated by clearing the Reset bit of the C0CTLR register. Entering the operation mode initiates the following functions by the module: •...

  • Page 232: Configuration Of The Can Module System Clock

    Under development This document is under development and its contents are subject to change. M16C/6N5 Group CAN Module Configuration of the CAN Module System Clock The M16C/6N5 group has a CAN module system clock select circuit. Configuration of the CAN module system clock can be done through manipulating the CCLKR register and the BRP bit of the C0CONR register.
  • Page 233 Under development This document is under development and its contents are subject to change. M16C/6N5 Group CAN Module Baud Rate Baud rate depends on X , the division value of the CAN module system clock, the division value of the prescaler for baud rate, and the number of Tq of one bit.

  • Page 234: Acceptance Filtering Function And Masking Function

    Under development This document is under development and its contents are subject to change. M16C/6N5 Group CAN Module Acceptance Filtering Function and Masking Function These functions serve the users to select and receive a facultative message. The C0GMR register, the C0LMAR register, and the C0LMBR register can perform masking to the standard ID and the extended ID of 29 bits.

  • Page 235: Acceptance Filter Support Unit (Asu)

    Under development This document is under development and its contents are subject to change. M16C/6N5 Group CAN Module Acceptance Filter Support Unit (ASU) The acceptance filter support unit has a function to judge valid/invalid of a received ID through table search. The IDs to receive are registered in the data table;...

  • Page 236: Basic Can Mode

    Under development This document is under development and its contents are subject to change. M16C/6N5 Group CAN Module Basic CAN Mode When the BasicCAN bit of the C0CTLR register is set to "1", slots 14 and 15 correspond to Basic CAN mode.

  • Page 237: Return From Bus Off Function

    Under development This document is under development and its contents are subject to change. M16C/6N5 Group CAN Module Return from Bus off Function When the protocol controller enters bus off state, it is possible to make it forced return from bus off state by the return from bus off function of the C0CTLR register.

  • Page 238: Reception And Transmission

    Under development This document is under development and its contents are subject to change. M16C/6N5 Group CAN Module Reception and Transmission Configuration of CAN Reception and Transmission Mode Table 1.19.3 shows configuration of CAN reception and transmission mode. Table 1.19.3 Configuration of CAN Reception and Transmission Mode TrmReq RecReq Remote...
  • Page 239 Under development This document is under development and its contents are subject to change. M16C/6N5 Group CAN Module Reception Figure 1.19.26 shows the behavior of the module when receiving two consecutive CAN messages, that fit into the slot of the shown C0MCTLj register (j = 0 to 15) and leads to losing/overwriting of the first message.
  • Page 240 Under development This document is under development and its contents are subject to change. M16C/6N5 Group CAN Module Transmission Figure 1.19.27 shows the timing of the transmit sequence. TrmReq bit TrmActive bit (3b) (3b) SentData bit CAN0 Successful (3b) Transmission Interrupt TrmState bit TrmSucc bit (3b)

  • Page 241: Can Interrupts

    Under development This document is under development and its contents are subject to change. M16C/6N5 Group CAN Module CAN Interrupts The CAN module provides the following CAN interrupts. • CAN0 Successful Reception Interrupt • CAN0 Successful Transmission Interrupt • CAN0 Error Interrupt Error Passive State Error BusOff State Bus Error (this feature can be disabled separately)

  • Page 242: Programmable I/O Ports

    Under development This document is under development and its contents are subject to change. M16C/6N5 Group Programmable I/O Ports Programmable I/O Ports The programmable input/output ports (hereafter referred to simply as “I/O ports”) consist of 87 lines P0 to P10 (except P8 ).
  • Page 243 Under development This document is under development and its contents are subject to change. M16C/6N5 Group Programmable I/O Ports Pull-up selection Direction register to P1 Port P1 control register Port latch Data bus (Note) Pull-up selection Direction register to P1 Port P1 control register Data bus Port latch...
  • Page 244 Under development This document is under development and its contents are subject to change. M16C/6N5 Group Programmable I/O Ports Pull-up selection Direction register , P6 , P7 "1" Output Data bus Port latch (Note) Switching between CMOS and Input to respective peripheral functions Pull-up selection Direction register to P8...
  • Page 245 Under development This document is under development and its contents are subject to change. M16C/6N5 Group Programmable I/O Ports Pull-up selection Direction register , P6 Port latch Data bus (Note 1) Switching between CMOS and Nch Input to respective peripheral functions Pull-up selection Direction register , P6...
  • Page 246 Under development This document is under development and its contents are subject to change. M16C/6N5 Group Programmable I/O Ports Pull-up selection Direction register to P10 (inside dotted-line not included) to P10 (inside dotted-line Data bus Port latch included) (Note) Analog input Input to respective peripheral functions Pull-up selection D-A output enabled...
  • Page 247 Under development This document is under development and its contents are subject to change. M16C/6N5 Group Programmable I/O Ports Pull-up selection Direction register Data bus Port latch (Note) Pull-up selection Direction register "1" Output Data bus Port latch (Note) Note: symbolizes a parasitic diode.
  • Page 248 Under development This document is under development and its contents are subject to change. M16C/6N5 Group Programmable I/O Ports Port Pi direction register (i = 0 to 7, 9, 10) (Notes 1, 2) Symbol Address After reset 03E2 , 03E3 , 03E6 , 03E7 PD0 to PD3...
  • Page 249 Under development This document is under development and its contents are subject to change. M16C/6N5 Group Programmable I/O Ports Port Pi register (i = 0 to 7, 9, 10) (Note 1) Symbol Address After reset 03E0 , 03E1 , 03E4 , 03E5 P0 to P3 Indeterminate...
  • Page 250 Under development This document is under development and its contents are subject to change. M16C/6N5 Group Programmable I/O Ports Pull-up control register 0 (Note 1) Symbol Address After reset 03FC PUR0 Bit symbol Bit name Function PU00 to P0 pull-up 0 : Not pulled high 1 : Pulled high (Note 2) PU01...
  • Page 251 Under development This document is under development and its contents are subject to change. M16C/6N5 Group Programmable I/O Ports Port control register Symbol Address After reset 03FF Bit symbol Bit name Function Operation performed when the P1 register is read 0 : When the port is set for input, the input levels of P1 to P1...
  • Page 252 Under development This document is under development and its contents are subject to change. M16C/6N5 Group Programmable I/O Ports Table 1.20.1 Unassigned Pin Handling in Single-chip Mode Pin name Connection Ports P0 to P7, P8 to P8 After setting for input mode, connect every pin to V via a resistor (pull-down);...
  • Page 253 Under development This document is under development and its contents are subject to change. M16C/6N5 Group Programmable I/O Ports Microcomputer Microcomputer (Input mode) (Input mode) P0 to P10 Port P6 to P10 Port (except for P8 (except for P8 (Input mode) (Input mode) Open Open...

  • Page 254: Electrical Characteristics

    Under development This document is under development and its contents are subject to change. M16C/6N5 Group Electrical Characteristics Electrical Characteristics Table 1.21.1 Absolute Maximum Ratings Symbol Parameter Condition Rated value Unit Supply voltage –0.3 to 6.5 Supply voltage –0.3<V Analog supply voltage –0.3 to 6.5 ____________ Input...
  • Page 255 Under development This document is under development and its contents are subject to change. M16C/6N5 Group Electrical Characteristics Table 1.21.2 Recommended Operating Conditions (Note 1) Standard Symbol Parameter Unit Min. Typ. Max. Supply voltage (V Analog supply voltage Supply voltage Analog supply voltage HIGH input 0.8V...
  • Page 256 Under development This document is under development and its contents are subject to change. M16C/6N5 Group Electrical Characteristics Table 1.21.3 Electrical Characteristics (Note 1) Standard Symbol Parameter Measuring condition Unit Min. Typ. Max. , P1 , P2 , P3 -2.0 HIGH output =–5mA voltage...
  • Page 257 Under development This document is under development and its contents are subject to change. M16C/6N5 Group Electrical Characteristics Table 1.21.4 A-D Conversion Characteristics (Note 1) Standard Symbol Parameter Measuring condition Unit Min. Typ. Max. – Resolution Bits Integral 10 bits ANEX0, ANEX1 input, ±3 non-linearity...
  • Page 258 Under development This document is under development and its contents are subject to change. M16C/6N5 Group Electrical Characteristics Timing Requirements (Referenced to V = 5 V, V = 0 V, at Topr = –40 to 85 °C unless otherwise specified) Table 1.21.7 External Clock Input (X Input) Standard...
  • Page 259 Under development This document is under development and its contents are subject to change. M16C/6N5 Group Electrical Characteristics Timing Requirements (Referenced to V = 5 V, V = 0 V, at Topr = –40 to 85 °C unless otherwise specified) Table 1.21.9 Timer A Input (Counter Input in Event Counter Mode) Standard Symbol...
  • Page 260 Under development This document is under development and its contents are subject to change. M16C/6N5 Group Electrical Characteristics Timing Requirements (Referenced to V = 5 V, V = 0 V, at Topr = –40 to 85 °C unless otherwise specified) Table 1.21.15 Timer B Input (Counter Input in Event Counter Mode) Standard Symbol...
  • Page 261 Under development This document is under development and its contents are subject to change. M16C/6N5 Group Electrical Characteristics Switching Characteristics (Referenced to V = 5 V, V = 0 V, at Topr = –40 to 85 °C unless otherwise specified) Table 1.21.21 Memory Expansion Mode and Microprocessor Mode (for setting with no wait) Standard Measuring...
  • Page 262 Under development This document is under development and its contents are subject to change. M16C/6N5 Group Electrical Characteristics Switching Characteristics (Referenced to V = 5 V, V = 0 V, at Topr = –40 to 85 °C unless otherwise specified) Table 1.21.22 Memory Expansion Mode and Microprocessor Mode (for 1- to 3-wait setting and external area access) Standard Measuring...
  • Page 263 Under development This document is under development and its contents are subject to change. M16C/6N5 Group Electrical Characteristics Switching Characteristics (Referenced to V = 5 V, V = 0 V, at Topr = –40 to 85 °C unless otherwise specified) Table 1.21.23 Memory Expansion Mode and Microprocessor Mode (for 2- to 3-wait setting, external area access and multiplexed bus selection) Standard...
  • Page 264 Under development This document is under development and its contents are subject to change. M16C/6N5 Group Electrical Characteristics c(TA) w(TAH) input w(TAL) c(UP) w(UPH) input w(UPL) input (Up/down input) During event counter mode input (When count on falling h(TIN—UP) su(UP—TIN) edge is selected) input (When count on rising...
  • Page 265 Under development This document is under development and its contents are subject to change. M16C/6N5 Group Electrical Characteristics Memory Expansion Mode and Microprocessor Mode (Effective for setting with wait) BCLK (Separate bus) WR, WRL, WRH (Separate bus) (Multiplexed bus) WR, WRL, WRH (Multiplexed bus) RDY input tsu(RDY—BCLK)

  • Page 266: Read Timing

    Under development This document is under development and its contents are subject to change. M16C/6N5 Group Electrical Characteristics Memory Expansion Mode and Microprocessor Mode (For setting with no wait) Read timing BCLK d(BCLK-CS) h(BCLK-CS) 25ns.max 4ns.min tcyc d(BCLK-AD) h(BCLK-AD) 25ns.max 4ns.min d(BCLK-ALE) h(BCLK-ALE)
  • Page 267 Under development This document is under development and its contents are subject to change. M16C/6N5 Group Electrical Characteristics Memory Expansion Mode and Microprocessor Mode For 1-wait setting and external area access Read timing BCLK d(BCLK-CS) h(BCLK-CS) 25ns.max 4ns.min tcyc d(BCLK-AD) h(BCLK-AD) 25ns.max 4ns.min...
  • Page 268 Under development This document is under development and its contents are subject to change. M16C/6N5 Group Electrical Characteristics Memory Expansion Mode and Microprocessor Mode For 2-wait setting and external area access Read timing tcyc BCLK h(BCLK-CS) d(BCLK-CS) 4ns.min 25ns.max h(BCLK-AD) d(BCLK-AD) 25ns.max 4ns.min...
  • Page 269 Under development This document is under development and its contents are subject to change. M16C/6N5 Group Electrical Characteristics Memory Expansion Mode and Microprocessor Mode For 3-wait setting and external area access Read timing tcyc BCLK h(BCLK-CS) d(BCLK-CS) 4ns.min 25ns.max h(BCLK-AD) d(BCLK-AD) 4ns.min 25ns.max...
  • Page 270 Under development This document is under development and its contents are subject to change. M16C/6N5 Group Electrical Characteristics Memory Expansion Mode and Microprocessor Mode For 1- or 2-wait setting, external area access and multiplexed bus selection Read timing BCLK h(BCLK-CS) d(BCLK-CS) h(RD-CS) 4ns.min...
  • Page 271 Under development This document is under development and its contents are subject to change. M16C/6N5 Group Electrical Characteristics Memory Expansion Mode and Microprocessor Mode For 3-wait setting, external area access and multiplexed bus selection Read timing tcyc BCLK h(RD-CS) h(BCLK-CS) (0.5 ✕...

  • Page 272: Flash Memory

    Under development This document is under development and its contents are subject to change. M16C/6N5 Group Flash Memory Flash Memory Flash Memory Performance The flash memory version is functionally the same as the mask ROM version except that it internally contains flash memory.

  • Page 273: Memory Map

    Under development This document is under development and its contents are subject to change. M16C/6N5 Group Flash Memory Memory Map The ROM in the flash memory version is separated between a user ROM area and a boot ROM area. Figure 1.22.1 shows the block diagram of flash memory. The user ROM area has a 4-Kbyte block A, in addition to the area that stores a program for microcomputer operation during singe-chip or memory expansion mode.

  • Page 274: Boot Mode

    Under development This document is under development and its contents are subject to change. M16C/6N5 Group Flash Memory Boot Mode After a hardware reset which is performed by applying a low-level signal to the P5 pin and a high-level signal to the CNV and P5 pins, the microcomputer is placed in boot mode, thereby executing the program in the boot ROM area.
  • Page 275 Under development This document is under development and its contents are subject to change. M16C/6N5 Group Flash Memory ROM code protect control address Symbol Address Value when shipped 1 1 1 ROMCP 0FFFFF (Note 1) Bit name Function Bit symbol Reserved bit Set to "1"...

  • Page 276: Cpu Rewrite Mode

    Under development This document is under development and its contents are subject to change. M16C/6N5 Group Flash Memory CPU Rewrite Mode In CPU rewrite mode, the user ROM area can be rewritten by executing software commands from the CPU. Therefore, the user ROM area can be rewritten directly while the microcomputer is mounted on-board without having to use a ROM programmer, etc.
  • Page 277 Under development This document is under development and its contents are subject to change. M16C/6N5 Group Flash Memory • EW0 Mode The microcomputer is placed in CPU rewrite mode by setting the FMR0 register’s FMR01 bit to “1” (CPU rewrite mode enabled), ready to accept commands. In this case, because the FMR1 register’s FMR11 bit = 0, EW0 mode is selected.
  • Page 278 Under development This document is under development and its contents are subject to change. M16C/6N5 Group Flash Memory Figure 1.22.4 shows the FMR0 register and FMR1 register. FMR00 Bit This bit indicates the operating status of the flash memory. The bit is “0” when the Program, Erase, or Lock Bit program is running;...
  • Page 279 Under development This document is under development and its contents are subject to change. M16C/6N5 Group Flash Memory Flash memory control register 0 Symbol Address After reset FMR0 01B7 XX000001 Bit symbol Bit name Function 0 : Busy (being written or erased) (Note 1) RY/BY status flag FMR00 1 : Ready...
  • Page 280 Under development This document is under development and its contents are subject to change. M16C/6N5 Group Flash Memory EW0 mode operation procedure Rewrite control program Single-chip mode, memory expansion For only boot mode mode, or boot mode set the FMR05 bit to "1" (user ROM area access) Set the FMR01 bit by writing "0"...
  • Page 281 Under development This document is under development and its contents are subject to change. M16C/6N5 Group Flash Memory Low power dissipation mode program Transfer a low power dissipation mode program Set the FMR01 bit by writing "0" and then "1" to any area other the flash memory (CPU rewrite mode enabled) Jump to the low power dissipation mode program...
  • Page 282 Under development This document is under development and its contents are subject to change. M16C/6N5 Group Flash Memory Precautions on CPU Rewrite Mode Described below are the precautions to be observed when rewriting the flash memory in CPU rewrite mode. (1) Operation Speed Before entering CPU rewrite mode (EW0 or EW1 mode), select 10 MHz or less for CPU clock using the CM06 bit in the CM0 register and the CM17 to CM16 bits in the CM1 register.
  • Page 283 Under development This document is under development and its contents are subject to change. M16C/6N5 Group Flash Memory (6) DMA Transfer In EW1 mode, make sure that no DMA transfers will occur while the FMR0 register’s FMR00 bit = 0 (during the auto program or auto erase period).

  • Page 284: Software Commands

    Under development This document is under development and its contents are subject to change. M16C/6N5 Group Flash Memory Software Commands Software commands are described below. The command code and data must be read and written in 16-bit unit, to and from even addresses in the user ROM area. When writing command code, the high-order 8 bits (D to D ) are ignored.
  • Page 285 Under development This document is under development and its contents are subject to change. M16C/6N5 Group Flash Memory Clear Status Register Command (50 This command clears the status register to “0”. Write “xx50 ” in the first bus cycle, and the FMR06 to FMR07 bits in the FMR0 register and SR4 to SR5 in the status register will be set to “0”.
  • Page 286 Under development This document is under development and its contents are subject to change. M16C/6N5 Group Flash Memory Block Erase Write “xx20 ” in the first bus cycle and write “xxD0 ” to the uppermost address of a block (even address, however) in the second bus cycle, and an auto erase operation (erase and verify) will start.
  • Page 287 Under development This document is under development and its contents are subject to change. M16C/6N5 Group Flash Memory Erase All Unlocked Block Write “xxA7 ” in the first bus cycle and write “xxD0 ” in the second bus cycle, and all blocks except block A will be erased successively, one block at a time.
  • Page 288 Under development This document is under development and its contents are subject to change. M16C/6N5 Group Flash Memory Read Lock Bit Status Command (71 This command reads the lock bit status of a specified block. Write “xx71 ” in the first bus cycle and write “xxD0 ”...

  • Page 289: Status Register

    Under development This document is under development and its contents are subject to change. M16C/6N5 Group Flash Memory Data Protect Function Each block in the flash memory has a nonvolatile lock bit. The lock bit is effective when the FMR02 bit = 0 (lock bit enabled).
  • Page 290 Under development This document is under development and its contents are subject to change. M16C/6N5 Group Flash Memory Table 1.22.5 Status Register Contents Status register FMR0 register Status name Value after reset “0” “1” SR7 (D FMR00 Sequencer status Busy Ready SR6 (D Reserved...
  • Page 291 Under development This document is under development and its contents are subject to change. M16C/6N5 Group Flash Memory Full Status Check When an error occurs, the FMR0 register’s FMR06 or FMR07 bits are set to “1”, indicating occurrence of each specific error. Therefore, execution results can be verified by checking these status bits (full status check).
  • Page 292 Under development This document is under development and its contents are subject to change. M16C/6N5 Group Flash Memory Full status check FMR06 = 1 (1) Execute the Clear Status Register command to set Command status flags to "0". sequence error FMR07 = 1? (2) Reexecute the command after checking that it is entered correctly.

  • Page 293: Standard Serial I/O Mode

    Under development This document is under development and its contents are subject to change. M16C/6N5 Group Flash Memory Standard Serial I/O Mode In standard serial I/O mode, the user ROM area can be rewritten while the microcomputer is mounted on- board by using a serial programmer suitable for the M16C/6N5 group.
  • Page 294 Under development This document is under development and its contents are subject to change. M16C/6N5 Group Flash Memory Table 1.22.7 Pin Functions for Standard Serial I/O Mode Name Description Power input Apply the voltage guaranteed for Program and Erase to V pin and 0 V to V pin.
  • Page 295 Under development This document is under development and its contents are subject to change. M16C/6N5 Group Flash Memory M16C/6N5 Group (Flash memory version) BUSY SCLK Connect Mode setup method oscillator circuit Signal Value CNVss RESET to V Package: 100P6S-A Figure 1.22.13 Pin Connections for Serial I/O Mode Rev.1.00 2003.05.30 page 281...
  • Page 296 Under development This document is under development and its contents are subject to change. M16C/6N5 Group Flash Memory Example of Circuit Application in Standard Serial I/O Mode Figures 1.22.14 and 1.22.15 show example of circuit application in standard serial I/O mode 1 and mode 2, respectively.

  • Page 297: Parallel I/O Mode

    Under development This document is under development and its contents are subject to change. M16C/6N5 Group Flash Memory Parallel I/O Mode In parallel I/O mode, the user ROM and boot ROM areas can be rewritten by using a parallel programmer suitable for the M16C/6N5 group.

  • Page 298: Can I/O Mode

    Under development This document is under development and its contents are subject to change. M16C/6N5 Group Flash Memory CAN I/O Mode In CAN I/O mode, the user ROM area can be rewritten while the microcomputer is mounted on-board by using a CAN programmer suitable for the M16C/6N5 group. For more information about CAN program- mers, contact the manufacturer of your CAN programmer.
  • Page 299 Under development This document is under development and its contents are subject to change. M16C/6N5 Group Flash Memory M16C/6N5 Group (Flash memory version) SCLK Connect Mode setup method oscillator circuit Signal Value CNVss RESET to V SCLK Package: 100P6S-A Figure 1.22.16 Pin Connections for CAN I/O Mode Rev.1.00 2003.05.30 page 285...
  • Page 300 Under development This document is under development and its contents are subject to change. M16C/6N5 Group Flash Memory Example of Circuit Application in CAN I/O Mode Figure 1.22.17 shows example of circuit application in CAN I/O mode. Refer to the user’s manual for CAN writer to handle pins controlled by a CAN writer.

  • Page 301: Electrical Characteristics

    Under development This document is under development and its contents are subject to change. M16C/6N5 Group Flash Memory Electrical Characteristics Table 1.22.9 lists the flash memory electrical characteristics. Table 1.22.10 lists the flash memory version program/erase voltage and read operation voltage characteristics. Table 1.22.9 Flash Memory Electrical Characteristics (Note 1) Standard Symbol...
  • Page 302 Under development This document is under development and its contents are subject to change. M16C/6N5 Group Package Dimension Package Dimension 100P6S-A Plastic 100pin 14✕20mm body QFP EIAJ Package Code JEDEC Code Weight(g) Lead Material QFP100-P-1420-0.65 – 1.58 Alloy 42 Recommended Mount Pad Dimension in Millimeters Symbol –...
  • Page 303 Under development This document is under development and its contents are subject to change. M16C/6N5 Group Register Index Register Index C0TRMIC ........72 C0TSR .......... 215 AD0 ..........185 KUPIC ..........72 C1CTLR ........209 AD1 ..........185 CAN0 SLOT 0 to 15 AD2 ..........
  • Page 304 Under development This document is under development and its contents are subject to change. M16C/6N5 Group Register Index TB4 ..........115 TB4IC ..........72 S0RIC ..........72 WDC ..........86 TB4MR ...... 115,117,118,120 S0TIC ..........72 WDTS ..........86 TB5 ..........115 S1RIC ..........
  • Page 305 REVISION HISTORY M16C/6N5 Group Hardware Manual Description Rev. Date Page Summary 1.00 May 30, 2003 – First edition issued...
  • Page 306 Blank page...
  • Page 307 M16C/6N5 Group Rev.1.00 Editioned by Committee of editing of RENESAS Semiconductor Hardware Manual This book, or parts thereof, may not be reproduced in any form without permission of Renesas Technology Corporation. Copyright © 2003. Renesas Technology Corporation, All rights reserved.
  • Page 308 M16C/6N5 Group Hardware Manual 2-6-2, Ote-machi, Chiyoda-ku, Tokyo, 100-0004, Japan...
  • Page 309 Usage Notes Reference Book RENESAS 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/60 SERIES For the most current Usage Notes Reference Book, please visit our website. Before using this material, please visit our website to confirm that this is the most current document available.
  • Page 310 • The prior written approval of Renesas Technology Corporation is necessary to reprint or reproduce in whole or in part these materials.
  • Page 311 Preface The “Usage Notes Reference Book” is a compilation of usage notes from the Hardware Manual as well as technical news related to this product.
  • Page 312 Blank page...
  • Page 313 Table of Contents 1. Usage Precaution 1.1 Precautions for External Bus ........................1 1.2 Precautions for PLL Frequency Synthesizer ....................2 1.3 Precautions for Power Control ........................3 1.4 Precautions for Protection ..........................4 1.5 Precautions for Interrupts ..........................5 1.5.1 Reading Address 00000 16 ........................................
  • Page 314 Blank page...

  • Page 315: Usage Precaution

    Under development This document is under development and its contents are subject to change. M16C/6N5 Group 1.1 Precautions for External Bus 1. Usage Precaution 1.1 Precautions for External Bus 1. The external ROM version can operate only in the microprocessor mode, connect the CNV pin to V 2.

  • Page 316: Precautions For Pll Frequency Synthesizer

    Under development This document is under development and its contents are subject to change. M16C/6N5 Group 1.2 Precautions for PLL Frequency Synthesizer 1.2 Precautions for PLL Frequency Synthesizer Make the supply voltage stable to use the PLL frequency synthesizer. For ripple with the supply voltage 5 V, keep below 10 kHz as frequency, below 0.5 V (peak to peak) as voltage fluctuation band and below 1 V/mS as voltage fluctuation rate.

  • Page 317: Precautions For Power Control

    Under development This document is under development and its contents are subject to change. M16C/6N5 Group 1.3 Precautions for Power Control 1.3 Precautions for Power Control ____________ When exiting stop mode by hardware reset, set RESET pin to “L” until a main clock oscillation is stabilized.

  • Page 318: Precautions For Protection

    Under development This document is under development and its contents are subject to change. M16C/6N5 Group 1.4 Precautions for Protection 1.4 Precautions for Protection Set the PRC2 bit to “1” (write enabled) and then write to any address, and the PRC2 bit will be set to “0” (write protected).

  • Page 319: Precautions For Interrupts

    Under development This document is under development and its contents are subject to change. M16C/6N5 Group 1.5 Precautions for Interrupts 1.5 Precautions for Interrupts 1.5.1 Reading Address 00000 Do not read the address 00000 in a program. When a maskable interrupt request is accepted, the CPU reads interrupt information (interrupt number and interrupt request priority level) from the address 00000 during the interrupt sequence.

  • Page 320: Changing The Interrupt Generate Factor

    Under development This document is under development and its contents are subject to change. M16C/6N5 Group 1.5 Precautions for Interrupts 1.5.4 Changing the Interrupt Generate Factor If the interrupt generate factor is changed, the IR bit in the interrupt control register for the changed interrupt may inadvertently be set to “1”...

  • Page 321: Rewrite The Interrupt Control Register

    Under development This document is under development and its contents are subject to change. M16C/6N5 Group 1.5 Precautions for Interrupts 1.5.6 Rewrite the Interrupt Control Register (1) The interrupt control register for any interrupt should be modified in places where no requests for that interrupt may occur.

  • Page 322: Precautions For Dmac

    Under development This document is under development and its contents are subject to change. M16C/6N5 Group 1.6 Precautions for DMAC 1.6 Precautions for DMAC 1.6.1 Write to DMAE Bit in DMiCON Register (i = 0, 1) When both of the conditions below are met, follow the steps below. Conditions •...

  • Page 323: Precautions For Timers

    Under development This document is under development and its contents are subject to change. M16C/6N5 Group 1.7 Precautions for Timers 1.7 Precautions for Timers 1.7.1 Timer A 1.7.1.1 Timer A (Timer Mode) 1. The timer remains idle after reset. Set the mode, count source, counter value, etc. using the TAiMR (i = 0 to 4) register and the TAi register before setting the TAiS bit in the TABSR register to “1”...
  • Page 324 Under development This document is under development and its contents are subject to change. M16C/6N5 Group 1.7 Precautions for Timers 1.7.1.3 Timer A (One-shot Timer Mode) 1. The timer remains idle after reset. Set the mode, count source, counter value, etc. using the TAiMR (i = 0 to 4) register, the TAi register, the ONSF register TA0TGL and TA0TGH bits and the TRGSR register before setting the TAiS bit in the TABSR register to “1”...
  • Page 325 Under development This document is under development and its contents are subject to change. M16C/6N5 Group 1.7 Precautions for Timers 1.7.1.4 Timer A (Pulse Width Modulation Mode) 1. The timer remains idle after reset. Set the mode, count source, counter value, etc. using the TAiMR (i = 0 to 4) register, the TAi register, the ONSF register TA0TGL and TA0TGH bits and the TRGSR register before setting the TAiS bit in the TABSR register to “1”...

  • Page 326: Timer B

    Under development This document is under development and its contents are subject to change. M16C/6N5 Group 1.7 Precautions for Timers 1.7.2 Timer B 1.7.2.1 Timer B (Timer Mode) 1. The timer remains idle after reset. Set the mode, count source, counter value, etc. using the TBiMR (i = 0 to 5) register and TBi register before setting the TBiS bit in the TABSR or the TBSR register to “1”...
  • Page 327 Under development This document is under development and its contents are subject to change. M16C/6N5 Group 1.7 Precautions for Timers 1.7.2.3 Timer B (Pulse Period/pulse Width Measurement Mode) 1. The timer remains idle after reset. Set the mode, count source, etc. using the TBiMR (i = 0 to 5) register before setting the TBiS bit in the TABSR or the TBSR register to “1”...

  • Page 328: Precautions For Serial I/O (Clock Synchronous Serial I/O Mode)

    Under development This document is under development and its contents are subject to change. M16C/6N5 Group 1.8 Precautions for Serial I/O (Clock Synchronous Serial I/O Mode) 1.8 Precautions for Serial I/O (Clock Synchronous Serial I/O Mode) 1.8.1 Transmission/reception _______ With an external clock selected, and choosing the RTS function, the output level of the RTS goes to “L”...

  • Page 329: Precaution For Serial I/O (Special Modes)

    Under development This document is under development and its contents are subject to change. M16C/6N5 Group 1.9 Precautions for Serial I/O (Special Modes) 1.9 Precaution for Serial I/O (Special Modes) 1.9.1 Special Mode 2 _______ If a low-level signal is applied to the NMI pin when the TB2SC register IVPCR1 bit = 1 (three-phase _______ output forcible cutoff by input on NMI pin enabled), the RTS and CLK...

  • Page 330: Precautions For A-D Converter

    Under development This document is under development and its contents are subject to change. M16C/6N5 Group 1.10 Precautions for A-D Converter 1.10 Precautions for A-D Converter 1. Set the ADCON0 (except bit 6), ADCON1 and ADCON2 registers when A-D conversion is stopped (before a trigger occurs).
  • Page 331 Under development This document is under development and its contents are subject to change. M16C/6N5 Group 1.10 Precautions for A-D Converter 8. If the CPU reads the ADi register at the same time the conversion result is stored in the ADi register after completion of A-D conversion, an incorrect value may be stored in the ADi register.

  • Page 332: Precautions For Can Module

    Under development This document is under development and its contents are subject to change. M16C/6N5 Group 1.11 Precautions for CAN Module 1.11 Precautions for CAN Module 1.11.1 Reading C0STR Register The CAN module on the M16C/6N5 Group updates the status of the C0STR register in a certain period.
  • Page 333 Under development This document is under development and its contents are subject to change. M16C/6N5 Group 1.11 Precautions for CAN Module CPU read signal Updating period of CAN module CPU reset signal C0STR register ✕ ✕ ✕ ✕ ✕ b8: State_Reset bit 0: CAN operation mode ✕: When the CAN module’s State_Reset bit updating period matches the CPU’s read...

  • Page 334: Can Transceiver In Boot Mode

    Under development This document is under development and its contents are subject to change. M16C/6N5 Group 1.11 Precautions for CAN Module 1.11.2 CAN Transceiver in Boot Mode When programming the flash memory in boot mode via CAN bus, the operation mode of CAN transceiver should be set to “high-speed mode”...

  • Page 335: Precautions For Programmable I/O Ports

    Under development This document is under development and its contents are subject to change. M16C/6N5 Group 1.12 Precautions for Programmable I/O Ports 1.12 Precautions for Programmable I/O Ports _______ If a low-level signal is applied to the NMI pin when the TB2SC register IVPCR1 bit = “1” (three-phase _______ output forcible cutoff by input on NMI pin enabled), the P7 to P7...

  • Page 336: Precauitons For Electrical Characteristic Differences Between Mask Rom And Flash Memory Version Microcomputers

    Under development This document is under development and its contents are subject to change. M16C/6N5 Group 1.13 Precautions for Electrical Characteristic Differences Between Mask ROM and Flash Memory Version Microcomputers 1.13 Precautions for Electrical Characteristic Differences Between Mask ROM and Flash Memory Version Microcomputers Flash memory version and mask ROM version may have different characteristics, operating margin, noise tolerated dose, noise width dose in electrical characteristics due to internal ROM, different layout pattern, etc.

  • Page 337: Precautions For Flash Memory Version

    Under development This document is under development and its contents are subject to change. M16C/6N5 Group 1.14 Precautions for Flash Memory Version 1.14 Precautions for Flash Memory Version 1.14.1 Precautions for Functions to Prevent Flash Memory from Rewriting ID codes are stored in addresses 0FFFDF , 0FFFE3 , 0FFFEB , 0FFFEF...

  • Page 338: Operation Speed

    Under development This document is under development and its contents are subject to change. M16C/6N5 Group 1.14 Precautions for Flash Memory Version 1.14.8 Operation speed Before entering CPU rewrite mode (EW0 or EW1 mode), select 10 MHz or less for BCLK using the CM06 bit of the CM0 register and the CM17 to CM16 bits of the CM1 register.
  • Page 339 REVISION HISTORY M16C/6N5 Group Usage Notes Description Rev. Date Page Summary 1.00 May 30, 2003 – First edition issued...
  • Page 340 Blank page...
  • Page 341 RENESAS 16-BIT SINGLE-CHIP MICROCOMPUTER USAGE NOTES REFERENCE BOOK M16C/6N5 Group Rev.1.00 Editioned by Committee of editing of RENESAS Semiconductor Usage Notes Reference Book This book, or parts thereof, may not be reproduced in any form without permission of Renesas Technology Corporation.
  • Page 342 M16C/6N5 Group Usage Notes Reference Book 2-6-2, Ote-machi, Chiyoda-ku, Tokyo, 100-0004, Japan...

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