Operations; Basic Operations; Clk Polarity Selection - Renesas M16C/64A Series User Manual

M16C/64A Group
24.3

Operations

24.3.1

Basic Operations

SI/Oi transmits and receives data simultaneously. The SiTRR register is not divided into a register for
transmission/reception and buffer. Write transmit data to the SiTRR register while transmission/
reception is stopped. Read receive data from the SiTRR register while transmission/reception is
stopped.
24.3.2

CLK Polarity Selection

Use the SMi4 bit in the SiC register to select the transmit/receive clock polarity. Figure 24.2 shows
Polarity of Transmit/Receive Clock.
(1) When the SMi4 bit in the SiC register = 0
CLKi
SOUTi
SINi
(2) When the SMi4 bit = 1
CLKi
SOUTi
SINi
i = 3, 4
Notes:
The above diagram assumes the following:
1. The SMi5 bit in the SiC register is 0 (LSB first).
2. The SMi6 bit in the SiC register is 1 (internal clock).
3. The SM26 bit or SM27 bit in the S34C2 register is 1 (SOUTi output retains last bit level)
Figure 24.2 Polarity of Transmit/Receive Clock
R01UH0136EJ0210 Rev.2.10
Jul 31, 2012
D0 D1 D2 D3
D1 D2 D3
D0
D0 D1 D2 D3
D0 D1 D2 D3
24. Serial Interface SI/O3 and SI/O4
D4 D5 D6 D7
D4 D5 D6 D7
D4 D5 D6 D7
D4 D5 D6 D7
High level is output when not
transmitting/receiving data
Low level is output when not
transmitting/receiving data
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