Cold/Warm Start Discrimination - Renesas M16C/64A Series User Manual

M16C/64A Group
6.4.10

Cold/Warm Start Discrimination

The cold/warm start discrimination detects whether or not voltage applied to the VCC1 pin drops to the
RAM hold voltage or below. The reference voltage is Vdet0. Therefore, the voltage monitor 0 reset is
used for cold/warm start discrimination. Follow 7.4.2.1 "Voltage Monitor 0 Reset" to set the bits related
to the voltage monitor 0 reset.
The CWR bit in the RSTFR register is 0 (cold start) when power is turned on. The CWR bit also
becomes 0 after power-on reset or voltage monitor 0 reset. The CWR bit becomes 1 (warm start) by
writing 1, and remains unchanged at hardware reset, voltage monitor 1 reset, voltage monitor 2 reset,
oscillator stop detect reset, watchdog timer reset, or software reset.
In the cold/warm start discrimination, the Vdet0 level can be selected by setting the VDSEL1 bit in the
OFS1 address.
•
When power-on reset or voltage monitor 0 reset is used
Set the VDSEL1 bit to 0 (Vdet0_2).
•
When neither power-on reset nor voltage monitor 0 reset is used as the user system
The VDSEL1 bit can be set to 0 or 1.
When the VDSEL1 bit is 1 (Vdet0_0), voltage monitor 0 reset and its cancellation are based on
Vdet0_0. Therefore, execute hardware reset after cancelling the voltage monitor 0 reset.
Figure 6.6 shows the Cold/Warm Start Discrimination Example.
VCC1
Vdet0
CWR bit
Internal reset signal
Figure 6.6 Cold/Warm Start Discrimination Example
R01UH0136EJ0210 Rev.2.10
Jul 31, 2012
5 V
0 V
Set to 1 by a program
6. Resets
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