Renesas M16C/64A Series User Manual page 111

M16C/64A Group
When the VW1C1 bit
is 0 (digital filter
enabled)
When the VW1C1 bit
is 1 (digital filter
disabled) and the
VW1C7 bit is 0 (when
VCC1 reaches Vdet1
or above)
When the VW1C1 bit is
1 (digital filter disabled)
and the VW1C7 bit is 1
(when VCC1 reaches
Vdet1 or below)
VW1C1, VW1C2, VW1C3, VW1C6, VW1C7: Bits in the VW1C register
The above diagram assumes the following:
• The VC26 bit in the VCR2 register is 1 (voltage detector 1 enabled)
• The VW1C0 bit in the VW1C register is 1 (voltage monitor 1 interrupt/reset enabled)
Note:
1. When not using the voltage monitor 0 reset, operate at recommended operation condition VCC1.
Figure 7.6 Voltage Monitor 1 Interrupt/Reset Operation Example
R01UH0136EJ0210 Rev.2.10
Jul 31, 2012
VCC1
Vdet1
VW1C3 bit
Digital filter sampling clock × 3 cycles
VW1C2 bit
Voltage monitor 1
interrupt request
(when VW1C6 is 0)
Internal reset signal
(when VW1C6 is 1)
VW1C2 bit
Voltage monitor 1
interrupt request
(when VW1C6 is 0)
VW1C2 bit
Voltage monitor 1
interrupt request
(when VW1C6 is 0)
Internal reset signal
(when VW1C6 is 1)
Digital filter sampling clock × 3 cycles
Becomes 0 by accepting
an interrupt request
Set to 0
Becomes 0 by accepting an
interrupt request
tps + × 60 cycles (maximum)
8
fOCO-S
7. Voltage Detector
Set to 0
Set to 0
Becomes 0 by accepting an
interrupt request
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