15. Watchdog Timer; Introduction - Renesas M16C/64A Series User Manual

M16C/64A Group

15. Watchdog Timer

15.1

Introduction

The watchdog timer contains a 15-bit counter, and the count source protection mode (enabled/disabled)
can be set.
Table 15.1 lists Watchdog Timer Specifications.
Refer to 6.4.8 "Watchdog Timer Reset" for details of watchdog timer reset.
Figure 15.1 shows Watchdog Timer Block Diagram.
Table 15.1 Watchdog Timer Specifications
Item
Count source
Count operation
Count start conditions
Count stop condition
Watchdog timer
counter refresh
timing
Operation when the
timer underflows
Selectable functions
Write to the WDTR register
Internal reset signal
WDTR register written
WDTON bit in the OFS1 address
Prescaler
CPU clock
Bus hold
fOCO-S
WDC7,WDC4 to WDC0: Bits in the WDC register
CSPRO: Bit in the CSPR register
CM07: Bit in the CM0 register
PM12: Bit in the PM register
Figure 15.1 Watchdog Timer Block Diagram
R01UH0136EJ0210 Rev.2.10
Jul 31, 2012
Count Source Protection Mode Disabled Count Source Protection Mode Enabled
CPU clock
Decrement
Either of the following can be selected
(selected by the WDTON bit in the OFS1 address)
•
Count automatically starts after reset.
•
Count starts by writing to the WDTS register.
Stop mode, wait mode, bus hold
•
Reset (refer to 6. "Resets")
•
Write 00h, and then FFh to the WDTR register.
•
Underflow
Watchdog timer interrupt or watchdog
timer reset
•
Prescaler divide ratio
Divide-by-16 or divide-by-128 (selected by the WDC7 bit in the WDC register)
However, divide-by-2 is selected when the CM07 bit in the CM0 register is 1
(sub clock).
•
Count source protection mode
Enabled or disabled (selected by the CSPROINI bit in the OFS1 address and
the CSPRO bit in the CSPR register)
(low active)
WDC7
CM07
0
1/16
0
1
1
1/128
CSPRO
1/2
0
1
fOCO-S
None
Watchdog timer reset
Refresh
Watchdog timer counter
b14 b10 b3 b0
WDC4 to WDC0
Underflow
15. Watchdog Timer
PM12
Watchdog timer
0
interrupt
Watchdog timer reset
1
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