Renesas M16C/64A Series User Manual page 640

M16C/64A Group
CEC
CRXDEN bit
CABTEN bit
CRFLG bit
CRSTFLG bit
0
CRERRFLG bit
IR bit
CCRB1 register
CCRBE bit
CCRBAI bit
CRXDEN bit: Bit in the CECC3 register
CABTEN bit: Bit in the CECC4 register
Bits CRFLG, CRERRFLG, and CRSTFLG: Bits in the CECFLG register
IR bit: Bit in the CEC2IC register
Bits CCRBE and CCRBAI: Bits in the CCRB2 register
The above diagram applies under the following conditions.
The CFIL bit in the CECC2 register is 0 (filter disabled)
The CRISEL2 bit in the CISEL register is 1 (receive error interrupt enabled)
The CRISELS bit in the CISEL register is 0 (reception start bit interrupt disabled)
Figure 26.11 Reception Example (Change from Error Low Pulse Output Disabled to Enabled When
an Error Occurs)
R01UH0136EJ0210 Rev.2.10
Jul 31, 2012
Header block
ST H7 H3 H2
Receive error occurs
26. Consumer Electronics Control (CEC) Function
Error
low pulse
Set to 0 by a program
Change in synchronization
with the count source
Set to 0 by acceptance of an
interrupt or by a program
Undefined
Undefined
Undefined
Become 0 in
synchronization with
the count source
Become 0 in
synchronization with
the count source
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