Real-Time Clock Second Compare Data Register (Rtccsec) - Renesas M16C/64A Series User Manual

M16C/64A Group
20.2.8

Real-Time Clock Second Compare Data Register (RTCCSEC)

Real-Time Clock Second Compare Data Register
b7 b6 b5 b4 b3 b2 b1
The RTCCSEC register is enabled when bits RTCCMP1 to RTCCMP0 in the RTCCR2 register are 01b,
10b, or 11b (any compare mode).
SCMP03 to SCMP00 (First digit of second compare data bit) (b3-b0)
SCMP12 to SCMP10 (Second digit of second compare data bit) (b6-b4)
Set a value between 00 and 59 by the BCD code.
Write to these bits when the BSY bit in the RTCSEC register is 0 (not while data is updated).
R01UH0136EJ0210 Rev.2.10
Jul 31, 2012
Symbol
b0
RTCCSEC
Bit Symbol
SCMP00
SCMP01
First digit of second compare data bit
SCMP02
SCMP03
SCMP10
SCMP11 Second digit of second compare data bit Store compare data
SCMP12
—
No register bit. If necessary, set to 0. The read value is undefined value.
(b7)
Address
0348h
Bit Name
Store compare data
20. Real-Time Clock
Reset Value
X000 0000b
Setting
Function RW
Range
RW
RW
0 to 9
RW
RW
RW
0 to 5 RW
RW
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