Renesas M16C/64A Series User Manual page 842

REVISION HISTORY
Rev. Date
Page
2.00 Feb 07, 2011 129
Processor Mode
131
136
Bus
Chap. 11. 11.3.5.7 HOLD Signal: Deleted.
137
140
152
Memory Space Expansion Function
155, 156,
158, 159
Programmable I/O Ports
165
180
Interrupts
194, 195
219
219
221
Watchdog Timer
224
225
228
DMAC
243
250
Timer A
252
253
269, 282,
286, 291
273
277
M16C/64A Group Hardware Manual
9.6.5 Slow Read Mode: Added.
10.2.1 Processor Mode Register 0 (PM0):
Added the technical update number to the explanation of bits PM01 to PM00.
Figure 10.1 Memory Map in Single-Chip Mode: Added the 384 KB row to Address YYYYYh.
Table 11.1 Bus Specifications: Deleted "HOLD, HDLA available" in the External Bus row.
11.3.1.2 Bus Hold:
• Deleted the second condition to enter hold state "Inputting a low-level signal to the HOLD pin....".
• Added the fourth bullet to the explanations when the bus is in hold state.
11.4.4 HOLD: Added.
Figure 12.1 Memory Mapping and CS Areas in 1-MB Mode (PM13 = 0),
Figure 12.2 Memory Mapping and CS Areas in 1-MB Mode (PM13 = 1),
Figure 12.3 Memory Mapping and CS Areas in 4-MB Mode (PM13 = 0),
Figure 12.4 Memory Mapping and CS Areas in 4-MB Mode (PM13 = 1):
Added the 384 KB rows to note 1.
13.2 I/O Ports and Pins: Changed the style and layout.
13.3.3 Pull-Up Control Register 2 (PUR2):
Changed the PU21 bit from "P8_4 to P8_7 pull-up" to "P8_4, P8_6, P8_7 pull-up".
14.2.2 Interrupt Control Register 1 and 14.2.3 Interrupt Control Register 2:
• Moved the description for symbols and addresses to tables below the register diagram.
• Changed the IR bit explanations.
14.13.2 SP Setting: Deleted the descriptions regarding the NMI interrupt.
14.13.3 NMI Interrupt: Added the second bullet.
14.13.5 Rewriting the Interrupt Control Register and 14.13.6 Instruction to Rewrite the Interrupt
Control Register:
Rewritten from 14.13.5 Rewriting the Interrupt Control Register in the previous version.
15.2.1 Voltage Monitor 2 Control Register (VW2C): Changed the explanation below the diagram.
15.2.2 Count Source Protection Mode Register (CSPR): Changed the content of b6 to b0.
15.3.1 Optional Function Select Address 1 (OFS1): Deleted the explanation below the diagram.
16.3.3 Transfer Cycles: Changed "one cycle" to "one bus cycle" in line 5.
16.5.1 Write to the DMAE Bit in the DMiCON Register (i = 0 to 3): Added the technical update number.
Figure 17.2 Timer A Configuration:
Deleted "programmable output mode" from 11b of timer A0 and timer A3.
Figure 17.3 Timer A Block Diagram: Moved POFSi to right of MR0.
Table 17.7 Registers and Settings in Timer Mode,
Table 17.13 Registers and Settings in One-Shot Timer Mode,
Table 17.15 Registers and Settings in PWM Mode, and
Table 17.17 Registers and Settings in Programmable Output Mode:
Changed the Bit column of the TAi1 and TAi from "7 to 0".
Table 17.9 Registers and Settings in Event Counter Mode (When Not Using Two-Phase Pulse
Signal Processing):
• Changed the Setting column in the PCLKR and TACS0 to TACS2 rows.
• Changed the Bit column of the TAi1 and TAi from "7 to 0".
Table 17.11 Registers and Settings in Event Counter Mode (When Processing Two-Phase Pulse
Signal):
• Changed the Setting column in the PCLKR, TACS0 to TACS2, and ONSF rows.
• Changed the Bit column of the TAi1 and TAi from "7 to 0".
Description
Summary
C - 9