Renesas M16C/64A Series User Manual page 522

M16C/64A Group
Table 23.17 Registers Used and Settings in I
Register Bits
IICM2
CSC
SWC
ALS
UiSMR2
STAC
SWC2
SDHI
7
0, 2, 4
NODC
UiSMR3
CKPH
DL2 to DL0 Set the amount of SDAi digital delay.
STAREQ
RSTAREQ
STPREQ
STSPSEL
ACKD
UiSMR4
ACKC
SCLHI
SWC9
U0IRS
U1IRS
U0RRM
U1RRM
UCON
CLKMD0
CLKMD1
RCSP
7
i = 0 to 2, 5 to 7
Note:
1. This table does not describe a procedure.
R01UH0136EJ0210 Rev.2.10
Jul 31, 2012
2
Master
2
See Table 23.18 "I C Mode Functions".
Set to 1 to enable clock synchronization.
Set to 1 to fix SCLi output to low after
receiving the eighth bit of the clock.
Set to 1 to stop SDAi output when
arbitration lost is detected.
Set to 0.
Set to 1 to forcibly pull SCLi output low.
Set to 1 to disable SDAi output.
Set to 0.
Set to 0.
Set to 1.
Set to 1 to generate start condition.
Set to 1 to generate restart condition.
Set to 1 to generate stop condition.
Set to 1 to output each condition.
Select ACK or NACK.
Set to 1 to output ACK data.
Set to 1 to stop SCLi output when stop
condition is detected.
Set to 0.
Set to 1.
Set to 1.
Set to 0.
Set to 0.
Set to 0.
Set to 0.
Set to 0.
Set to 0.
23. Serial Interface UARTi (i = 0 to 2, 5 to 7)
(1)
C Mode (2/2)
Function
See Table 23.18 "I
Set to 0.
Set to 1 to fix SCLi output to low after
receiving the eighth bit of the clock.
Set to 0.
Set to 1 to initialize UARTi at start condition
detection.
Set to 1 to forcibly pull SCLi output low.
Set to 1 to disable SDAi output.
Set to 0.
Set to 0.
Set to 1.
Set the amount of SDAi digital delay.
Set to 0.
Set to 0.
Set to 0.
Set to 0.
Select ACK or NACK.
Set to 1 to output ACK data.
Set to 0.
Set to 1 to set SCLi to remain low at the
falling edge of the ninth bit of clock.
Set to 1.
Set to 1.
Set to 0.
Set to 0.
Set to 0.
Set to 0.
Set to 0.
Set to 0.
Slave
2
C Mode Functions".
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