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Renesas M16C/29 Series User Manual

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Page 1 On April 1 , 2010, NEC Electronics Corporation merged with Renesas Technology Corporation, and Renesas Electronics Corporation took over all the business of both companies. Therefore, although the old company name remains in this document, it is a valid Renesas Electronics document. We appreciate your understanding.
Page 2 Renesas Electronics. Renesas Electronics shall not be in any way liable for any damages or losses incurred by you or third parties arising from the use of any Renesas Electronics product for an application categorized as “Specific”...
Page 3 All information contained in these materials, including products and product specifications, represents information on the product at the time of publication and is subject to change by Renesas Electronics Corp. without notice. Please review the latest information published by Renesas Electronics Corp. through various means, including the Renesas Electronics Corp.
Page 4 Please be sure to implement safety measures to guard against the possibility of physical injury, and injury or damage caused by fire in the event of the failure of a Renesas product, such as safety design for hardware and software including but not limited to redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other applicable measures.
Page 5 General Precautions in the Handling of MPU/MCU Products The following usage notes are applicable to all MPU/MCU products from Renesas. For detailed usage notes on the products covered by this manual, refer to the relevant sections of the manual. If the descriptions under General Precautions in the Handling of MPU/MCU Products and in the body of the manual differ from each other, the description in the body of the manual takes precedence.
Page 6 The following documents apply to the M16C/29 Group. Make sure to refer to the latest versions of these documents. The newest versions of the documents listed may be obtained from the Renesas Technology Web site. Document Type...
Page 7 Notation of Numbers and Symbols The notation conventions for register names, bit names, numbers, and symbols used in this manual are described below. Register Names, Bit Names, and Pin Names Registers, bits, and pins are referred to in the text by symbols. The symbol is accompanied by the word “register,”...
Page 8 Register Notation The symbols and terms used in register diagrams are described below. XXX Register Symbol Address After Reset Bit Symbol Bit Name Function b1 b0 XXX bits XXX0 1 0: XXX 0 1: XXX 1 0: Do not set. XXX1 1 1: XXX Nothing is assigned.
Page 9 List of Abbreviations and Acronyms Abbreviation Full Form ACIA Asynchronous Communication Interface Adapter bits per second Cyclic Redundancy Check Direct Memory Access DMAC Direct Memory Access Controller Global System for Mobile Communications Hi-Z High Impedance IEBus Inter Equipment bus Input/Output IrDA Infrared Data Association Least Significant Bit...
Page 10 Table of Contents Quick Reference to Pages Classified by Address _____________________ B-1 1. Overview ____________________________________________________ 1 1.1 Features ........................... 1 1.1.1 Applications ........................ 1 1.1.2 Specifications ......................2 1.2 Block Diagram ........................4 1.3 Product List ........................6 1.4 Pin Assignments ......................12 1.5 Pin Description .......................
Page 11: Table Of Contents
5. Resets _____________________________________________________ 35 5.1 Hardware Reset ......................35 5.1.1 Hardware Reset 1 ....................35 5.1.2 Brown-Out Detection Reset (Hardware Reset 2) ............. 35 5.2 Software Reset ....................... 36 5.3 Watchdog Timer Reset ....................36 5.4 Oscillation Stop Detection Reset ..................36 5.5 Voltage Detection Circuit ....................
Page 12 9. Interrupts ___________________________________________________ 70 9.1 Type of Interrupts ......................70 9.1.1 Software Interrupts ....................71 9.1.2 Hardware Interrupts ....................72 9.2 Interrupts and Interrupt Vector ..................73 9.2.1 Fixed Vector Tables ....................73 9.2.2 Relocatable Vector Tables ..................74 9.3 Interrupt Control ......................75 9.3.1 I Flag ........................
Page 13 12. Timers ___________________________________________________ 101 12.1 Timer A ........................103 12.1.1 Timer Mode ......................106 12.1.2 Event Counter Mode .................... 107 12.1.3 One-shot Timer Mode ..................112 12.1.4 Pulse Width Modulation (PWM) Mode ..............114 12.2 Timer B ........................117 12.2.1 Timer Mode ......................119 12.2.2 Event Counter Mode ....................
Page 14 14.2 SI/O3 and SI/O4 ......................217 14.2.2 CLK Polarity Selection ..................220 14.2.1 SI/Oi Operation Timing ..................220 14.2.3 Functions for Setting an SOUTi Initial Value ............221 15. A/D Converter _____________________________________________ 222 15.1 Operating Modes ......................228 15.1.1 One-Shot Mode ....................228 15.1.2 Repeat mode ......................
Page 15 16.5.3 Bit 2: Slave Address Comparison Flag (AAS) ............. 269 16.5.4 Bit 3: Arbitration Lost Detection Flag (AL) ............269 16.5.5 Bit 4: I C bus Interface Interrupt Request Bit (PIN) ..........270 16.5.6 Bit 5: Bus Busy Flag (BB) ..................270 16.5.7 Bit 6: Communication Mode Select Bit (Transfer Direction Select Bit: TRX) ..
Page 16 17.2 Operating Modes ......................300 17.2.1 CAN Reset/Initialization Mode ................300 17.2.2 CAN Operating Mode ................... 301 17.2.3 CAN Sleep Mode ....................301 17.2.4 CAN Interface Sleep Mode .................. 302 17.2.5 Bus Off State ......................302 17.3 Configuration of the CAN Module System Clock ............303 17.3.1 Bit Timing Configuration ..................
Page 17 20.4 CPU Rewrite Mode ..................... 337 20.4.1 EW Mode 0 ......................338 20.4.2 EW Mode 1 ......................338 20.5 Register Description ....................339 20.5.1 Flash Memory Control Register 0 (FMR0) ............339 20.5.2 Flash Memory Control Register 1 (FMR1) ............340 20.5.3 Flash Memory Control Register 4 (FMR4) ............
Page 18 21. Electrical Characteristics _____________________________________ 366 21.1 Normal version ......................366 21.2 T version ........................387 21.3 V Version ........................408 22. Usage Notes ______________________________________________ 421 22.1 SFRs ........................... 421 22.1.1 For 80-Pin Package ..................... 421 22.1.2 For 64-Pin Package ..................... 421 22.1.3 Register Setting ....................
Page 19 22.9 A/D Converter ......................439 22.10 Multi-Master I C bus Interface ................. 441 22.10.1 Writing to the S00 Register ................441 22.10.2 AL Flag ....................... 441 22.11 CAN Module ......................442 22.11.1 Reading C0STR Register ................... 442 22.11.2 CAN Transceiver in Boot Mode ................444 22.12 Programmable I/O Ports ...................
Page 20 Appendix 1. Package Dimensions ________________________________ 453 Appendix 2. Functional Comparison _______________________________ 454 Appendix 2.1 Difference between M16C/28 Group and M16C/29 Group (Normal-ver.) ..454 Appendix 2.2 Difference between M16C/28 and M16C/29 Group (T-ver./V-ver.) ....455 Register Index ________________________________________________ 456 A-11...
Page 21 Quick Reference to Pages Classified by Address Register Symbol Page Register Symbol Page Address Address 0000 0040 CAN0 wakeup interrupt control register C01WKIC 0001 0041 C0RECIC 0002 0042 CAN0 successful reception interrupt control register C0TRMIC 0003 0043 CAN0 successful transmission interrupt control regiser Processor mode register 0 INT3 interrupt control register INT3IC...
Page 22 Quick Reference to Pages Classified by Address Register Symbol Page Register Symbol Page Address Address 00C0 0080 00C1 0081 0082 00C2 CAN0 message box 2: Identifier/DLC CAN0 message box 6: Identifier/DLC 0083 00C3 00C4 0084 0085 00C5 0086 00C6 00C7 0087 00C8 0088...
Page 23 Quick Reference to Pages Classified by Address Register Symbol Page Register Symbol Page Address Address 0100 0140 0101 0141 0102 0142 CAN0 message box 10: Identifer/DLC CAN0 message box 14: Identifier/DLC 0103 0143 0104 0144 0105 0145 0146 0106 0147 0107 0148 0108...
Page 24 Quick Reference to Pages Classified by Address Register Symbol Page Register Symbol Page Address Address 0180 0240 0181 0241 0242 0182 CAN0 acceptance filter support register C0AFS 0183 0243 0184 0244 0245 0185 0186 0246 0247 0248 0249 01B0 024A 024C 01B1 01B2...
Page 25 Quick Reference to Pages Classified by Address Register Symbol Page Register Symbol Page Address Address 0300 0340 TM, WG register 0 146,147 G1TM0, G1PO0 0301 0341 0302 0342 TM, WG register 1 Timer A1-1 register TA11 146,147 G1TM1, G1PO1 0343 0303 0344 0304...
Page 26 Quick Reference to Pages Classified by Address Register Symbol Page Register Symbol Page Address Address 104, 118, 03C0 0380 Count start flag TABSR A/D register 0 03C1 Clock prescaler reset flag CPSRF 105,118 03C2 0381 A/D register 1 One-shot start flag ONSF 0382 03C3...
Page 27 M16C/29 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 1. Overview 1.1 Features The M16C/29 Group of single-chip control MCU incorporates the M16C/60 series CPU core, employing the high-performance silicon gate CMOS technology and sophisticated instructions for a high level of effi- ciency. The M16C/29 Group is housed in 64-pin and 80-pin plastic molded LQFP packages. These single- chip MCUs operate using sophisticated instructions featuring a high level of instruction efficiency.
Page 28 1. Overview 1.1.2 Specifications Table 1.1 lists performance overview of M16C/29 Group 80-pin package. Table 1.2 lists performance overview of M16C/29 Group 64-pin package. Table 1.1 Performance Overview of M16C/29 Group (T-ver./V-ver.) (80-Pin Package) Item Performance Number of basic instructions 91 instructions Shortest instruction 50 ns (f(BCLK) = 20MH...
Page 29 1. Overview Table 1.2 Performance Overview of M16C/29 Group (64-Pin Package) Item Performance Number of basic instructions 91 instructions Shortest instruction 50 ns (f(BCLK) = 20MH = 3.0 to 5.5 V) (Normal-ver./T-ver.) excution time 100 ns(f(BCLK) = 10MH = 2.7 to 5.5 V) (Normal-ver.) 50 ns (f(BCLK) = 20MH = 4.2 to 5.5 V, -40 to 105°C)
Page 30 1. Overview 1.2 Block Diagram Figure 1.1 is a block diagram of the M16C/29 Group, 80-pin package. I / O P o r t s Port P0 Port P1 Port P2 Port P3 I n t e r n a l P e r i p h e r a l F u n c t i o n s T i m e r ( 1 6 b i t s ) U A R T / c l o c k s y n c h r o n o u s S I / O System clock generator...
Page 31 1. Overview Figure 1.2 is a block diagram of the M16C/29 Group, 64-pin package. I / O P o r t s Port P0 Port P1 Port P2 P o r t P 3 I n t e r n a l P e r i p h e r a l F u n c t i o n s U A R T / C l o c k s y n c h r o n o u s S I / O T i m e r ( 1 6 b i t s ) System clock generator...
Page 32 1. Overview 1.3 Product List Tables 1.3 to 1.5 list the M16C/29 Group products and Figure 1.3 shows the type numbers, memory sizes and packages. Tables 1.6 to 1.8 list the product code of flash memory version for M16C/29 Group. Figure 1.4 to Figure 1.6 show the marking diagram of flash memory version for M16C/29 Group.
Page 33 1. Overview Table 1.5 Product List (3) -V Version As of March, 2007 y t i y t i page 7...
Page 34 1. Overview Type No. M 3 0 2 9 0 F A T H P - U3 Product Code See Tables 1.6 and 1.9 for Normal-ver., Tables 1.7 and 1.10 for T-ver., and Tables 1.8 and 1.11 for V-ver.. Package type: HP = Package PLQP0080KB-A (80P6Q-A) Package PLQP0064KB-A (64P6Q-A) Version...
Page 35 1. Overview Table 1.6 Product Codes of Flash Memory Version -M16C/29 Group, Normal-ver. C º C º C º C º C º C º C º C º Table 1.7 Product Codes of Flash Memory Version -M16C/29 Group, T-ver. C º...
Page 36 1. Overview (1) Flash Memory Version, PLQP0080KB-A (80P6Q-A), Normal-ver. M16C Product Name: indicates M30290FAHP M30290FAHP Chip Version and Product Code: A U3 A: indicates chip version XXXXXXX The first edition is shown to be blank and continues with A and B. U3: indicates product code (see Table 1.6) Date Code (7 digits): indicates manufacturing management code (2) Flash Memory Version, PLQP0064KB-A (64P6Q-A), Normal-ver.
Page 37 1. Overview (1) Flash Memory Version, PLQP0080KB-A (80P6Q-A), V-ver. M16C Product Name: indicates M30290FAVHP M30290FAVHP Chip Version and Product Code: A U3 A: indicates chip version XXXXXXX The first edition is shown to be blank and continues with A and B. U3: indicates product code (see Table 1.8) Date Code (7 digits): indicates manufacturing management code (2) Flash Memory Version, PLQP0064KB-A (64P6Q-A), V-ver.
Page 38 1. Overview 1.4 Pin Assignments Figures 1.7 and 1.8 show the pin assignments (top view). /AN0 /CLK /AN0 /AN0 /SIN /AN0 /SOUT /AN0 M16C/29 Group (M16C/29) /AN0 /AN0 PLQP0080KB-A /CTS /RTS /CTS /CLKS /CLK (80P6Q-A) /RxD (top view) /TXD /SDA /TA0 /CTS1/RTS1/CTS /CLKS...
Page 39 1. Overview Table 1.12 Pin Characteristics for 80-Pin Package - i t page 13...
Page 40 1. Overview Table 1.12 Pin Characteristics for 80-Pin Package (continued) - i t page 14...
Page 41 1. Overview /AN0 /CLK /AN0 /AN0 OUT3 M16C/29 Group (M16C/29) /CTS /RTS /CTS0/CLKS1 /CLK /RxD PLQP0064KB-A /TxD /TxD /SDA /TA0 /RTS1/CTS1/CTS0/CLKS1 (64P6Q-A) /RxD /SCL /TA0 /CLK1 (top view) /CLK /TA1 /V/RxD1 /CTS /RTS /TA1 /V/TxD1 /TA2 /TA2 /AN2 /CTX /TA3 /AN3 /TB2 /CRX...
Page 42 1. Overview Table 1.13 Pin Characteristics for 64-Pin Package - t l page 16...
Page 43 1. Overview Table 1.13 Pin Characteristics for 64-Pin Package (continued) - i t page 17...
Page 44 1. Overview 1.5 Pin Description Table 1.14 Pin Description (64-pin and 80-pin packages) Classification Symbol I/O Type Function Power supply Apply 0V to the Vss pin. Apply following voltage to the Vcc pin. 2.7 to 5.5 V (Normal), 3.0 to 5.5 V (T-ver.), 4.2 to 5.5 V (V-ver.) Analog power Supplies power to the A/D converter.
Page 45 1. Overview Table 1.14 Pin Description (64-pin and 80-pin packages) (Continued) Classification Symbol I/O Type Function Timer S INPC1 to INPC1 Input pins for the time measurement function OUTC1 to OUTC1 Output pins for the waveform generating function Input pin for the CAN communication function Output pin for the CAN communication function I/O Ports to P0...
Page 46 1. Overview Table 1.14 Pin Description (80-pin packages only) (Continued) Classification Symbol I/O Type Function Serial I/O CLK4 Inputs and outputs the transfer clock Inputs serial data Outputs serial data OUT4 A/D Converter to AN0 Analog input pins for the A/D converter to AN2 to AN2 I/O Ports...
Page 47 2. Central Processing Unit (CPU) 2. Central Processing Unit (CPU) Figure 2.1 shows the CPU registers. The CPU has 13 registers. Of these, R0, R1, R2, R3, A0, A1 and FB comprise a register bank. There are two register banks. b8 b7 R0H(R0's high bits) R0L(R0's low bits)
Page 48 2. Central Processing Unit (CPU) 2.3 Frame Base Register (FB) FB is configured with 16 bits, and is used for FB relative addressing. 2.4 Interrupt Table Register (INTB) INTB is configured with 20 bits, indicating the start address of an interrupt vector table. 2.5 Program Counter (PC) PC is configured with 20 bits, indicating the address of an instruction to be executed.
Page 49 3. Memory 3. Memory Figure 3.1 is a memory map of the M16C/29 Group. M16C/29 Group provides 1-Mbyte address space from addresses 00000 to FFFFF . The internal ROM is allocated lower addresses beginning with address FFFFF . For example, 64-Kbytes internal ROM is allocated addresses F0000 to FFFFF Two 2-Kbyte internal ROM areas, block A and block B, are available in the flash memory version.
Page 50 4. Special Function Registers (SFRs) 4. Special Function Registers (SFRs) SFRs (Special Function Registers) are the control registers of peripheral functions. Table 4.1 to 4.11 list the SFR address map. Table 4.1 SFR Information (1) Register Symbol After reset Address 0000 0001 0002...
Page 51 4. Special Function Registers (SFRs) Table 4.2 SFR Information (2) Register Symbol After reset Address 0040 CAN0 wakeup interrupt control register C01WKIC XXXXX000 0041 CAN0 successful reception interrupt control register C0RECIC XXXXX000 0042 CAN0 successful transmission interrupt control register C0TRMIC XXXXX000 0043 INT3 interrupt control register...
Page 52 4. Special Function Registers (SFRs) Table 4.3 SFR Information (3) Register Symbol After reset Address CAN0 message box 2: Identifier/DLC 0080 0081 0082 0083 0084 0085 CAN0 message box 2 : Data field 0086 0087 0088 0089 008A 008B 008C 008D CAN0 message box 2 : Time stamp 008E...
Page 53 4. Special Function Registers (SFRs) Table 4.4 SFR Information (4) Register Symbol After reset Address CAN0 message box 6: Identifier/DLC 00C0 00C1 00C2 00C3 00C4 00C5 CAN0 message box 6 : Data field 00C6 00C7 00C8 00C9 00CA 00CB 00CC 00CD CAN0 message box 6 : Time stamp 00CE...
Page 54 4. Special Function Registers (SFRs) Table 4.5 SFR Information (5) Register Symbol After reset Address CAN0 message box 10: Identifier/DLC 0100 0101 0102 0103 0104 0105 CAN0 message box 10 : Data field 0106 0107 0108 0109 010A 010B 010C 010D CAN0 message box 10 : Time stamp 010E...
Page 55 4. Special Function Registers (SFRs) Table 4.6 SFR Information (6) Register Symbol After reset Address CAN0 message box 14: Identifier/DLC 0140 0141 0142 0143 0144 0145 CAN0 message box 14 : Data field 0146 0147 0148 0149 014A 014B 014C 014D CAN0 message box 14 : Time stamp 014E...
Page 56 4. Special Function Registers (SFRs) Table 4.7 SFR Information (7) Register Symbol After reset Address CAN0 message control register 0 C0MCTL0 0200 CAN0 message control register 1 C0MCTL1 0201 CAN0 message control register 2 C0MCTL2 0202 CAN0 message control register 3 C0MCTL3 0203 CAN0 message control register 4...
Page 57 4. Special Function Registers (SFRs) Table 4.8 SFR Information (8) Register Symbol After reset Address Time measurement, Pulse generation register 0 G1TM0,G1PO0 0300 0301 Time measurement, Pulse generation register 1 G1TM1,G1PO1 0302 0303 Time measurement, Pulse generation register 2 G1TM2,G1PO2 0304 0305 Time measurement, Pulse generation register 3...
Page 58 4. Special Function Registers (SFRs) Table 4.9 SFR Information (9) Register Symbol After reset Address 0340 0341 Timer A1-1 register TA11 0342 0343 Timer A2-1 register TA21 0344 0345 Timer A4-1 register TA41 0346 0347 Three phase PWM control register 0 INVC0 0348 Three phase PWM control register 1...
Page 59 4. Special Function Registers (SFRs) Table 4.10 SFR Information (10) Register Symbol After reset Address Count start flag TABSR 0380 Clock prescaler reset flag CPSRF 0XXXXXXX 0381 One-shot start flag ONSF 0382 Trigger select register TRGSR 0383 Up-dowm flag 0384 0385 Timer A0 register 0386...
Page 60 4. Special Function Registers (SFRs) Table 4.11 SFR Information (11) Register Symbol After reset Address A/D register 0 03C0 03C1 A/D register 1 03C2 03C3 A/D register 2 03C4 03C5 A/D register 3 03C6 03C7 A/D register 4 03C8 03C9 A/D register 5 03CA 03CB...
Page 61: Resets
5. Resets 5. Resets Hardware reset 1, brown-out detection reset (hardware reset 2), software reset, watchdog timer reset, and oscillation stop detection reset are implemented to reset the MCU. 5.1 Hardware Reset Hardware reset 1 and brown-out detection reset are available as the hardware reset. 5.1.1 Hardware Reset 1 ____________ Pins, CPU, and SFRs are reset by using the RESET pin.
Page 62: Software Reset
5. Resets Recommended operating voltage RESET RESET Equal to or less Equal to or less than 0.2V than 0.2V More than td(ROC) + td(P-R) Figure 5.1 Example Reset Circuit 5.2 Software Reset The MCU resets its pins, CPU, and SFRs when the PM03 bit in the PM0 register is set to 1 (reset) and the MCU executes a program in an address indicated by the reset vector.
Page 63 5. Resets More than td(P-R) td(ROC) RESET Max. 2 ms CPU clock: 28 cycles CPU clock FFFFC Content of reset vector Address FFFFE Figure 5.2 Reset Sequence ____________ Table 5.1 Pin Status When RESET Pin Level is “L” Status Pin name P0 to P3, Input port (high impedance) P6 to P10...
Page 64: Voltage Detection Circuit
5. Resets 5.5 Voltage Detection Circuit Note = 5 V is assumed in 5.5 Voltage Detection Circuit. Voltage detection circuit in the M16C/29 Group, T-ver. and V-ver. cannot be used. The voltage detection circuit has the reset level detection circuit and the low voltage detection circuit. The reset level detection circuit monitors the voltage applied to the V pin.
Page 65 5. Resets V o l t a g e D e t e c t i o n R e g i s t e r 1 S y m b o l A d d r e s s A f t e r R e s e t ( 2 ) 0 0 0 0...
Page 66 5. Resets Lo w V o l t a g e D e t e c t i o n I n t e r r u p t R e g i s t e r ( 1 ) Symbol Address After Reset...
Page 67: Low Voltage Detection Interrupt
5. Resets 5.5.1 Low Voltage Detection Interrupt If the D40 bit in the D4INT register is set to 1 (low voltge detection interrupt enabled), a low voltage detection interrupt request is generated when voltage applied to the V pin is above or below Vdet4. The low voltage detection interrupt shares the same interrupt vector with watchdog timer interrupt and oscillation stop, re-oscillation detection interrupt.
Page 68 5. Resets Low voltage detection interrupt generation circuit DF1, DF0 D42 bit is set to 0 (not detected) by writing a 0 in a program. VC27 bit is Low voltage detection circuit set to 0 (low voltage detection circuit D4INT clock(the disabled), the D42 bit is set to 0.
Page 69: Limitations On Stop Mode
5. Resets 5.5.2. Limitations on Stop Mode When all the conditions below are met, the low voltage detection interrupt is generated and the MCU exits stop mode as soon as the CM10 bit in the CM1 register is set to 1 (all clocks stopped). •...
Page 70: Processor Mode
6. Processor Mode 6. Processor Mode The MCU supports single-chip mode only. Figures 6.1 and 6.2 show the associated registers. Processor Mode Register 0 Symbol Address After Reset 0004 Bit Symbol Bit Name Function Reserved bit Set to 0 (b2-b0) The MCU is reset when PM03 Software reset bit...
Page 71 6. Processor Mode Processeor Mode Register 2 Symbol Address After Reset 001E XXX00000 Bit Symbol Bit Name Function Specifying wait when 0: 2 waits PM20 accessing SFR (2) 1: 1 wait 0: Clock is protected by PRCR System clock protective register PM21 bit (3,4)
Page 72 6. Processor Mode The internal bus consists of CPU bus, memory bus, and peripheral bus. Bus Interface Unit (BIU) is used to interfere with CPU, ROM/RAM, and perpheral functions by controling CPU bus, memory bus, and periph- eral bus. Figure 6.3 shows the block diagram of the internal bus. CPU address bus Memory address bus CPU data bus...
Page 73: Clock Generation Circuit
7. Clock Generation Circuit 7. Clock Generation Circuit The clock generation circuit contains four oscillator circuits as follows: (1) Main clock oscillation circuit (2) Sub clock oscillation circuit (3) Variable on-chip oscillators (4) PLL frequency synthesizer Table 7.1 lists the specifications of the clock generation circuit. Figure 7.1 shows the clock generation circuit.
Page 74 7. Clock Generation Circuit CCLK2-CCLK0=000 CCLK2-CCLK0=001 CCLK2-CCLK0=010 CCLK2-CCLK0=011 CCLK2-CCLK0=100 CAN module system clock divider PCLK5=0,CM01-CM00=00 I/O ports PCLK5=0,CM01-CM00=01 Sub-clock generating circuit PCLK5=1, PCLK5=0, COUT CM01-CM00=00 PCLK5=0, CM01-CM00=10 CM01-CM00=11 1/32 CM04 PCLK0=1 Sub-clock PCLK0=0 Variable On-chip CM21 oscillator on-chip clock oscillator Oscillation 1SIO stop, re-...
Page 75 7. Clock Generation Circuit System Clock Control Register 0 Symbol Address After Reset 0006 01001000 Bit Symbol Bit Name Function Clock output function See Table 7.3 CM00 select bit CM01 Wait Mode peripheral function 0: Do not stop peripheral function clock in wait mode CM02 clock stop bit (10)
Page 76 7. Clock Generation Circuit System Clock Control Register 1 Symbol Address After Reset 0007 00100000 Bit Symbol Bit Name Function All clock stop control bit 0 : Clock on CM10 (4, 6) 1 : All clocks off (stop mode) System clock select bit 1 CM11 0 : Main clock (6, 7)
Page 77 7. Clock Generation Circuit Oscillation Stop Detection Register Symbol Address After Reset 000C 2 (11) 0X000010 Bit Symbol Bit Name Function Oscillation stop, re- 0: Oscillation stop, re-oscillation CM20 detection function disabled oscillation detection bit (7, 9, 10, 11) 1: Oscillation stop, re-oscillation detection function enabled System clock select bit 2 0: Main clock or PLL clock...
Page 78 7. Clock Generation Circuit Peripheral Clock Select Register Symbol Address After Reset PCLKR 025E 00000011 0 0 0 Bit Symbol Bit Name Function Timers A, B clock select bit (Clock source for the timers A, 0: f PCLK0 B, the timer S, the dead timer, 1: f SI/O3, SI/O4 and multi-master C bus)
Page 79 7. Clock Generation Circuit PLL Control Register 0 (1,2) Symbol Address After Reset PLC0 001C 0001X010 Bit Name Function Symbol PLL multiplying factor b1b0 PLC00 0 0 0: Do not set select bit 0 0 1: Multiply by 2 0 1 0: Multiply by 4 0 1 1: PLC01 1 0 0:...
Page 80: Main Clock
7. Clock Generation Circuit The following describes the clocks generated by the clock generation circuit. 7.1 Main Clock The main clock is generated by the main clock oscillation circuit. This clock is used as the clock source for the CPU and peripheral function clocks. The main clock oscillator circuit is configured by connecting a resonator between the X and X pins.
Page 81: Sub Clock
7. Clock Generation Circuit 7.2 Sub Clock The sub clock is generated by the sub clock oscillation circuit. This clock is used as the clock source for the CPU clock, as well as the timer A and timer B count sources. The sub clock oscillator circuit is configured by connecting a crystal resonator between the X and X COUT...
Page 82: On-Chip Oscillator Clock
7. Clock Generation Circuit 7.3 On-chip Oscillator Clock This clock is supplied by a variable on-chip oscillator. This clock is used as the clock source for the CPU and peripheral function clocks. In addition, if the PM22 bit in the PM2 register is 1 (on-chip oscillator clock for the watchdog timer count source), this clock is used as the count source for the watchdog timer (Refer to 10.
Page 83 7. Clock Generation Circuit START Set the CM07 bit to 0 (main clock), bits CM17 and CM16 to (main clock undivided), and the CM06 bit to 0 (bits CM17 and CM16 enabled). Set bits PLC02 to PLC00 (multiplying factor). (To select a 16 MHz or higher PLL clock) Set the PM20 bit to 0 (2-wait states).
Page 84: Cpu Clock And Peripheral Function Clock
7. Clock Generation Circuit 7.5 CPU Clock and Peripheral Function Clock The CPU clock is used to operate the CPU and peripheral function clocks are used to operate the peripheral functions. 7.5.1 CPU Clock This is the operating clock for the CPU and watchdog timer. The clock source for the CPU clock can be chosen to be the main clock, sub clock, on-chip oscillator clock or the PLL clock.
Page 85: Power Control
7. Clock Generation Circuit 7.6 Power Control There are three power control modes. In this chapter, all modes other than wait and stop modes are referred to as normal operation mode. 7.6.1 Normal Operation Mode Normal operation mode is further classified into seven modes. In normal operation mode, because the CPU clock and the peripheral function clocks both are on, the CPU and the peripheral functions are operating.
Page 86: Wait Mode
7. Clock Generation Circuit 7.6.1.6 On-chip Oscillator Mode The selected on-chip oscillator clock divided by 1 (undivided), 2, 4, 8 or 16 provides the CPU clock. The on-chip oscillator clock is also the clock source for the peripheral function clocks. If the sub clock is on, f can be used as the count source for timers A and B.
Page 87 7. Clock Generation Circuit 7.6.2.3 Pin Status During Wait Mode Table 7.5 lists pin status during wait mode. Table 7.5 Pin Status in Wait Mode Status I/O ports Retains status before wait mode When fC selected Does not stop When f1, f8, f32 selected Does not stop when the CM02 bit is set to 0 Retains status before wait mode when the CM02 bit is set to 1 7.6.2.4 Exiting Wait Mode...
Page 88: Stop Mode
7. Clock Generation Circuit 7.6.3 Stop Mode In stop mode, all oscillator circuits are turned off, so are the CPU clock and the peripheral function clocks. Therefore, the CPU and the peripheral functions clocked by these clocks stop operating. The least amount of power is consumed in this mode.
Page 89 7. Clock Generation Circuit Figure 7.11 shows the state transition from normal operation mode to stop mode and wait mode. Figure 7.12 shows the state transition in normal operation mode. Table 7.7 shows a state transition matrix describing allowed transition and setting. The vertical line shows current state and horizontal line shows state after transition.
Page 90 7. Clock Generation Circuit Main clock oscillation On-chip oscillator clock oscillation On-chip oscillator low power Middle-speed mode Middle-speed mode Middle-speed mode PLL operation mode Middle-speed mode On-chip oscillator mode PLC07=1 dissipation mode High-speed mode (divide by 4) (divide by 8) (divide by 16) (divide by 2) CM11=1...
Page 91 7. Clock Generation Circuit Table 7.7 Allowed Transition and Setting State after transition On-chip oscillator On-chip oscillator High-speed mode, Low power PLL operation Low-speed mode 2 low power mode 2 Stop mode Wait mode mode middle-speed mode dissipation mode dissipation mode High-speed mode, (9) 7 (13) 3...
Page 92: System Clock Protective Function
7. Clock Generation Circuit 7.7 System Clock Protective Function When the main clock is selected for the CPU clock source, this function protects the clock from modifica- tions in order to prevent the CPU clock from becoming halted by run-away. If the PM21 bit in the PM2 register is set to 1 (clock modification disabled), the following bits are protected against writes: •...
Page 93: Operation When Cm27 Bit = 0 (Oscillation Stop Detection Reset)
7. Clock Generation Circuit 7.8.1 Operation When CM27 bit = 0 (Oscillation Stop Detection Reset) When main clock stop is detected when the CM20 bit is 1 (oscillation stop, re-oscillation detection func- tion enabled), the MCU is initialized, coming to a halt (oscillation stop reset; refer to “SFR”, “Reset”). This status is reset with hardware reset 1.
Page 94: How To Use Oscillation Stop And Re-Oscillation Detect Function
7. Clock Generation Circuit 7.8.3 How to Use Oscillation Stop and Re-oscillation Detect Function • The oscillation stop and re-oscillation detect interrupt shares the vector with the watchdog timer inter- rupt. If the oscillation stop, re-oscillation detection and watchdog timer interrupts both are used, read the CM22 bit in an interrupt routine to determine which interrupt source is requesting the interrupt.
Page 95: Protection
8. Protection 8. Protection In the event that a program runs out of control, this function protects the important registers so that they will not be rewritten easily. Figure 8.1 shows the PRCR register. The following lists the registers protected by the PRCR register.
Page 96: Interrupts
9. Interrupts 9. Interrupts Note The SI/O4 interrupt of peripheral function interrupts is not available in the 64-pin package. The low voltage detection function is not available in M16C/29 T-ver. and V-ver.. 9.1 Type of Interrupts Figure 9.1 shows types of interrupts. Undefined instruction (UND instruction) Overflow (INTO instruction) Software...
Page 97: Software Interrupts
9. Interrupts 9.1.1 Software Interrupts A software interrupt occurs when executing certain instructions. Software interrupts are non-maskable interrupts. 9.1.1.1 Undefined Instruction Interrupt An undefined instruction interrupt occurs when executing the UND instruction. 9.1.1.2 Overflow Interrupt An overflow interrupt occurs when executing the INTO instruction with the O flag set to 1 (the opera- tion resulted in an overflow).
Page 98: Hardware Interrupts
9. Interrupts 9.1.2 Hardware Interrupts Hardware interrupts are classified into two types — special interrupts and peripheral function interrupts. 9.1.2.1 Special Interrupts Special interrupts are non-maskable interrupts. _______ 9.1.2.1.1 NMI Interrupt _______ _______ An NMI interrupt is generated when input on the NMI pin changes state from high to low. For details _______ about the NMI interrupt, refer to the section "NMI interrupt".
Page 99: Interrupts And Interrupt Vector
9. Interrupts 9.2 Interrupts and Interrupt Vector One interrupt vector consists of 4 bytes. Set the start address of each interrupt routine in the respective interrupt vectors. When an interrupt request is accepted, the CPU branches to the address set in the corresponding interrupt vector.
Page 100: Relocatable Vector Tables
9. Interrupts 9.2.2 Relocatable Vector Tables The 256 bytes beginning with the start address set in the INTB register comprise a reloacatable vector table area. Table 9.2 lists the relocatable vector tables. Setting an even address in the INTB register results in the interrupt sequence being executed faster than in the case of odd addresses.
Page 101: Interrupt Control
9. Interrupts 9.3 Interrupt Control The following describes how to enable/disable the maskable interrupts, and how to set the priority in which order they are accepted. What is explained here does not apply to nonmaskable interrupts. Use I flag in the the FLG register, IPL, and bits ILVL2 to ILVL0 in the each interrupt control register to enable/disable the maskable interrupts.
Page 102 9. Interrupts Interrupt Control Register Symbol Address After reset C01WKIC 0041 XXXXX000 C0RECIC 0042 XXXXX000 C0TRMIC 0043 XXXXX000 ICOC0IC 0045 XXXXX000 ICOC1IC, IICIC 0046 XXXXX000 BTIC, SCLDAIC 0047 XXXXX000 BCNIC 004A XXXXX000 DM0IC, DM1IC 004B , 004C XXXXX000 C01ERRIC 004D XXXXX000 ADIC, KUPIC 004E...
Page 103 9. Interrupts Interrupt Request Cause Select Register Symbol Address After Reset IFSR 035F Bit Symbol Bit Name Function IFSR0 INT0 interrupt polarity 0 : One edge switching bit 1 : Both edges IFSR1 INT1 interrupt polarity 0 : One edge switching bit 1 : Both edges IFSR2...
Page 104: I Flag
9. Interrupts 9.3.1 I Flag The I flag enables or disables the maskable interrupt. Setting the I flag to 1 (= enabled) enables the maskable interrupt. Setting the I flag to 0 (= disabled) disables all maskable interrupts. 9.3.2 IR Bit The IR bit is set to 1 (= interrupt requested) when an interrupt request is generated.
Page 105: Interrupt Sequence
9. Interrupts 9.4 Interrupt Sequence An interrupt sequence (the device behavior from the instant an interrupt is accepted to the instant the interrupt routine is executed) is described here. If an interrupt occurs during execution of an instruction, the processor determines its priority when the execution of the instruction is completed, and transfers control to the interrupt sequence from the next cycle.
Page 106: Interrupt Response Time
9. Interrupts 9.4.1 Interrupt Response Time Figure 9.6 shows the interrupt response time. The interrupt response or interrupt acknowledge time denotes time from when an interrupt request is generated till when the first instruction in the interrupt routine is executed. Specifically, it consists of the time from when an interrupt request is generated till when the instruction then executing is completed ((a) in Figure 9.6) and the time during which the inter- rupt sequence is executed ((b) in Figure 9.6).
Page 107: Saving Registers
9. Interrupts 9.4.3 Saving Registers In the interrupt sequence, the FLG register and PC are saved to the stack. At this time, the 4 high-order bits of the PC and the 4 high-order (IPL) and 8 low-order bits of the FLG register, 16 bits in total, are saved to the stack first.
Page 108 9. Interrupts The operation of saving registers carried out in the interrupt sequence is dependent on whether the SP at the time of acceptance of an interrupt request, is even or odd. If the stack pointer is even, the FLG register and the PC are saved, 16 bits at a time.
Page 109: Returning From An Interrupt Routine
9. Interrupts 9.4.4 Returning from an Interrupt Routine The FLG register and PC in the state in which they were immediately before entering the interrupt se- quence are restored from the stack by executing the REIT instruction at the end of the interrupt routine. Thereafter the CPU returns to the program which was being executed before accepting the interrupt request.
Page 110 9. Interrupts Priority level of each interrupt Level 0 (initial value) Highest INT1 Timer B2 Timer B0 Timer A3 Timer A1 ICOC interrupt 1, I C bus interface INT3 INT2 INT0 Timer B1 Timer A4 Timer A2 ICOC base timer, S ICOC interrupt 0 UART1 reception UART0 reception...
Page 111: Int Interrupt
9. Interrupts ______ 9.6 INT Interrupt _______ INTi interrupt (i=0 to 5) is triggered by the edges of external inputs. The edge polarity is selected using the IFSRi bit in the IFSR register. ________ The INT5 input has an effective digital debounce function for a noise rejection. Refer to "19.6 Digital ________ Debounce function"...
Page 112: Nmi Interrupt
9. Interrupts ______ 9.7 NMI Interrupt _______ _______ An NMI interrupt request is generated when input on the NMI pin changes state from high to low, after the _______ ______ NMI interrupt was enabled by writing a 1 to bit 4 in the register PM2. The NMI interrupt is a non-maskable interrupt, once it is enabled.
Page 113: Can0 Wake-Up Interrupt
9. Interrupts 9.9 CAN0 Wake-up Interrupt CAN0 wake-up interrupt occurs when a falling edge is input to CRX. The CAN0 wake-up interrupt is en- abled when the PortEn bit is set to 1 (CTX/CRX function) and Sleep bit is set to 1(Sleep mode enabled) in the C0CTLR register.
Page 114 9. Interrupts Table 9.6 PC Value Saved in Stack Area When Address Match Interrupt Request Is Acknowledged Value of the PC that is Instruction at the address indicated by the RMADi register saved to the stack area The address • 2-byte op-code instruction indicated by the •...
Page 115: Watchdog Timer
10. Watchdog Timer 10. Watchdog Timer The watchdog timer is the function of detecting when the program is out of control. Therefore, we recommend using the watchdog timer to improve reliability of a system. The watchdog timer contains a 15-bit counter which counts down the clock derived by dividing the CPU clock using the prescaler.
Page 116: Count Source Protective Mode
10. Watchdog Timer Watchdog Timer Control Register Symbol Addres s After Reset 000F 00XXXXXX Bit Symbol Bit Name Function High-order bits of watchdog timer (b4-b0) Reserved bit Set to 0 (b5) Reserved bit Set to 0 (b6) 0 : Divided by 16 Prescaler select bit WDC7 1 : Divided by 128...
Page 117: Dmac
11. DMAC 11. DMAC Note Do not use SI/O4 interrupt request as a DMA request in the 64-pin package. The DMAC (Direct Memory Access Controller) allows data to be transferred without the CPU intervention. Two DMAC channels are included. Each time a DMA request occurs, the DMAC transfers one (8 or 16-bit) data from the source address to the destination address.
Page 118 11. DMAC Table 11.1 DMAC Specifications Item Specification No. of channels 2 (cycle steal method) Transfer memory space • From any address in the 1M bytes space to a fixed address • From a fixed address to any address in the 1M bytes space •...
Page 119 11. DMAC DMA0 Request Cause Select Register Symbol Address After Reset DM0SL 03B8 Bit Symbol Bit Name Function DSEL0 DSEL1 DMA request cause Refer to note (1) select bit DSEL2 DSEL3 Nothing is assigned. When write, set to 0. (b5-b4) When read, their content are 0 DMA request cause 0: Basic cause of request...
Page 120 11. DMAC DMA1 Request Cause Select Register Symbol Address After Reset DM1SL 03BA Function Bit Name Bit Symbol DSEL0 DMA request cause Refer to note (1) select bit DSEL1 DSEL2 DSEL3 Nothing is assigned. If necessary, set (b5-b4) to 0. When read, their contents are 0 DMA request cause 0: Basic cause of request expansion select bit...
Page 121 11. DMAC DMAi Source Pointer (i = 0, 1) (b19) (b16)(b15) (b8) (b23) Symbol Address After Reset SAR0 0022 to 0020 Undefined SAR1 0032 to 0030 Undefined Function Setting Range Set the source address of transfer 00000 to FFFFF Nothing is assigned. If necessary, set 0. When read, the contents are 0 NOTE: 1.
Page 122: Transfer Cycles
11. DMAC 11.1 Transfer Cycles The transfer cycle consists of a memory or SFR read (source read) bus cycle and a write (destination write) bus cycle. The number of read and write bus cycles is affected by the source and destination addresses of transfer.
Page 123 11. DMAC (1) When the transfer unit is 8 or 16 bits and the source of transfer is an even address CPU clock Address Dummy CPU use Source Destination CPU use cycle RD signal WR signal Data Dummy CPU use Source Destination CPU use...
Page 124: Dma Transfer Cycles
11. DMAC 11.2. DMA Transfer Cycles Any combination of even or odd transfer read and write adresses is possible. Table 11.2 shows the number of DMA transfer cycles. Table 11.3 shows the Coefficient j, k. The number of DMAC transfer cycles can be calculated as follows: No.
Page 125: Dma Enable
11. DMAC 11.3 DMA Enable When a data transfer starts after setting the DMAE bit in the DMiCON register (i = 0, 1) to 1 (enabled), the DMAC operates as follows: (a) Reload the forward address pointer with the SARi register value when the DSD bit in DMiCON register is 1 (forward) or the DARi register value when the DAD bit in the DMiCON register is 1 (forward).
Page 126: Channel Priority And Dma Transfer Timing
11. DMAC 11.5 Channel Priority and DMA Transfer Timing If both DMA0 and DMA1 are enabled and DMA transfer request signals from DMA0 and DMA1 are de- tected active in the same sampling period (one period from a falling edge to the next falling edge of CPU clock), the DMAS bit on each channel is set to 1 (DMA requested) at the same time.
Page 127: Timers
12. Timers 12. Timers Eight 16-bit timers, each capable of operating independently of the others, can be classified by function as either timer A (five) and timer B (three). The count source for each timer acts as a clock, to control such timer operations as counting, reloading, etc.
Page 128 12. Timer PCLK0 bit = 0 Clock prescaler • Main clock 1 or • PLL clock 1/32 PCLK0 bit = 1 • On-chip oscillator Reset clock Set the CPSR bit in the CPSRF register to 1 (prescaler reset) 1 or Timer B2 overflow or underflow ( to Timer A count source) •...
Page 129: Timer A
12. Timer A 12.1 Timer A Figure 12.3 shows a block diagram of the timer A. Figures 12.4 to 12.6 show registers related to the timer A. The timer A supports the following four modes. Except in event counter mode, timers A0 to A4 all have the same function.
Page 130 12. Timer A Timer Ai Register (i= 0 to 4) Symbol Address After Reset (b15) (b8) 0387 , 0386 Undefined b0 b7 0389 , 0388 Undefined 038B , 038A Undefined 038D , 038C Undefined 038F , 038E Undefined Mode Function Setting Range Timer Divide the count source by n + 1 where n = set...
Page 131 12. Timer A One-shot Start Flag Symbol Address After Reset ONSF 0382 Bit Symbol Bit Name Function Timer A0 one-shot start flag The timer starts counting by setting TA0OS this bit to 1 while bits TMOD1 and Timer A1 one-shot start flag TA1OS TMOD0 in the TAiMR register (i = 0 to 4) = 10...
Page 132: Timer Mode
12. Timer A 12.1.1 Timer Mode In timer mode, the timer counts a count source generated internally (see Table 12.1). Figure 12.7 shows TAiMR register in timer mode. Table 12.1 Specifications in Timer Mode Item Specification Count source Count operation •...
Page 133: Event Counter Mode
12. Timer A 12.1.2 Event Counter Mode In event counter mode, the timer counts pulses from an external device or overflows and underflows of other timers. Timers A2, A3, and A4 can count two-phase external signals. Table 12.2 lists specifica- tions in event counter mode (when not processing two-phase pulse signal).
Page 134 12. Timer A Timer Ai Mode Register (i=0 to 4) (When not using two-phase pulse signal processing) Symbol Address After Reset TA0MR to TA4MR 0396 to 039A Bit Symbol Bit Name Function TMOD0 b1 b0 Operation mode select bit 0 1 : Event counter mode TMOD1 0: Pulse is not output Pulse output function...
Page 135 12. Timer A Table 12.3 Specifications in Event Counter Mode (when processing two-phase pulse signal with timers A2, A3 and A4) Item Specification Count source • Two-phase pulse signals input to TAi or TAi pins (i = 2 to 4) Count operation •...
Page 136 12. Timer A Timer Ai Mode Register (i=2 to 4) (When using two-phase pulse signal processing) Symbol Address After Reset TA2MR to TA4MR 0398 to 039A Bit Symbol Bit Name Function TMOD0 b1 b0 Operation mode select bit 0 1: Event counter mode TMOD1 To use two-phase pulse signal processing, set this bit to 0 To use two-phase pulse signal processing, set this bit to 0...
Page 137 12. Timer A 12.1.2.1 Counter Initialization by Two-Phase Pulse Signal Processing This function initializes the timer count value to 0 by Z-phase (counter initialization) input during two- phase pulse signal processing. This function can only be used in timer A3 event counter mode during two-phase pulse signal process- _______ ing, free-running type, x4 processing, with Z-phase entered from the INT2 pin.
Page 138: One-Shot Timer Mode
12. Timer A 12.1.3 One-shot Timer Mode In one-shot timer mode, the timer is activated only once by one trigger. (See Table 12.4) When the trigger occurs, the timer starts up and continues operating for a given period. Figure 12.11 shows the TAiMR register in one-shot timer mode.
Page 139 12. Timer A Timer Ai Mode Register (i=0 to 4) Symbol Address After Reset TA0MR to TA4MR to 039A Bit Symbol Bit Name Function TMOD0 b1 b0 Operation mode select bit 1 0: One-shot timer mode TMOD1 0: Pulse is not output (TA pin functions iOUT Pulse output function...
Page 140: Pulse Width Modulation (Pwm) Mode
12. Timer A 12.1.4 Pulse Width Modulation (PWM) Mode In PWM mode, the timer outputs pulses of a given width in succession (see Table 12.5). The counter functions as either 16-bit pulse width modulator or 8-bit pulse width modulator. Figure 12.12 shows TAiMR register in pulse width modulation mode.
Page 141 12. Timer A Timer Ai Mode Register (i= 0 to 4) Symbol Address After Reset TA0MR to TA4MR 0396 to 039A Bit Symbol Bit Name Function TMOD0 b1 b0 Operation mode select bit 1 1: PWM mode TMOD1 0: Pulse is not output (TAiOUT pin functions as I/O Pulse output funcion port) select bit...
Page 142 12. Timer A 1 / f – 1) Count source “H” Input signal to “L” Trigger is not generated by this signal 1 / f “H” PWM pulse output from TA iOUT “L” IR bit in the TAiIC register : Frequency of count source Set to 0 upon accepting an interrupt request or by program i = 0 to 4 NOTES:...
Page 143: Timer B
12. Timer B 12.2 Timer B Figure 12.15 shows a block diagram of the timer B. Figures 12.16 and 12.17 show registers related to the timer B. Timer B supports the following four modes. Use bits TMOD1 and TMOD0 in the TBiMR register (i = 0 to 2) to select the desired mode.
Page 144 12. Timer B Timer Bi Register (i=0 to 2 )(1) Symbol Address After Reset 0391 , 0390 Undefined (b15) b0 b7 0393 , 0392 Undefined 0395 , 0394 Undefined Function Setting Rrange Mode Divide the count source by n + 1 0000 to FFFF Timer mode...
Page 145: Timer Mode
12. Timer B 12.2.1 Timer Mode In timer mode, the timer counts a count source generated internally (see Table 12.6). Figure 12.18 shows TBiMR register in timer mode. Table 12.6 Specifications in Timer Mode Item Specification Count source Count operation •...
Page 146: Event Counter Mode
12. Timer B 12.2.2 Event Counter Mode In event counter mode, the timer counts pulses from an external device or overflows and underflows of other timers (see Table 12.7). Figure 12.19 shows the TBiMR register in event counter mode. Table 12.7 Specifications in Event Counter Mode Item Specification Count source...
Page 147: Pulse Period And Pulse Width Measurement Mode
12. Timer B 12.2.3 Pulse Period and Pulse Width Measurement Mode In pulse period and pulse width measurement mode, the timer measures pulse period or pulse width of an external signal (see Table 12.8). Figure 12.20 shows the TBiMR register in pulse period and pulse width measurement mode.
Page 148 12. Timer B Count source “H” Measurement pulse “L” Transfer Transfer (undefined value) (measured value) Reload register counter transfer timing Timing at which counter reaches 0000 TBiS bit TBiIC register's IR bit Set to 0 upon accepting an interrupt request or by program TBiMR register's MR3 bit Bits TB0S to TB2S are assigned to the bit 5 to bit 7 in the TABSR register.
Page 149: A/D Trigger Mode
12. Timer B 12.2.4 A/D Trigger Mode A/D trigger mode is used together with simultaneous sample sweep mode or delayed trigger mode 0 of A/D conversion to start A/D conversion. It is used in timer B0 and timer B1 only. In this mode, the timer starts counting by one trigger until the count value becomes 0000 .
Page 150 12. Timer B Timer Bi Mode Register (i= 0 to 1) Symbol Address After Reset TB0MR to TB1MR 039B to 039C 00XX0000 Function Bit Symbol Bit Name TMOD0 b1 b0 Operation mode select bit 0 0: Timer mode or A/D trigger mode TMOD1 Invalid in A/D trigger mode Either 0 or 1 is enabled...
Page 151: Three-Phase Motor Control Timer Function
12. Timer (Three-phase Motor Control Timer Function) 12.3 Three-phase Motor Control Timer Function Timers A1, A2, A4 and B2 can be used to output three-phase motor drive waveforms. Table 12.10 lists the specifications of the three-phase motor control timer function. Figure 12.24 shows the block diagram for three-phase motor control timer function.
Page 152 12. Timer (Three-phase Motor Control Timer Function) Figure 12.25 Three-phase Motor Control Timer Functions Block Diagram page 126...
Page 153 12. Timer (Three-phase Motor Control Timer Function) Three-phase PWM Control Register 0 b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address After Reset INVC0 0348 Bit Symbol Bit Name Function 0: ICTB2 counter is incremented by 1 on the rising edge of timer A1 reload control Effective interrupt output signal INV00...
Page 154 12. Timer (Three-phase Motor Control Timer Function) Three-phase PWM Control Register 1 b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address After Reset INVC1 0349 Bit Symbol Bit Name Function Timer A1, A2, A4 start 0: Timer B2 underflow INV10 trigger signal select bit 1: Timer B2 underflow and write to the...
Page 155 12. Timer (Three-phase Motor Control Timer Function) Three-phase Output Buffer Register(i=0,1) Symbol Address After Reset IDB0 034A 00111111 IDB1 034B 00111111 Bit Symbol Bit Name Function Write the output level U phase output buffer i 0: Active level 1: Inactive level DUBi U phase output buffer i When read, these bits show the three-phase...
Page 156 12. Timer (Three-phase Motor Control Timer Function) Timer Ai, Ai-1 Register (i=1, 2, 4) (1, 2, 3, 4, 5) Symbol Address After reset 0389 -0388 Undefined 038B -038A Undefined (b15) (b8) 038F -038E Undefined b0 b7 (6,7) TA11 0343 -0342 Undefined (6,7) TA21...
Page 157 12. Timer (Three-phase Motor Control Timer Function) Timer B2 Special Mode Register Symbol Address After Reset TB2SC 039E X0000000 Bit Symbol Bit Name Function Timer B2 reload timing PWCON 0: Timer B2 underflow switch bit 1: Timer A output at odd-numbered Three-phase output port 0: Three-phase output forcible cutoff by SD pin input IVPCR1...
Page 158 12. Timer (Three-phase Motor Control Timer Function) Timer B2 Register (b15) (b8) b0 b7 Symbol Address After Reset 0395 -0394 Undefined Setting Range Function 0000 to FFFF Divide the count source by n + 1 where n = set value. Timer A1, A2 and A4 are started at every occurrence of underflow.
Page 159 12. Timer (Three-phase Motor Control Timer Function) Timer Ai Mode Register Symbol Address After Reset b7 b6 b5 b4 b3 b2 b1 b0 TA1MR 0397 TA2MR 0398 TA4MR 039A Bit Symbol Bit Name Function TMOD0 Set to 10 (one-shot timer mode) for the Operation mode three-phase motor control timer function select bit...
Page 160 12. Timer (Three-phase Motor Control Timer Function) The three-phase motor control timer function is enabled by setting the INV02 bit in the INVC0 register to 1. When this function is on, timer B2 is used to control the carrier wave, and timers A4, A1 and A2 are used to control three-phase PWM outputs (U, U, V, V, W and W).
Page 161 12. Timer (Three-phase Motor Control Timer Function) Sawtooth Waveform as a Carrier Wave Sawtooth wave Signal wave Timer B2 Start trigger signal for timer A4 Timer A4 one-shot pulse Rewrite registers Transfer the values to the three- IDB0 and IDB1 phase output shift register U phase output signal...
Page 162: Position-Data-Retain Function
12. Timer (Three-phase Motor Control Timer Function) 12.3.1 Position-Data-Retain Function This function is used to retain the position data synchronously with the three-phase waveform output.There are three position-data input pins for U, V, and W phases. A trigger to retain the position data (hereafter, this trigger is referred to as "retain trigger") can be selected by the PDRT bit in the PDRF register.
Page 163 12. Timer (Three-phase Motor Control Timer Function) 12.3.1.2 Position-data-retain Function Control Register Figure 12.36 shows the structure of the position-data-retain function contol register. Position-Data-Retain Function Control Register Symbol Address After Reset PDRF 034E XXXX 0000 Bit Symbol Bit Name Function Input level at pin IDW is read out.
Page 164: Three-Phase/Port Output Switch Function
12. Timer (Three-phase Motor Control Timer Function) 12.3.2 Three-phase/Port Output Switch Function When the INVC03 bit in the INVC0 register set to 1 (Timer output enabled for three-phase motor control) and setting the PFCi (i=0 to 5) in the PFCR register to 0 (I/O port), the three-phase PWM output pin (U, U, V, V, W and W) functions as I/O port.
Page 165 12. Timer (Three-phase Motor Control Timer Function) Port Function Control Register Symbol Address After Reset PFCR 0358 0011 1111 Bit Symbol Bit Name Function 0: Input/Output port P8 Port P8 output PFC0 1: Three-phase PWM output function select bit (U phase output) 0: Input/Output port P8 Port P8 output...
Page 166: Timer S
13. Timer S 13. Timer S The Timer S (Input Capture/Output Compare : here after, Timer S is referred to as "IC/OC".) is a high- performance I/O port for time measurement and waveform generation. The IC/OC has one 16-bit base timer for free-running operation and eight 16-bit registers for time measure- ment and waveform generation.
Page 167 13. Timer S Figure 13.1 shows the block diagram of the IC/OC. PCLK0=0 Main clock, PLL clock, or f On-chip PCLK0=1 oscillator clock Request by matching G1BTRR and base timer Request by matching G1PO0 register and base timer Request from INT1 pin Base timer reset BCK1 to BCK0 or f...
Page 168 13. Timer S Figures 13.2 to 13.10 show registers associated with the IC/OC base timer, the time measurement func- tion, and the waveform generating function. Base Timer Register Symbol Address After Reset (b7) (b0) G1BT 0321 - 0320 Undefined Setting Range Function When the base timer is operating: When read, the value of base timer plus 1 can...
Page 169 13. Timer S Divider Register Symbol Address After Reset G1DV 032A Function Setting range Divide f or two-phase pulse input by (n+1) to FF for f clock cycles generation. n: the setting value of the G1DV register Base Timer Control Register 1 Symbol Address After Reset...
Page 170 13. Timer S Base Timer Reset Register Symbol Address After Reset (b7) (b0) G1BTRR 0329 - 0328 Undefined Function Setting Range When enabled by the RST4 bit in the G1BCR0 0000 to FFFF register, the base timer is reset by matching the G1BTRR register setting value and the base timer setting value.
Page 171 13. Timer S Time Measurement Control Register j (j=0 to 7) Symbol Address After Reset G1TMCR0 to G1TMCR3 0318 , 0319 , 031A , 031B G1TMCR4 to G1TMCR7 031C , 031D , 031E , 031F Bit Name Function Symbol CTS0 : No time measurement Time measurement : Rising edge...
Page 172 13. Timer S Waveform Generation Register j (j=0 to 7) Symbol Address After Reset (b0) (b7) G1TM0 to G1TM2 0301 -0300 0303 -0302 0305 -0304 Indeterminte G1TM3 to G1TM5 0307 -0306 0309 -0308 030B -030A Indeterminte Indeterminte G1TM6 to G1TM7 030D -030C 030F...
Page 173 13. Timer S Waveform Generation Register j (j=0 to 7) Symbol Address After Reset (b0) (b7) G1PO0 to G1PO2 0301 -0300 0303 -0302 0305 -0304 Undefined G1PO3 to G1PO5 0307 -0306 0309 -0308 030B -030A Undefined Undefined G1PO6 to G1PO7 030D -030C 030F...
Page 174 13. Timer S Function Select Register Symbol Address After Reset G1FS 0327 Bit Name Function Symbol Channel 0 time measure- 0: Select the waveform generating FSC0 ment/waveform generating function function select bit 1: Select the time measurement Channel 1 Time Measure- FSC1 ment/Waveform Generating function...
Page 175 13. Timer S Interrupt Request Register Symbol Address After Reset G1IR 0330 Undefined Bit Name Function Symbol 0 : No interrupt request G1IR0 Interrupt request, Ch0 1 : Interrupt requested G1IR1 Interrupt request, Ch1 G1IR2 Interrupt request, Ch2 G1IR3 Interrupt request, Ch3 G1IR4 Interrupt request, Ch4 G1IR5...
Page 176 13. Timer S Interrupt Enable Register 0 Symbol Address After Reset G1IE0 0331 Bit Name Function Symbol 0 : IC/OC interrupt 0 request disable G1IE00 Interrupt enable 0, CH0 1 : IC/OC interrupt 0 request enable G1IE01 Interrupt enable 0, CH1 G1IE02 Interrupt enable 0, CH2 G1IE03...
Page 177: Base Timer
13. Timer S 13.1 Base Timer The base timer is a free-running counter that counts an internally generated count source. Table 13.2 lists specifications of the base timer. Table 13.3 shows registers associated with the base timer. Figure 13.11 shows a block diagram of the base timer. Figure 13.12 shows an example of the base timer in counter increment mode.
Page 178 13. Timer S BCK1 to BCK0 or f (n+1) divider Base timer b14 b15 Two-phase pulse input (Note 1) Overflow signal Base timer BTS bit in G1BCR1 register overflow request RST4 Matched with G1BTRR RST1 Base timer reset Matched with G1PO0 register RST2 NOTE: Input "L"...
Page 179 13. Timer S FFFF C000 State of a counter 8000 4000 0000 IT=1 in the G1BCR0 register (Base timer interrupt generated by the bit 14 overflow) b14 overflow signal Base Timer interrupts IT=0 in the G1BCR0 register (Base timer interrupt generated by the bit 15 overflow) b15 overflow signal Base Timer interrupt...
Page 180 13. Timer S (1) When the base timer is reset while the base timer increments the counter (A-phase) Input waveform min 1 µs (B-phase) min 1 µs When selects no division with the divider by (n+1) (Note 1) INT1 (Z-phase) Base timer starts counting Value of counter Set to 0 at this timing...
Page 181: Base Timer Reset Register(G1Btrr)
13. Timer S 13.1.1 Base Timer Reset Register(G1BTRR) The G1BTRR register provides the capability to reset the base timer when the base timer count value matches the value stored in the G1BTRR register. The G1BTRR register is enabled by the RST4 bit in the G1BCR0 register.
Page 182: Interrupt Operation
13. Timer S 13.2 Interrupt Operation The IC/OC interrupt contains several request causes. Figure 13.18 shows the IC/OC interrupt block dia- gram and Table 13.4 shows the IC/OC interrupt assignation. When either the base timer reset request or base timer overflow request is generated, the IR bit in the BTIC register corresponding to the IC/OC base timer interrupt is set to 1 (with an interrupt request).
Page 183: Time Measurement Function
13. Timer S 13.4 Time Measurement Function In synchronization with an external trigger input, the value of the base timer is stored into the G1TMj register (j=0 to 7). Table 13.5 shows specifications of the time measurement function. Table 13.6 shows register settings associated with the time measurement function.
Page 184 13. Timer S Table 13.6 Register Settings Associated with the Time Measurement Function Register Function G1TMCRj CTS1 to CTS0 Select time measurement trigger DF1 to DF0 Select the digital filter function GT, GOC, GSC Select the gate function Select the prescaler function G1TPRk Setting value of prescaler G1FS...
Page 185 13. Timer S When selecting the rising edge as a timer measurement trigger (Bits CTS1 and CTS0 in the G1TMCRj register (j=0 to 7)=01 Base timer n+9 n+10 n+11 n+12 n+13 n+14 INPC1j pin input or trigger signal after passing the digital filter G1IRj bit write 0 by program if setting to 0...
Page 186 13. Timer S (a) With the prescaler function (When the G1TPRj register (j = 6, 7) is set to 02 , the PR bit in the G1TMCRj register (j = 6, 7) is set to 1) Base timer n+9 n+10 n+11 +12 n+13 n+14 INPC1j pin input or...
Page 187: Waveform Generating Function
13. Timer S 13.5 Waveform Generating Function Waveforms are generated when the base timer value matches the G1POj (j=0 to 7) register value. The waveform generating function has the following three modes : • Single-phase waveform output mode • Phase-delayed waveform output mode •...
Page 188: Single-Phase Waveform Output Mode
13. Timer S 13.5.1 Single-Phase Waveform Output Mode Output signal level of the OUTC1j pin becomes high ("H") when the INV bit in the G1POCRj (j=0 to 7) register is set to 0(output is not reversed) and the base timer value matches the G1POj (j=0 to 7) register value.
Page 189 13. Timer S (1) Free-running operation (The RST4, RST2, and RST1 bits in the G1BCR0 and G1BCR1 registers are set to 0) FFFF Base timer 0000 65536-m Inverse Inverse OUTC1j pin Return to default output level 65536 When setting to 0, write 0 by program G1IRj bit j=0 to 7...
Page 190: Phase-Delayed Waveform Output Mode
13. Timer S 13.5.2 Phase-Delayed Waveform Output Mode Output signal level of the OUTC1j pin is inversed every time the base timer value matches the G1POj register value ( j=0 to 7). Table 13.9 lists specifications of phase-delayed waveform mode. Figure 13.23 shows an example of phase-delayed waveform mode operation.
Page 191 13. Timer S (1) Free-running operation (Bits RST4, RST2, and RST1 in the registers G1BCR0 and G1BCR1 are set to 0) FFFF Base timer 0000 65536 65536 Inverse OUTC1j pin Inverse 65536X2 Write 0 by program if setting to 0 G1IRj bit j=0 to 7 m : Setting value of the G1POj register...
Page 192: Set/Reset Waveform Output (Sr Waveform Output) Mode
13. Timer S 13.5.3 Set/Reset Waveform Output (SR Waveform Output) Mode Output signal level of the OUTC1j pin becomes high ("H") when the INV bit in the G1POCRi (i=0 to 7) is set to 0 (output is not reversed) and the base timer value matches the G1POj register value (j=0, 2, 4, 6). The "H"...
Page 193 13. Timer S (1) Free-running operation (Bits RST2 and RST1 in the G1BCR0 register and the RST4 bit in the G1BCR1 register are set to 0) FFFF Base timer 0000 65536-n+m Return to default output level OUTC1j pin Inverse Inverse 65536 Write 0 by program if setting to 0...
Page 194: I/O Port Function Select
13. Timer S 13.6 I/O Port Function Select The value in the G1FE and G1FS registers decides which IC/OC pin to be an input or output pin. In SR waveform generating mode, two channels, a set of even channel and odd channel, are used every output waveform, however, the waveform is output from an even channel only.
Page 195: Inpc17 Alternate Input Pin Selection
13. Timer S 13.6.1 INPC17 Alternate Input Pin Selection The input capture pin for IC/OC channel 7 can be assigned to one of two package pins. The CH7INSEL ________ bit in the G1BCR0 register selects IC/OC INPC1 from P2 /OUTC1 /INPC1 or P17/INT5/INPC1 /IDU.
Page 196: Serial I/O
14.Serial I/O 14. Serial I/O Note The SI/O4 interrupt of peripheral function interrupt is not available in the 64-pin package. Serial I/O is configured with five channels: UART0 to UART2, SI/O3 and SI/O4. 14.1 UARTi (i=0 to 2) UARTi each have an exclusive timer to generate a transfer clock, so they operate independently of each other.
Page 197 14. Serial I/O PCLK1=0 2SIO 1SIO or 2SIO 1SIO Main clock, PLL clock, PCLK1=1 or on-chip oscillator clock 8SIO 32SIO (UART0) UART reception Clock source selection Receive 1/16 clock Reception CLK1 to CLK0 Clock synchronous control circuit Transmit/ type U0BRG 1SIO or 2SIO Internal...
Page 198 14.Serial I/O Clock synchronous type UART (7 bits) disabled UART (8 bits) Clock UARTi receive register synchronous UART (7 bits) type STPS=0 PRYE=0 RxDi STPS=1 UART PRYE=1 UART (9 bits) enabled Clock synchronous type UART (8 bits) UART (9 bits) UARTi receive buffer register Address 03A6...
Page 199 14. Serial I/O No reverse IOPOL=0 RxD data RxD2 reverse circuit IOPOL=1 Reverse Clock synchronous type UART (7 bits) disabled UART Clock UARTi receive register UART(7 bits) (8 bits) synchronous STPS=0 PRYE=0 type STPS=1 PRYE=1 Clock UART UART synchronous type enabled (9 bits) UART...
Page 200 14.Serial I/O UARTi Transmit Buffer Register (i=0 to 2) Symbol Address After Reset (b15) (b8) U0TB 03A3 -03A2 Undefined U1TB 03AB -03AA Undefined U2TB 037B -037A Undefined Function Transmit data Nothing is assigned. If necessary, set to 0. When read, their contents are undefined NOTES: 1.
Page 201 14. Serial I/O UARTi Transmit/receive Mode Register (i=0, 1) Symbol Address After Reset U0MR, U1MR 03A0 , 03A8 Function Bit Name Symbol SMD0 b2 b1 b0 Serial I/O mode select bit 0 0 0 : Serial I/O disabled 0 0 1 : Clock synchronous serial I/O mode SMD1 1 0 0 : UART mode transfer data 7 bit long 1 0 1 : UART mode transfer data 8 bit long...
Page 202 14.Serial I/O UARTi Transmit/receive Control Rregister 0 (i=0 to 2) Symbol Address After Reset U0C0 to U2C0 03A4 , 03AC , 037C 00001000 Bit Name Function Symbol b1 b0 CLK0 BRG count source 0 0 : f or f is selected 1SIO 2SIO select bit...
Page 203 14. Serial I/O UARTi Transmit/receive Control Register 1 (i=0, 1) Symbol Address After Reset U0C1, U1C1 03A5 ,03AD 00000010 Function Bit Name Symbol Transmit enable bit 0 : Transmission disabled 1 : Transmission enabled Transmit buffer 0 : Data present in UiTB register empty flag 1 : No data present in UiTB register Receive enable bit...
Page 204 14.Serial I/O UART2 Special Mode Register b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address After Reset U2SMR 0377 X0000000 Function Bit Name Symbol 0 : Other than I C bus mode IICM C bus mode select bit 1 : I C bus mode Arbitration lost detecting 0 : Update per bit...
Page 205 14. Serial I/O UART2 Special Mode Register 3 b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address After Reset U2SMR3 0375 000X0X0X Bit Name Function Symbol Nothing is assigned. If necessary, set to 0. (b0) When read, the content is undefined CKPH Clock phase set bit 0 : Without clock delay...
Page 206: Clock Synchronous Serial I/O Mode
14.Serial I/O 14.1.1 Clock Synchronous serial I/O Mode The clock synchronous serial I/O mode uses a transfer clock to transmit and receive data. Table 14.1 lists the specifications of the clock synchronous serial I/O mode. Table 14.2 lists the registers used in clock synchronous serial I/O mode and the register values set.
Page 207 14. Serial I/O Table 14.2 Registers to Be Used and Settings in Clock Synchronous Serial I/O Mode Register Function UiTB 0 to 7 Set transmission data UiRB 0 to 7 Reception data can be read Overrun error flag UiBRG 0 to 7 Set bit rate UiMR SMD2 to SMD0...
Page 208 14.Serial I/O Table 14.3 lists pin functions for the case where the multiple transfer clock output pin select function is deselected. Table 14.4 lists the P6 pin functions during clock synchronous serial I/O mode. Note that for a period from when the UARTi operation mode is selected to when transfer starts, the TxDi pin outputs an “H”.
Page 209 14. Serial I/O (1) Example of Transmit Timing (Internal clock is selected) Transfer clock UiC1 register Write data to the UiTB register TE bit UiC1 register TI bit Transferred from UiTB register to UARTi transmit register “H” CTSi “L” Stopped pulsing because CTSi = “H” Stopped pulsing because the TE bit = 0 CLKi TxDi...
Page 210 14.Serial I/O 14.1.1.1 Counter Measure for Communication Error Occurs If a communication error occurs while transmitting or receiving in clock synchronous serial I/O mode, follow the procedures below. •Resetting the UiRB register (i=0 to 2) (1) Set the RE bit in the UiC1 register to 0 (reception disabled) (2) Set bits SMD2 to SMD0 in the UiMR register to 000 (Serial I/O disabled) (3) Set bits SMD2 to SMD0 in the UiMR register to 001...
Page 211 14. Serial I/O 14.1.1.2 CLK Polarity Select Function Use the CKPOL bit in the UiC0 register (i=0 to 2) to select the transfer clock polarity. Figure 14.11 shows the polarity of the transfer clock. (1) When the CKPOL bit in the UiC0 register is set to 0 (transmit data output at the falling edge and the receive data taken in at the rising edge of the transfer clock) (2) When the CKPOL bit in the UiC0 register is set to 1 (transmit data output at the rising edge and the receive data taken in at the falling edge of the transfer clock)
Page 212 14.Serial I/O 14.1.1.4 Continuous receive mode When the UiRRM bit (i=0 to 2) is set to 1 (continuous receive mode), the TI bit in the UiC1 register is set to 0 (data present in the UiTB register) by reading the UiRB register. In this case, i.e., UiRRM bit is set to 1, do not write dummy data to the UiTB register in a program.
Page 213 14. Serial I/O _______ _______ 14.1.1.7 CTS/RTS separate function (UART0) _______ _______ _______ _______ This function separates CTS /RTS , outputs RTS from the P6 pin, and accepts as input the CTS from the P6 pin or P7 pin. To use this function, set the register bits as shown below. _______ _______ •...
Page 214: Clock Asynchronous Serial I/O (Uart) Mode
14.Serial I/O 14.1.2 Clock Asynchronous Serial I/O (UART) Mode The UART mode allows transmitting and receiving data after setting the desired bit rate and transfer data format. Table 14.5 lists the specifications of the UART mode. Table 14.5 UART Mode Specifications Item Specification Transfer data format...
Page 215 14. Serial I/O Table 14.6 Registers to Be Used and Settings in UART Mode Register Function UiTB 0 to 8 Set transmission data UiRB 0 to 8 Reception data can be read OER,FER,PER,SUM Error flag UiBRG 0 to 7 Set bit rate UiMR SMD2 to SMD0 Set these bits to 100...
Page 216 14.Serial I/O Table 14.7 lists the functions of the input/output pins in UART mode. Table 14.8 lists the P6 pin func- tions during UART mode. Note that for a period from when the UARTi operation mode is selected to when transfer starts, the TxDi pin outputs an “H”.
Page 217 14. Serial I/O • Example of transmit timing when transfer data is 8-bit long (parity enabled, one stop bit) The transfer clock stops momentarily as CTSi is “H” when the stop bit is checked. The transfer clock starts as the transfer starts immediately CTSi changes to “L”. Transfer clock UiC1 register TE bit...
Page 218 14.Serial I/O • Example of receive timing when transfer data is 8 bits long (parity disabled, one stop bit) UiBRG count source UiC1 register RE bit Stop bit Start RxDi Sampled “L” Receive data taken in Transfer clock Reception triggered when transfer clock Read out from Transferred from UARTi receive is generated by falling edge of start bit...
Page 219 14. Serial I/O 14.1.2.2 Counter Measure for Communication Error If a communication error occurs while transmitting or receiving in UART mode, follow the procedure below. • Resetting the UiRB register (i=0 to 2) (1) Set the RE bit in the UiC1 register to 0 (reception disabled) (2) Set the RE bit in the UiC1 register to 1 (reception enabled) •...
Page 220 14.Serial I/O 14.1.2.4 Serial Data Logic Switching Function (UART2) The data written to the U2TB register has its logic reversed before being transmitted. Similarly, the received data has its logic reversed when read from the U2RB register. Figure 14.19 shows serial data logic.
Page 221 14. Serial I/O _______ _______ 14.1.2.6 CTS/RTS Separate Function (UART0) _______ _______ _______ _______ This function separates CTS /RTS , outputs RTS from the P6 pin, and accepts as input the CTS from the P6 pin or P7 pin. To use this function, set the register bits as shown below. _______ _______ •...
Page 222: Special Mode 1 (I 2 C Bus Mode)(Uart2)
14. Serial I/O 14.1.3 Special Mode 1 (I C bus mode)(UART2) C bus mode is provided for use as a simplifed I C bus interface compatible mode. Table 14.10 lists the specifications of the I C bus mode. Tables 14.11 and 14.12 list the registers used in the I C bus mode and the register values set.
Page 223 14. Serial I/O Start and stop condition generation block SDA2 DMA0, DMA1 request STSPSEL=1 Delay STSP circuit STSP STSPSEL=0 IICM2=1 Transmission UART2 transmit, register NACK interrupt ACKC=1 ACKC=0 request UART2 IICM=1 and IICM2=0 SDHI ACKD bit DMA0 Arbitration Noise Filter IICM2=1 UART2 receive, Reception register...
Page 224 14. Serial I/O Table 14.11 Registers to Be Used and Settings in I C bus mode (1) (Continued) Register Function Master Slave U2TB 0 to 7 Set transmission data Set transmission data U2RB 0 to 7 Reception data can be read Reception data can be read ACK or NACK is set in this bit ACK or NACK is set in this bit...
Page 225 14. Serial I/O Table 14.12 Registers to Be Used and Settings in I C bus Mode (2) (Continued) Register Function Master Slave U2SMR4 STAREQ Set this bit to 1 to generate start Set to 0 condition RSTAREQ Set this bit to 1 to generate restart Set to 0 condition STPREQ...
Page 226 14. Serial I/O Table 14.13 I C bus mode Functions Function Clock synchronous serial I/O C bus mode (SMD2 to SMD0 = 010 , IICM = 1) mode (SMD2 to SMD0 = 001 IICM2 = 0 IICM2 = 1 IICM = 0) (NACK/ACK interrupt) (UART transmit/ receive interrupt) CKPH = 1...
Page 227 14. Serial I/O (1) When the IICM2 bit is set to 0 (ACK or NACK interrupt) and the CKPH bit is set to 0 (No clock delay) SCL2 (ACK or NACK) SDA2 ACK interrupt (DMA request) or NACK interrupt Data is transferred to the U2RB register •••...
Page 228 14. Serial I/O 14.1.3.1 Detection of Start and Stop Condition Whether a start or a stop condition has been detected is determined. A start condition-detected interrupt request is generated when the SDA pin changes state from high to low while the SCL pin is in the high state.
Page 229 14. Serial I/O Table 14.14 STSPSEL Bit Functions Function STSPSEL = 0 STSPSEL = 1 Output of SCL2 and SDA2 pins Output transfer clock and data/ The STAREQ, RSTAREQ and Program with a port determines STPREQ bit determine how the how the start condition or stop start condition or stop condition is condition is output...
Page 230 14. Serial I/O 14.1.3.4 Transfer Clock Data is transmitted/received using a transfer clock like the one shown in Figure 14.25. The CSC bit in the U2SMR2 register is used to synchronize the internally generated clock (internal SCL2) and an external clock supplied to the SCL pin.
Page 231 14. Serial I/O 14.1.3.7 ACK and NACK If the STSPSEL bit in the U2SMR4 register is set to 0 (start and stop conditions not generated) and the ACKC bit in the U2SMR4 register is set to 1 (ACK data output), the value of the ACKD bit in the U2SMR4 register is output from the SDA pin.
Page 232: Special Mode 2 (Uart2)
14. Serial I/O 14.1.4 Special Mode 2 (UART2) Multiple slaves can be serially communicated from one master. Transfer clock polarity and phase are selectable. Table 14.15 lists the specifications of Special Mode 2. Table 14.16 lists the registers used in Special Mode 2 and the register values set.
Page 233 14. Serial I/O (Master) (Slave) (Slave) Figure 14.26 Serial Bus Communication Control Example (UART2) Table 14.16 Registers to Be Used and Settings in Special Mode 2 Register Function U2TB 0 to 7 Set transmission data U2RB 0 to 7 Reception data can be read Overrun error flag U2BRG 0 to 7...
Page 234 14. Serial I/O 14.1.4.1 Clock Phase Setting Function One of four combinations of transfer clock phases and polarities can be selected using the CKPH bit in the U2SMR3 register and the CKPOL bit in the U2C0 register. Make sure the transfer clock polarity and phase are the same for the master and slave to communi- cate.
Page 235 14. Serial I/O "H" Slave control input "L" "H" Clock input "L" (CKPOL=0, CKPH=0) Clock input "H" (CKPOL=1, CKPH=0) "L" "H" Data output timing "L" Data input timing Undefined Figure 14.28 Transmission and Reception Timing (CKPH=0) in Slave Mode (External Clock) "H"...
Page 236: Special Mode 3 (Iebus Mode)(Uart2)
14. Serial I/O 14.1.5 Special Mode 3 (IEBus mode)(UART2) In this mode, one bit in the IEBus is approximated with one byte of UART mode waveform. Table 14.17 lists the registers used in IEBus mode and the register values set. Figure 14.30 shows the functions of bus collision detect function related bits.
Page 237 14. Serial I/O (1) The ABSCS bit in the U2SMR register (bus collision detect sampling clock select) If ABSCS=0, bus collision is determined at the rising edge of the transfer clock Transfer clock TxD2 RxD2 Input to TA0 Timer A0 If ABSCS is set to 1, bus collision is determined when timer A0 (one-shot timer mode) underflows (2) The ACSE bit in the U2SMR register (auto clear of transmit enable bit)
Page 238: Special Mode 4 (Sim Mode) (Uart2)
14. Serial I/O 14.1.6 Special Mode 4 (SIM Mode) (UART2) Based on UART mode, this is an SIM interface compatible mode. Direct and inverse formats can be implemented, and this mode allows output of a low from the TxD2 pin when a parity error is detected. Table 14.18 lists the specifications of SIM mode.
Page 239 14. Serial I/O Table 14.19 Registers to Be Used and Settings in SIM Mode Register Function U2TB 0 to 7 Set transmission data U2RB 0 to 7 Reception data can be read OER,FER,PER,SUM Error flag U2BRG 0 to 7 Set bit rate U2MR SMD2 to SMD0 Set to 101...
Page 240 14. Serial I/O (1) Transmit Timing Transfer Clock TE bit in U2C1 Data is written to register the UART2 register TI bit in U2C1 register Data is transferred from the U2TB register to the UART2 transmit Stop Parity register Start Parity Error Signal returned from An "L"...
Page 241 14. Serial I/O Figure 14.32 shows the example of connecting the SIM interface. Connect T and R and apply pull-up. SIM card Figure 14.32 SIM Interface Connection 14.1.6.1 Parity Error Signal Output The parity error signal is enabled by setting the U2ERE bit in theU2C1 register to 1. •...
Page 242 14. Serial I/O 14.1.6.2 Format • Direct Format Set the PRY bit in the U2MR register to 1, the UFORM bit in U2C0 register to 0 and the U2LCH bit in U2C1 register to 0. • Inverse Format Set the PRY bit to 0, UFORM bit to 1 and U2LCH bit to 1. Figure 14.34 shows the SIM interface format.
Page 243: O3 And Si/O4
14. Serial I/O 14.2 SI/O3 and SI/O4 Note The SI/O4 interrupt of peripheral function interrupt is not available in the 64-pin package. SI/O3 and SI/O4 are exclusive clock-synchronous serial I/Os. Figure 14.35 shows the block diagram of SI/O3 and SI/O4, and Figure 14.36 shows the SI/O3 and SI/O4- related registers.
Page 244 14. Serial I/O SI/Oi Control Register (i = 3, 4) S y m b o l A d d r e s s A f t e r R e s e t S 3 C 0 3 6 2 0 1 0 0 0 0 0 0 S 4 C 0 3 6 6...
Page 245 14. Serial I/O Table 14.20 SI/O3 and SI/O4 Specifications Item Specification Transfer data format • Transfer data length: 8 bits Transfer clock • The SMi6 bit in the SiC (i=3, 4) register is set to 1 (internal clock) : fj/ (2(n+1)) fj = f .
Page 246: Clk Polarity Selection
14. Serial I/O 14.2.1 SI/Oi Operation Timing Figure 14.37 shows the SI/Oi operation timing 1.5 cycle (max) "H" SI/Oi internal clock "L" "H" CLKi output "L" Signal written to the "H" SiTRR register "L" i output "H" "L" "H" i input "L"...
Page 247: Functions For Setting An Souti Initial Value
14. Serial I/O 14.2.3 Functions for Setting an S i Initial Value If the SMi6 bit in SiC register is set to 0 (external clock), the S pin output level can be fixed high or low OUTi when not transferring data. However, when transmitting data consecutively, the last bit (bit 0) value of the last transmitted data is retained between the sccessive data transmissions.
Page 248: A/D Converter
15. A/D Converter 15. A/D Converter Note Ports P0 to P0 (AN0 to AN0 ), P1 to P1 (AN2 to AN2 ) and P9 to P9 (AN2 to AN2 ) are not available in 64-pin package. Do not use port P0 to P0 (AN0 to AN0...
Page 249 15. A/D Converter A/D conversion rate selection CKS1=1 CKS2=0 ø CKS0=1 CKS1=0 CKS0=0 CKS2=1 Resistor ladder VCUT=0 VCUT=1 Successive conversion register ADCON1 register (address 03D7 ADCON0 register (address 03D6 Addresses (03C1 to 03C0 A/D register 0(16) (03C3 to 03C2 A/D register 1(16) (03C5 to 03C4 A/D register 2(16)
Page 250 15. A/D Converter A/D Control Register 0 Symbol Address After Reset ADCON0 03D6 00000XXX Bit Symbol Bit Name Function Analog input pin select bit Function varies with each operation mode b4 b3 0 0: One-shot mode or Delayed trigger mode 0,1 A/D operation mode 0 1: Repeat mode select bit 0...
Page 251 15. A/D Converter A/D Trigger Control Register (1, 2) Symbol Address After Reset ADTRGCON 03D2 Bit Symbol Bit Name Function 0 : Other than simultaneous sample sweep A/D Operation Mode mode or delayed trigger mode 0,1 Select Bit 2 1 : Simultaneous sample sweep mode or delayed trigger mode 0,1 A/D Operation Mode 0 : Other than delayed trigger mode 0,1...
Page 252 15. A/D Converter A/D Conversion Status Register 0 Symbol Address After reset ADSTAT0 03D3 Bit Symbol Bit Name Function AN1 trigger status flag 0: AN1 trigger did not occur during ADERR0 AN0 conversion 1: AN1 trigger occured during AN0 conversion ADERR1 Conversion termination flag 0: Conversion not terminated...
Page 253 15. A/D Converter Timer B2 special mode register After Reset Symbol Address TB2SC 039E X0000000 Bit Symbol Bit Name Function 0: Timer B2 underflow PWCON Timer B2 reload timing switch bit 1: Timer A output at odd-numbered Three-phase output port 0: Three-phase output forcible cutoff IVPCR1 SD control bit 1...
Page 254: Operating Modes
15. A/D Converter 15.1 Operating Modes 15.1.1 One-Shot Mode In one-shot mode, analog voltage applied to a selected pin is once converted to a digital code. Table 15.3 shows the one-shot mode specifications. Figure 15.6 shows the operation example in one-shot mode.
Page 255 15. A/D Converter A/D Control Register 0 Symbol Address After Reset ADCON0 03D6 00000XXX Bit Symbol Bit Name Function b2 b1 b0 Analog input pin 0 0 0: Select AN select bit (2, 3) 0 0 1: Select AN 0 1 0: Select AN 0 1 1: Select AN 1 0 0: Select AN 1 0 1: Select AN...
Page 256: Repeat Mode
15. A/D Converter 15.1.2 Repeat mode In repeat mode, analog voltage applied to a selected pin is repeatedly converted to a digital code. Table 15.4 shows the repeat mode specifications. Figure 15.8 shows the operation example in repeat mode. Figure 15.9 shows the ADCON0 to ADCON2 registers in repeat mode. Table 15.4 Repeat Mode Specifications Item Specification...
Page 257 15. A/D Converter A/D Control Register 0 Symbol Address After Reset ADCON0 03D6 00000XXX Bit Symbol Bit Name Function b2 b1 b0 0 0 0: Select AN 0 0 1: Select AN 0 1 0: Select AN 0 1 1: Select AN Analog input pin select 1 0 0: Select AN (2, 3)
Page 258: Single Sweep Mode
15. A/D Converter 15.1.3 Single Sweep Mode In single sweep mode, analog voltages applied to the selected pins are converted one-by-one to a digital code. Table 15.5 shows the single sweep mode specifications. Figure 15.10 shows the operation example in single sweep mode. Figure 15.11 shows the ADCON0 to ADCON2 registers in single sweep mode.
Page 259 15. A/D Converter A/D Control Register 0 Symbol Address After Reset ADCON0 03D6 00000XXX Bit Symbol Bit Name Function Analog input pin select bit Invalid in single sweep mode b4 b3 A/D operation mode 1 0: Single sweep mode or Simultaneous select bit 0 sample sweep mode 0: Software trigger...
Page 260: Repeat Sweep Mode 0
15. A/D Converter 15.1.4 Repeat Sweep Mode 0 In repeat sweep mode 0, analog voltages applied to the selected pins are repeatedly converted to a digital code. Table 15.6 shows the repeat sweep mode 0 specifications. Figure 15.12 shows the opera- tion example in repeat sweep mode 0.
Page 261 15. A/D Converter A/D Control Register 0 Symbol Address After Reset ADCON0 03D6 00000XXX Bit Symbol Bit Name Function Analog input pin select bit Invalid in repeat sweep mode 0 b4 b3 A/D operation mode 1 1: Repeat sweep mode 0 or select bit 0 repeat sweep mode 1 0: Software trigger...
Page 262: Repeat Sweep Mode 1
15. A/D Converter 15.1.5 Repeat Sweep Mode 1 In repeat sweep mode 1, analog voltage is applied to the all selected pins are converted to a digital code, with mainly used in the selected pins. Table 15.7 shows the repeat sweep mode 1 specifications. Figure 15.14 shows the operation example in repeat sweep mode 1.
Page 263 15. A/D Converter A/D Control Register 0 Symbol Address After Reset ADCON0 03D6 00000XXX Bit Symbol Bit Name Function Analog input pin select bit Invalid in repeat sweep mode 1 b4 b3 A/D operation mode 1 1: Repeat sweep mode 0 or select bit 0 repeat sweep mode 1 0: Software trigger...
Page 264: Simultaneous Sample Sweep Mode
15. A/D Converter 15.1.6 Simultaneous Sample Sweep Mode In simultaneous sample sweep mode, analog voltages applied to the selected pins are converted one-by- one to a digital code. The input voltages of AN0 and AN1 are sampled simultaneously using two circuits of sample and hold circuit.
Page 265 15. A/D Converter A/D Control Register 0 Symbol Address After Reset ADCON0 03D6 00000XXX Bit Symbol Bit Name Function Analog input pin select bit Invalid in repeat sweep mode 0 b4 b3 A/D operation mode 1 0: Single sweep mode or select bit 0 simultaneous sample sweep mode See Table 15.9...
Page 266 15. A/D Converter A/D Trigger Control Register Symbol Address After Reset ADTRGCON 03D2 Bit Symbol Bit Name Function A/D operation mode select 1: Simultaneous sample sweep mode or bit 2 delayed trigger mode 0, 1 A/D operation mode select 0: Other than delayed trigger mode 0, 1 bit 3 HPTRG0 trigger select bit...
Page 267: Delayed Trigger Mode 0
15. A/D Converter 15.1.7 Delayed Trigger Mode 0 In delayed trigger mode 0, analog voltages applied to the selected pins are converted one-by-one to a digital code. The delayed trigger mode 0 used in combination with A/D trigger mode of Timer B. The Timer B0 underflow starts a single sweep conversion.
Page 268 15. A/D Converter •Example when selecting AN to AN to A/D sweep pins (SCAN1 to SCAN0 = 01 •Example 1: When Timer B1 underflow is generated during AN pin conversion A/D pin input voltage sampling Timer B0 underflow A/D pin conversion Timer B1 underflow •Example 2: When Timer B1 underflow is generated after AN pin conversion...
Page 269 15. A/D Converter •Example when selecting AN to AN to A/D sweep pins (SCAN1 to SCAN0 = 01 •Example 1: When Timer B1 underflow is generated during AN pin conversion A/D pin input Timer B0 underflow voltage sampling Timer B1 underflow A/D pin conversion ADST flag Do not set to 1 by program...
Page 270 15. A/D Converter •Example 3: When Timer B0 underflow is generated during A/D pin conversion of any pins except AN Timer B0 underflow A/D pin input Timer B0 underflow (Abort othrt pins conversion ) voltage sampling Timer B1 underflow Timer B1 underflow A/D pin conversion ADST flag Do not set to 1 by program...
Page 271 15. A/D Converter A/D Control Register 0 Symbol Address After Reset ADCON0 03D6 00000XXX Bit Symbol Bit Name Function b2 b1 b0 Analog input pin 1 1 1: Set to 111b in delayed trigger select bit mode 0 b4 b3 A/D operation mode 0 0: One-shot mode or delayed trigger mode select bit 0...
Page 272 15. A/D Converter A/D Trigger Control Register Symbol Address After Reset ADTRGCON 03D2 Bit Symbol Bit Name Function A/D operation mode select Simultaneous sample sweep mode or bit 2 delayed trigger mode 0, 1 A/D operation mode select Delayed trigger mode 0, 1 bit 3 HPTRG0 trigger select bit...
Page 273: Delayed Trigger Mode 1
15. A/D Converter 15.1.8 Delayed Trigger Mode 1 In delayed trigger mode 1, analog voltages applied to the selected pins are converted one-by-one to a ___________ digital code. When the input of the AD pin (falling edge) changes state from “H” to “L”, a single sweep conversion is started.
Page 274 15. A/D Converter •Example when selecting AN to AN to A/D sweep pins (SCAN1 to SCAN0 = 01 •Example 1: When AD pin falling edge is generated during AN pin conversion A/D pin input voltage sampling A/D pin conversion pin input •Example 2: When AD pin falling edge is generated again after AN pin conversion...
Page 275 15. A/D Converter •Example when selecting AN to AN to A/D sweep pins (SCAN1 to SCAN0 = 01 •Example 1: When AD pin falling edge is generated during AN pin conversion A/D pin input pin input voltage sampling A/D pin conversion ADST flag Do not set to 1 by program ADERR0 flag...
Page 276 15. A/D Converter •Example 3: When AD input falling edge is generated more than two times after AN pin conversion A/D pin input voltage sampling A/D pin conversion pin input (valid after single sweep conversion) (invalid) ADST flag Do not set to 1 by program ADERR0 flag ADERR1 flag ADTCSF flag...
Page 277 15. A/D Converter A/D Control Register 0 Symbol Address After Reset ADCON0 03D6 00000XXX Bit Symbol Bit Name Function b2 b1 b0 Analog input pin 1 1 1: Set to 111b in delayed trigger select bit mode 1 b4 b3 A/D operation mode 0 0 : One-shot mode or delayed trigger mode select bit 0...
Page 278 15. A/D Converter A/D Trigger Control Register Symbol Address After Reset ADTRGCON 03D2 Bit Symbol Bit Name Function A/D operation mode select Simultaneous sample sweep mode or bit 2 delayed trigger mode 0, 1 A/D operation mode select Delayed trigger mode 0, 1 bit 3 HPTRG0 trigger select bit...
Page 279: Resolution Select Function
15. A/D Converter 15.2 Resolution Select Function The BITS bit in the ADCON1 register determines the resolution. When the BITS bit is set to 1 (10-bit precision), the A/D conversion result is stored into bits 0 to 9 in the ADi register (i=0 to 7). When the BITS bit is set to 0 (8-bit precision), the A/D conversion result is stored into bits 7 to 0 in the ADi register.
Page 280: Output Impedance Of Sensor Under A/D Conversion
15. A/D Converter 15.5 Output Impedance of Sensor under A/D Conversion To carry out A/D conversion properly, charging the internal capacitor C shown in Figure 15.29 has to be completed within a specified period of time. T (sampling time) as the specified time. Let output imped- ance of sensor equivalent circuit be R0, MCU’s internal resistance be R, precision (error) of the A/D converter be X, and the A/D converter’s resolution be Y (Y is 1024 in the 10-bit mode, and 256 in the 8- bit mode).
Page 281 16. MULTI-MASTER I C bus INTERFACE 16. Multi-master I C bus Interface The multi-master I C bus interface is a serial communication circuit based on Philips I C bus data transfer format, equipped with arbitration lost detection and synchronous functions. Figure 16.1 shows a block diagram of the multi-master I C bus interface and Table 16.1 lists the multi-master I C bus interface func-...
Page 282: Multi-Master I C Bus Interface
16. MULTI-MASTER I C bus INTERFACE Figure 16.1 Block diagram of multi-master I C bus interface page 256...
Page 283 16. MULTI-MASTER I C bus INTERFACE C0 Address Register Symbol Address After Reset S0D0 02E2 Bit Symbol Bit Name Function Reserved bit Set to 0 (b0) SAD0 SAD1 SAD2 Compare with received Slave address address data SAD3 SAD4 SAD5 SAD6 Figure 16.2 S0D0 Register page 257...
Page 284 16. MULTI-MASTER I C bus INTERFACE C0 Data Shift Register Symbol Address After Reset 02E0 Function Transmit/receive data are stored. In master transmit mode, the start condition/stop condition are triggered by writing data ( 1 ) to the register (refer to 16.9 START Condition Generation Method and 16.11 STOP Condition Generation Method).
Page 285 16. MULTI-MASTER I C bus INTERFACE C0 Control Register 0 Symbol Address After Reset S1D0 02E3 Bit Symbol Bit Name Function b2 b1 b0 Bit counter 0 0 0: 8 (Number of transmit/receive 0 0 1: 7 bits) 0 1 0: 6 0 1 1: 5 1 0 0: 4 1 0 1: 3...
Page 286 16. MULTI-MASTER I C bus INTERFACE C0 Status Register Symbol Address After Reset 02E8 0001000X Bit Symbol Bit Name Function Last receive bit 0: Last bit = 0 1: Last bit = 1 0: No general call detected ADR0 General call detecting flag 1: General call detected Slave address comparison flag 0: No address matched...
Page 287 16. MULTI-MASTER I C bus INTERFACE C0 Control Register 1 Symbol Address After Reset S3D0 02E6 00110000 Bit Symbol Bit Name Function The interrupt enable bit for 0: Disable the I C bus interface STOP condition detection interrupt of STOP condition detection 1: Enable the I C bus interface...
Page 288 16. MULTI-MASTER I C bus INTERFACE C0 Control Register 2 Symbol Address After Reset S4D0 02E7 Bit Symbol Bit Name Function 0: Disabled Time out detection 1: Enabled function enable bit 0: Not detected Time out detection flag 1: Detected Time out detection time TOSEL 0: Long time...
Page 289 16. MULTI-MASTER I C bus INTERFACE C0 Start/stop Condition Control Register Symbol Address After Reset S2D0 02E5 00011010 Bit Symbol Bit Name Function SSC0 SSC1 Setting for detection condition START/STOP condition of START/STOP condition. SSC2 setting bits See Table 16.2 SSC3 SSC4 nterrupt pin...
Page 290: I 2 C0 Data Shift Register (S00 Register)
16. MULTI-MASTER I C bus INTERFACE 16.1 I C0 Data Shift Register (S00 register) The S00 register is an 8-bit data shift register to store a received data and to write a transmit data. When a transmit data is written to the S00 register, the transmit data is synchronized with a SCL clock and the data is transferred from bit 7.
Page 291: I 2 C0 Clock Control Register (S20 Register)
16. MULTI-MASTER I C bus INTERFACE 16.3 I C0 Clock Control Register (S20 register) The S20 register is used to set theACK control, SCL mode and the SCL frequency. 16.3.1 Bits 0 to 4: SCL Frequency Control Bits (CCR0–CCR4) These bits control the SCL frequency. See Table 16.3 . 16.3.2 Bit 5: SCL Mode Specification Bit (FAST MODE) The FAST MODE bit selects SCL mode.
Page 292 16. MULTI-MASTER I C bus INTERFACE Table 16.3 Setting values of S20 register and SCL frequency Setting value of CCR4 to CCR0 SCL frequency (at V =4MHz, unit : kHz) CCR4 CCR3 CCR2 CCR1 CCR0 Standard clock mode High-speed clock mode Setting disabled Setting disabled Setting disabled...
Page 293: I 2 C0 Control Register 0 (S1D0)
16. MULTI-MASTER I C bus INTERFACE 16.4 I C0 Control Register 0 (S1D0) The S1D0 register controls data communication format. 16.4.1 Bits 0 to 2: Bit Counter (BC0–BC2) Bits BC2 to BC0 decide how many bits are in one byte data transferred next. After the selected num- bers of bits are transferred successfully, I C bus interface interrupt request is gnerated and bits BC2 to BC0 are reset to 000...
Page 294: Bit 7: I 2 C Bus Interface Pin Input Level Select Bit (Tiss)
16. MULTI-MASTER I C bus INTERFACE 16.4.5 Bit 7: I C bus Interface Pin Input Level Select Bit (TISS) The TISS bit selects the input level of the SCL and SDA pins for the multi-master I C bus interface. When the TISS bit is set to 1, the P2 and P2 become the SMBus input level.
Page 295: I 2 C0 Status Register (S10 Register)
16. MULTI-MASTER I C bus INTERFACE 16.5 I C0 Status Register (S10 register) The S10 register monitors the I C bus interface status. When using the S10 register to check the status, use the 6 low-order bits for read only. 16.5.1 Bit 0: Last Receive Bit (LRB) The LRB bit stores the last bit value of received data.
Page 296: Bit 4: I C Bus Interface Interrupt Request Bit (Pin)
16. MULTI-MASTER I C bus INTERFACE 16.5.5 Bit 4: I C bus Interface Interrupt Request Bit (PIN) The PIN bit generates an I C bus interface interrupt request signal. Every one byte data is ransferred, the PIN bit is changed from 1 to 0. At the same time, an I C bus interface interrupt request is generated.
Page 297: Bit 6: Communication Mode Select Bit (Transfer Direction Select Bit: Trx)
16. MULTI-MASTER I C bus INTERFACE 16.5.7 Bit 6: Communication Mode Select Bit (Transfer Direction Select Bit: TRX) This TRX bit decides a transfer direction for data communication. When the TRX bit is set to 0, receive mode is entered and data is received from a transmit device. When the TRX bit is set to 1, transmit mode is entered, and address data and control data are output to the SDA synchronized with a clock gener- ated in the SCL...
Page 298: I 2 C0 Control Register 1 (S3D0 Register)
16. MULTI-MASTER I C bus INTERFACE 16.6 I C0 Control Register 1 (S3D0 register) The S3D0 register controls the I C bus interface circuit. 16.6.1 Bit 0 : Interrupt Enable Bit by STOP Condition (SIM ) The SIM bit enables the I C bus interface interrupt request by detecting a STOP condition.
Page 299: Bits 2,3 : Port Function Select Bits Ped, Pec
16. MULTI-MASTER I C bus INTERFACE In receive mode, ACK bit = 1 WIT bit = 0 7 clock 8 clock 1 clock clock 7 bit 8 bit ACK bit 1 bit ACKBIT bit PIN flag Internal WAIT flag C bus interface interrupt request signal The writing signal of the S00 register...
Page 300: Bits 4,5 : Sda/Scl Logic Output Value Monitor Bits Sdam/Sclm
16. MULTI-MASTER I C bus INTERFACE 16.6.4 Bits 4,5 : SDA/SCL Logic Output Value Monitor Bits SDAM/SCLM Bits SDAM/SCLM can monitor the logic value of the SDA and SCL output signals from the I C bus interface circuit. The SDAM bit monitors the SDA output logic value. The SCLM bit monitors the SCL output logic value.
Page 301: I 2 C0 Control Register 2 (S4D0 Register)
16. MULTI-MASTER I C bus INTERFACE 16.7 I C0 Control Register 2 (S4D0 Register) The S4D0 register controls the error communication detection. If the SCL clock is stopped counting dring data transfer, each device is stopped, staying online. To avoid the situation, the I C bus interface circuit has a function to detect the time-out when the SCL clock is stopped in high-level ("H") state for a specific period, and to generate an I...
Page 302: Bit0: Time-Out Detection Function Enable Bit (Toe)
16. MULTI-MASTER I C bus INTERFACE 16.7.1 Bit0: Time-Out Detection Function Enable Bit (TOE) The TOE bit enables the time-out detection function. When the TOE bit is set to 1, time-out is detected and the I C bus interface interrupt request is generated when the following conditions are met. 1) the BB flag in the S10 register is set to 1 (bus busy) 2) the SCL clock stops for time-out detection period while high-level ("H") signal is maintained (see Table 16.7)
Page 303: I 2 C0 Start/Stop Condition Control Register (S2D0 Register)
16. MULTI-MASTER I C bus INTERFACE 16.8 I C0 START/STOP Condition Control Register (S2D0 Register) The S2D0 register controls the START/STOP condition detections. 16.8.1 Bit0-Bit4: START/STOP Condition Setting Bits (SSC0-SSC4) The SCL release time and the set-up and hold times are mesured on the base of the I C bus system clock ).
Page 304: Start Condition Generation Method
16. MULTI-MASTER I C bus INTERFACE 16.9 START Condition Generation Method Set the MST bit, TRX bit and BB flags in the S10 register to 1 and set the PIN bit and 4 low-order bits in the S10 register to 0 simultaneously, to enter START condition standby mode, when the ES0 bit in the S1D0 register is set to 1 (I C bus interface enabled) and the BB flag is set to 0 (bus free).
Page 305: Start Condition Duplicate Protect Function
16. MULTI-MASTER I C bus INTERFACE 16.10 START Condition Duplicate Protect Function A START condition is generated when verifying that the BB flag in the S10 register does not use buses. However, if the BB flag is set to 1 (bus busy) by the START condition which other master device generates immediately after the BB flag is verified, the START condition is suspended by the START condition dupli- cate protect function.
Page 306 16. MULTI-MASTER I C bus INTERFACE S 0 0 r e g i s t e r S e t u p Hold t i m e time Figure 16.16 Start condition generation timing diagram S00 register H o l d Setup t i m e time...
Page 307: Start/Stop Condition Detect Operation
16. MULTI-MASTER I C bus INTERFACE 16.12 START/STOP Condition Detect Operation Figure 16.18, Figure 16.19 and Table 16.10 show START/STOP condition detect operations. Bits SSC4 to SSC0 in the S2D0 register set the START/STOP conditions. The START/STOP condition can be de- tected only when the input signal of the SCL and SDA met the following conditions: the SCL release...
Page 308: Address Data Communication
16. MULTI-MASTER I C bus INTERFACE 16.13 Address Data Communication This section describes data transmit control when a master transferes data or a slave receives data in 7-bit address format. Figure 16.20 (1) shows a master transmit format. (1) A master transmit device transmits data to a receive device D a t a D a t a S l a v e a d d r e s s...
Page 309: Example Of Slave Receive
16. MULTI-MASTER I C bus INTERFACE 16.13.2 Example of Slave Receive For example, a slave receives data as shown below when following conditions are met: high-speed clock mode, SCL frequency of 400 kHz, ACK clock added and addressing format. 1) Set a slave address in the 7 high-order bits in the S0D0 register 2) Set A5 to the S20 register, 000 to bits ICK4 to ICK2 in the S4D0 register, and 00...
Page 310: Precautions
16. MULTI-MASTER I C bus INTERFACE 16.14 Precautions (1) Access to the registers of I C bus interface circuit The following is precautions when read or write the control registers of I C bus interface circuit •S00 register Do not rewrite the S00 register during data transfer. If the bits in the S00 register are rewritten, the bit counter for transfer is reset and data may not be transferred successfully.
Page 311 16. MULTI-MASTER I C bus INTERFACE BB flag Bit reset signal Related bits 1.5 V cycle Figure 16.21 The bit reset timing (The STOP condition detection) BB flag Bit reset signal Related bits BC2 - BC0 TRX (in slave mode) Figure 16.22 The bit reset timing (The START condition detection) PIN bit BC0 - BC2...
Page 312 16. MULTI-MASTER I C bus INTERFACE (2) Generation of RESTART condition In order to generate a RESTART condition after 1-byte data transfer, write E0 to the S10 register, enter START condition standby mode and leave the SDA open. Generate a START condition trigger by setting the S00 register after inserting a sufficient software wait until the SDA outputs a high-level ("H") signal.
Page 313: Can Module
17. CAN Module 17. CAN Module The CAN (Controller Area Network) module for the M16C/29 Group of MCUs is a communication controller implementing the CAN 2.0B protocol. The M16C/29 Group contains one CAN module which can transmit and receive messages in both standard (11-bit) ID and extended (29-bit) ID formats. Figure 17.1 shows a block diagram of the CAN module.
Page 314: Can Module-Related Registers
17. CAN Module 17.1 CAN Module-Related Registers The CAN0 module has the following registers. (1) CAN Message Box A CAN module is equipped with 16 slots (16 bytes or 8 words each). Slots 14 and 15 can be used as Basic CAN.
Page 315: Can0 Message Box
17. CAN Module 17.1.1 CAN0 Message Box Table 17.1 shows the memory mapping of the CAN0 message box. It is possible to access to the message box in byte or word. Mapping of the message contents differs from byte access to word access. Byte access or word access can be selected by the MsgOrder bit of the C0CTLR register.
Page 316 17. CAN Module Figures 17.2 and 17.3 show the bit mapping in each slot in byte access and word access. The content of each slot remains unchanged unless transmission or reception of a new message is performed. bit 7 bit 0 Data Byte 0 Data Byte 1 Data Byte 7...
Page 317: Acceptance Mask Registers
17. CAN Module 17.1.2 Acceptance Mask Registers Figures 17.4 and 17.5 show the C0GMR register, the C0LMAR register, and the C0LMBR register, in which bit mapping in byte access and word access are shown. Addresses CAN0 bit 7 bit 0 0160 0161 C0GMR register...
Page 318: Can Sfr Registers
17. CAN Module 17.1.3 CAN SFR Registers 17.1.3.1 C0MCTLj Register (j = 0 to 15) Figure 17.6 shows the C0MCTLj register. CAN0 message control register j ( j = 0 to 15) Address Symbol After Reset C0MCTL0 to C0MCTL15 0200 to 020F Bit Symbol Bit Name...
Page 319 17. CAN Module 17.1.3.2 C0CTLR Register Figure 17.7 shows the C0CTLR register. CAN0 Control Register Symbol Address After reset C0CTLR 0210 X0000001 Bit Symbol Bit Name Function CAN module 0: Operation mode Reset reset bit (Note 1) 1: Reset/initialization mode Loop back mode 0: Loop back mode disabled LoopBack...
Page 320 17. CAN Module 17.1.3.3 C0STR Register Figure 17.8 shows the C0STR register. CAN0 Status Register Symbol Address After Reset C0STR 0212 Bit Symbol Bit Name Function b3 b2 b1 b0 0 0 0 0: Slot 0 0 0 0 1: Slot 1 Active slot bits MBOX 0 0 1 0: Slot 2...
Page 321 17. CAN Module 17.1.3.4 C0SSTR Register Figure 17.9 shows the C0SSTR register. CAN0 Slot Status Register (b15) (b8) b0 b7 Symbol Address After Reset C0SSTR 0215 , 0214 0000 Function Setting Values 0: Reception slot The message has been read. Transmission slot Slot status bits Transmission is not completed.
Page 322 17. CAN Module 17.1.3.5 C0ICR Register Figure 17.10 shows the C0ICR register. CAN0 Interrupt Control Register (b15) (b8) b0 b7 Symbol Address After Reset C0ICR 0217 , 0216 0000 Function Setting Values 0: Interrupt disabled Interrupt enable bits: 1: Interrupt enabled Each bit corresponds with a slot with the same number.
Page 323 17. CAN Module 17.1.3.7 C0CONR Register Figure 17.12 shows the C0CONR register. CAN0 Configuration Register Symbol Address After reset Undefined C0CONR 021A Bit symbol Bit name Function b3 b2 b1 b0 0 0 0 0: Divide-by-1 of f 0 0 0 1: Divide-by-2 of f Prescaler division 0 0 1 0: Divide-by-3 of f ratio select bits...
Page 324 17. CAN Module 17.1.3.8 C0RECR Register Figure 17.13 shows the C0RECR register. CAN0 Receive Error Count Register Address Symbol After Reset C0RECR 021C Function Counter Value Reception error counting function 16 (1) The value is incremented or decremented to FF according to the CAN module's error status NOTE: 1.
Page 325 17. CAN Module 17.1.3.10 C0TSR Register Figure 17.15 shows the C0TSR register. CAN0 Time Stamp Register (b15) (b8) b0 b7 Symbol Address After Reset C0TSR 021F , 021E 0000 Function Counter Value Time stamp function 0000 to FFFF NOTE: 1. Use a 16-bit data for reading. Figure 17.15 C0TSR Register 17.1.3.11 C0AFS Register Figure 17.16 shows the C0AFS register.
Page 326: Operating Modes
17. CAN Module 17.2 Operating Modes The CAN module has the following four operating modes. • CAN Reset/Initialization Mode • CAN Operating Mode • CAN Sleep Mode • CAN Interface Sleep Mode Figure 17.17 shows transition between operating modes. MCU Reset Reset = 0 CAN reset/initialization CAN operating mode...
Page 327: Can Operating Mode
17. CAN Module 17.2.2 CAN Operating Mode The CAN operating mode is activated by setting the Reset bit in the C0CTLR register to 0. If the Reset bit is set to 0, check that the State_Reset bit in the C0STR register is set to 0. If 11 consecutive recessive bits are detected after entering the CAN operating mode, the module initiates the following functions: •...
Page 328: Can Interface Sleep Mode
17. CAN Module 17.2.4 CAN Interface Sleep Mode The CAN interface sleep mode is activated by setting the CCLK3 bit in the CCLKR register to 1. It should never be activated but only via the CAN sleep mode. Entering the CAN interface sleep mode instantly stops the clock supply to the CPU Interface in the mod- ule and thereby reduces power dissipation.
Page 329: Configuration Of The Can Module System Clock
17. CAN Module 17.3 Configuration of the CAN Module System Clock The M16C/29 Group has a CAN module system clock select circuit. Configuration of the CAN module system clock can be done through manipulating the CCLKR register and the BRP bit in the C0CONR register. For the CCLKR register, refer to 7.
Page 330: Bit-Rate
17. CAN Module 17.3.2 Bit-rate Bit-rate depends on f , the division value of the CAN module system clock, the division value of the baud rate prescaler, and the number of Tq of one bit. Table 17.2 shows the examples of bit-rate. Table 17.2 Examples of Bit-rate Bit-rate 20MHz...
Page 331: Acceptance Filtering Function And Masking Function
17. CAN Module 17.4 Acceptance Filtering Function and Masking Function These functions serve the users to select and receive a facultative message. The C0GMR register, the C0LMAR register, and the C0LMBR register can perform masking to the standard ID and the extended ID of 29 bits.
Page 332: Acceptance Filter Support Unit (Asu)
17. CAN Module 17.5 Acceptance Filter Support Unit (ASU) The acceptance filter support unit has a function to judge valid/invalid of a received ID through table search. The IDs to receive are registered in the data table; a received ID is stored in the C0AFS register, and table search is performed with a decoded received ID.
Page 333: Basiccan Mode
17. CAN Module 17.6 BasicCAN Mode When the BasicCAN bit in the C0CTLR register is set to 1 (Basic CAN mode enabled), slots 14 and 15 correspond to Basic CAN mode. During normal operations, individual slots can select either data frame or remote frame by CPU setting.
Page 334: Return From Bus Off Function
17. CAN Module 17.7 Return from Bus off Function When the protocol controller enters bus off state, it is possible to make it forced return from bus off state by setting the RetBusOff bit in the C0CTLR register to 1 (Force return from bus off). At this time, the error state changes from bus off state to error active state.
Page 335: Reception And Transmission
17. CAN Module 17.10 Reception and Transmission Configuration of CAN Reception and Transmission Mode Table 17.3 shows configuration of CAN reception and transmission mode. Table 17.3 Configuration of CAN Reception and Transmission Mode TrmReq RecReq Remote RspLock Communication mode of the slot Communication environment configuration mode: configure the communication mode of the slot.
Page 336: Reception
17. CAN Module 17.10.1 Reception Figure 17.25 shows the behavior of the module when receiving two consecutive CAN messages, that fit into the slot of the shown C0MCTLj register (j = 0 to 15) and leads to losing/overwriting of the first message.
Page 337: Transmission
17. CAN Module 17.10.2 Transmission Figure 17.26 shows the timing of the transmit sequence. TrmReq bit TrmActive bit SentData bit CAN0 Successful Transmission Interrupt TrmState bit TrmSucc bit MBOX bit Transmission slot No. j = 0 to 15 Figure 17.26 Timing of Transmit Sequence (1) If the TrmReq bit in the C0MCTLj register (j = 0 to 15) is set to 1 (Transmission slot) in the bus idle state, the TrmActive bit in the C0MCTLj register and the TrmState bit in the C0STR register are set to 1 (Transmitting/Transmitter), and CAN module starts the transmission.
Page 338: Can Interrupts
17. CAN Module 17.11 CAN Interrupts The CAN module provides the following CAN interrupts. • CAN0 Successful Reception Interrupt • CAN0 Successful Transmission Interrupt • CAN0 Error Interrupt Error Passive State Error BusOff State Bus Error (this feature can be disabled separately) •...
Page 339: Crc Calculation Circuit
18. CRC Calculation Circuit 18. CRC Calculation Circuit The Cyclic Redundancy Check (CRC) calculation detects errors in blocks of data. The MCU uses a gen- erator polynomial of CRC_CCITT (X + 1) or CRC-16 (X + 1) to generate CRC code.
Page 340 18. CRC Calculation Circuit CRC Data Register (b15) (b8) Symbol Address After Reset b0 b7 CRCD 03BD to 03BC Undefined Function Setting Range CRC calculation result output 0000 to FFFF CRC Input Register Symbol Address After Reset CRCIN 03BE Undefined Setting Range Function Data input...
Page 341 18. CRC Calculation Circuit (1) Setting 0000 (initial value) CRD data register CRCD [03BD , 03BC (2) Setting 01 CRC input register CRCIN [03BE 2 cycles After CRC calculation is complete CRD data register CRCD 1189 [03BD , 03BC Stores CRC code The code resulting from sending 01 in LSB first mode is (10000 0000).This the CRC code in the generating polynomial, + 1), becomes the remainder resulting from dividing (1000 0000)X...
Page 342: Programmable I/O Ports
19. Programmable I/O Ports 19. Programmable I/O Ports Note Ports P0 to P0 , P1 to P1 , P3 to P3 and P9 to P9 are not available in 64-pin package. The programmable input/output ports (hereafter referred to simply as “I/O ports”) consist of 71 lines P0, P1, P2, P3, P6, P7, P8, P9, P10 (except P9 ) for the 80-pin package, or 55 lines P0 to P0...
Page 343: Pin Assignment Control Register (Pacr)
19. Programmable I/O Ports 19.5 Pin Assignment Control Register (PACR) Figure 19.10 shows the PACR register. After reset, set bits PACR2 to PACR0 in the PACR register before a signal is input or output to each pin. When bits PACR2 to PACR0 are not set, some pins do not function as I/O ports.
Page 344 19. Programmable I/O Ports Pull-up selection Direction register to P0 (inside dotted-line included) to P10 Data bus Port latch to P3 (inside dotted-line not included) Analog input Pull-up selection Direction register to P1 (inside dotted-line included) Port P1 control register Data bus Port latch (inside dotted-line not included)
Page 345 19. Programmable I/O Ports Pull-up selection Direction register , P2 , P7 to P7 "1" Output Port latch Data bus Switching between CMOS and Input to respective peripheral functions Pull-up selection to P8 Direction register Port latch Data bus Input to respective peripheral functions Pull-up selection Direction register , P6...
Page 346 19. Programmable I/O Ports Pull-up selection Direction register , P6 “1” Output Port latch Data bus Switching between CMOS and Nch Pull-up selection NMI Enable Direction register Port latch Data bus Digital Debounce NMI Interrupt Input NMI Enable Pull-up selection , P9 , P9 to P10...
Page 347 19. Programmable I/O Ports Pull-up selection , P9 (inside dotted-line included) Direction register , P9 (inside dotted-line not included) Output Port latch Data bus Analog input Input to respective peripheral functions Pull-up selection Direction register Data bus Port latch Pull-up selection Direction register Data bus Port latch...
Page 348 19. Programmable I/O Ports signal input RESET RESET signal input NOTE: symbolizes a parasitic diode. Make sure the input voltage on each port will not exceed Vcc. Figure 19.5 I/O Pins page 322...
Page 349 19. Programmable I/O Ports Port Pi Direction Register (i=0 to 3, 6 to 8, and 10) Symbol Address After Reset PD0 to PD3 03E2 , 03E3 , 03E6 , 03E7 PD6 to PD8 03EE , 03EF , 03F2 PD10 03F6 Bit Symbol Bit Name Function...
Page 350 19. Programmable I/O Ports Port Pi Register (i=0 to 3, 6 to 8 and 10) Symbol Address After Reset P0 to P3 03E0 , 03E1 , 03E4 , 03E5 Undefined Undefined P6 to P8 03EC , 03ED , 03F0 Undefined 03F4 Bit Symbol Bit Name...
Page 351 19. Programmable I/O Ports Pull-up Control Register 0 (1) Symbol Address After Reset PUR0 03FC Bit Symbol Bit Name Function PU00 to P0 pull-up 0: Not pulled up PU01 to P0 pull-up 1: Pulled up PU02 to P1 pull-up PU03 to P1 pull-up PU04...
Page 352 19. Programmable I/O Ports Port Control Register Symbpl Address After Reset 03FF Bit symbol Bit Name Function PCR0 Port P1 control bit Operation performed when the P1 register is read 0: When the port is set for input, the input levels of P1 to P1 pins are read.
Page 353 19. Programmable I/O Ports NMI Digital Debounce Register (1,2) Symbol Address After Reset NDDR 033E Function Setting Range If the set value =n, - n = 0 to FE ; a signal with pulse width, greater than to FF (n+1)/f8, is input into NMI / SD - n = FF ;...
Page 354 19. Programmable I/O Ports Example of INT5 Digital Debounce Function (if P17DDR = 03 • Digital Debounce Filter Clock Port In Signal Out To INT5 Data Bus Reload Value Count Value Data Bus (write) (read) Reload Value Port In Signal Out Count Value Reload Value (continued)
Page 355 19. Programmable I/O Ports Table 19.1 Unassigned Pin Handling in Single-chip Mode t s i l l u t s i l l u NOTES: 1. If the port enters output mode and is left open, it is in input mode before output mode is entered by program after reset.
Page 356: Flash Memory Version
20. Flash Memory Version 20. Flash Memory Version 20.1 Flash Memory Performance In the flash memory version, rewrite operation to the flash memory can be performed in four modes: CPU rewrite mode, standard serial I/O mode, parallel I/O mode, and CAN I/O mode. Table 20.1 lists specifications of the flash memory version.
Page 357: Boot Mode
20. Flash Memory Version Table 20.2. Flash Memory Rewrite Modes Overview Flash memory CPU rewrite mode Standard serial I/O Parallel I/O mode CAN I/O mode rewrite mode mode Function The user ROM area is The user ROM area The user ROM areas The user ROM areas is rewritten when the CPU is rewritten using a are rewritten using a...
Page 358: Memory Map
20. Flash Memory Version 20.2 Memory Map The flash memory contains the user ROM area and the boot ROM area (reserved area). Figures 20.1 to 20.3 show a block diagram of the flash memory. The user ROM area has space to store the MCU operation program in single-chip mode and two 2-Kbyte spaces: the block A and B.
Page 359 20. Flash Memory Version (Data space) 00F000 Block B :2K bytes 00F7FF 00F800 Block A :2K bytes 00FFFF (Program space) 0E8000 Block 4 : 32K bytes 0EFFFF 0F0000 Block 3 : 32K bytes NOTES: 1. To specify a block, use the maximum even address in the block. 2.
Page 360 20. Flash Memory Version (Data space) 00F000 Block B :2K bytes 00F7FF 00F800 Block A :2K bytes 00FFFF (Program space) 0E0000 Block 5 : 32K bytes 0E7FFF 0E8000 Block 4 : 32K bytes 0EFFFF 0F0000 Block 3 : 32K bytes NOTES: 1.
Page 361: Functions To Prevent Flash Memory From Rewriting
20. Flash Memory Version 20.3 Functions To Prevent Flash Memory from Rewriting The flash memory has a built-in ROM code protect function for parallel I/O mode and a built-in ID code check function for standard input/output mode to prevent the flash memory from reading or rewriting. 20.3.1 ROM Code Protect Function The ROM code protect function disables reading or changing the contents of the on-chip flash memory in parallel I/O mode.
Page 362 20. Flash Memory Version ROM Code Protect Control Address Symbol Address Factory Setting ROMCP 0FFFFF Bit Name Function Bit Symbol Set to 1 Reserved Bit (b5-b0) ROM Code Protect Level b7 b6 ROMCP1 1 Set Bit (1, 2, 3, 4) Enables protect 11: Disables protect NOTES:...
Page 363: Cpu Rewrite Mode
20. Flash Memory Version 20.4 CPU Rewrite Mode In CPU rewrite mode, the user ROM area can be rewritten when the CPU executes software commands. The user ROM area can be rewritten with MCU mounted on a board without using the ROM writer. The program and block erase commands are executed only in the user ROM area.
Page 364: Ew Mode 0
20. Flash Memory Version 20.4.1 EW Mode 0 The MCU enters CPU rewrite mode by setting the FMR01 bit in the FMR0 register to 1 (CPU rewrite mode enabled) and is ready to accept software commands. EW mode 0 is selected by setting the FMR11 bit in the FMR1 register to 0.
Page 365: Register Description
20. Flash Memory Version 20.5 Register Description Figure 20.6 shows the flash memory control register 0 and flash memory control register 1. Figure 20.7 shows the flash memory control register 4. 20.5.1 Flash Memory Control Register 0 (FMR0) •FMR 00 Bit The FMR00 bit indicates the operating state of the flash memory.
Page 366: Flash Memory Control Register 1 (Fmr1)
20. Flash Memory Version 20.5.2 Flash Memory Control Register 1 (FMR1) •FMR11 Bit EW mode 1 is entered by setting the FMR11 bit to 1 (EW mode 1). The FMR11 bit is valid only when the FMR01 bit is set to 1. •FMR16 Bit The combined setting of bits FMR02 and FMR16 enables program and erase in the user ROM area.
Page 367 20. Flash Memory Version Flash Memory Control Register 0 Symbol Address After Reset b7 b6 b5 b4 b3 b2 b1 b0 FMR0 01B7 00000001 Bit Name Function Bit Symbol 0: Busy (during writing or erasing) RY/BY status flag FMR00 1: Ready 0: Disables CPU rewrite mode CPU rewrite mode select bit FMR01...
Page 368 20. Flash Memory Version Flash Memory Control Register 4 Symbol Address After Reset b7 b6 b5 b4 b3 b2 b1 b0 01B3 FMR4 01000000 Bit Name Function Bit Symbol Erase suspend function 0: Disabled FMR40 enable bit 1: Enabled Erase suspend 0: Erase restart FMR41 request bit...
Page 369 20. Flash Memory Version EW mode 0 operation procedure Rewrite control program Set the FMR01 bit to 1 after writing 0 (CPU Single-chip mode rewrite mode enabled) Set CM0, CM1, and PM1 registers Execute software commands Transfer a rewrite control program to internal RAM Execute the Read Array command area Write 0 to the FMR01 bit...
Page 370 20. Flash Memory Version Low power consumption mode program Transfer a low power internal consumption mode Set the FMR01 bit to 1 after setting 0 (CPU program to RAM area rewrite mode enabled) Set the FMSTP bit to 1 (flash memory stopped. Jump to the low power consumption mode Low power consumption state) program transferred to internal RAM area.
Page 371: Precautions In Cpu Rewrite Mode
20. Flash Memory Version 20.6 Precautions in CPU Rewrite Mode Described below are the precautions to be observed when rewriting the flash memory in CPU rewrite mode. 20.6.1 Operation Speed When the CPU clock source is the main clock, set the CPU clock frequency at 10 MHz or less with the CM06 bit in the CM0 register and bits CM17 and CM16 in the CM1 register, before entering CPU rewrite mode (EW mode 0 or EW mode 1).
Page 372: Dma Transfer
20. Flash Memory Version 20.6.6 DMA Transfer In EW mode 1, do not generate a DMA transfer while the FMR00 bit in the FMR0 register is set to 0. (during the auto-programming or auto-erasing). 20.6.7 Writing Command and Data Write the command codes and data to even addresses in the user ROM area. 20.6.8 Wait Mode When entering wait mode, set the FMR01 bit to 0 (CPU rewrite mode disabled) before executing the WAIT instruction.
Page 373: Software Commands
20. Flash Memory Version 20.7 Software Commands Read or write 16-bit commands and data from or to even addresses in the user ROM area. When writing a command code, 8 high-order bits (D –D ) are ignored. Table 20.5 Software Commands First bus cycle Second bus cycle Command...
Page 374: Program Command (40 )
20. Flash Memory Version 20.7.4 Program Command (40 The program command writes 2-byte data to the flash memory. Auto program operation (data program and verify) start by writing xx40 in the first bus cycle and data to the write address specified in the second bus cycle. The address value specified in the first bus cycle must be the same even address as the write address secified in the second bus cycle.
Page 375: Block Erase
20. Flash Memory Version 20.7.5 Block Erase Auto erase operation (erase and verify) start in the specified block by writing xx20 in the first bus cycle and xxD0 to the highest-order even addresse of a block in the second bus cycle. The FMR00 bit in the FMR0 register indicates whether the auto-erase operation has been completed.
Page 376 20. Flash Memory Version (EW mode 0) Start Interrupt service routine FMR40=1 FMR41=1 Write the command code 16 (1) xx20 FMR46=1? Write xxD0 to the highest-order block address Access Flash Memory FMR00=1? FMR41=0 Return (2,4) Full status check (Interrupt service routine end) Block erase completed (EW mode 1) Start...
Page 377: Status Register
20. Flash Memory Version 20.8 Status Register The status register indicates the operating status of the flash memory and whether or not erase or pro- gram operation is successfully completed. Bits FMR00, FMR06, and FMR07 in the FMR0 register indi- cate the status of the status register.
Page 378: Full Status Check
20. Flash Memory Version 20.8.4 Full Status Check If an error occurs, bits FMR06 to FMR07 in the FMR0 register are set to 1, indicating a specific error. Therefore, execution results can be comfirmed by verifying these status bits (full status check). Table 20.7 lists errors and FMR0 register state.
Page 379 20. Flash Memory Version Full status check FMR06 =1 (1) Execute the clear status register command and set Command the status flag to 0 whether the command is FMR07=1? sequence error entered. (2) Execute the command again after checking that the correct command is entered or the program command or the block erase command is not executed on the protected blocks.
Page 380: Standard Serial I/O Mode
20. Flash Memory Version 20.9 Standard Serial I/O Mode In standard serial I/O mode, the serial programmer supporting the M16C/29 group can be used to rewrite the flash memory user ROM area, while the MCU is mounted on a board. For more information about the serial programmer, contact your serial programmer manufacturer.
Page 381 20. Flash Memory Version Table 20.8 Pin Descriptions (Flash Memory Standard Serial I/O Mode) Name Descriptio Apply the voltage guaranteed for Program and Erase to Vcc pin and 0 Power input V to Vss pin. Connect to Vcc pin. Reset input RESET Reset input pin.
Page 382 20. Flash Memory Version BUSY SCLK M16C/29 Group (64-pin package) (Flash memory version) (PLQP0064KB-A (64P6Q-A)) Mode setup method Value Signal CNVss Vss to Vcc Reset Connect oscillator circuit NOTE: 1. Set the following, either or both, in serial I/O Mode, while the RESET pin is applied a low-level ("L") signal. -Connect the CE pin to Vcc.
Page 383 20. Flash Memory Version M16C/29 Group (80-pin package) BUSY (Flash memory version) SCLK (PLQP0080KB-A(80P6Q-A)) Mode setup method Signal Value CNVss Reset Vss to Vcc Connect oscillator circuit NOTE: 1. Set the following, either or both, in serial I/O Mode, while the RESET pin is applied a low-level ("L") signal. -Connect the CE pin to Vcc.
Page 384: Example Of Circuit Application In Standard Serial I/O Mode
20. Flash Memory Version 20.9.2 Example of Circuit Application in Standard Serial I/O Mode Figure 20.17 shows an example of a circuit application in standard serial I/O mode 1 and Figure 20.18 shows an example of a circuit application in standard serial I/O mode 2. Refer to the user's manual of your serial programmer to handle pins controlled by the serial programmer.
Page 385 20. Flash Memory Version SCLK (CE) TxD output BUSY Monitor output RxD input CNVss (RP) (1) In this example, a selector controls the input voltage applied to CNVss to switch between single-chip mode and standard serial I/O mode. NOTE: 1. Set the following, either or both. - Connect the CE pin to Vcc - Connect the RP pin to Vss and the P1 pin to Vcc...
Page 386: Parallel I/O Mode
20. Flash Memory Version 20.10 Parallel I/O Mode In parallel input/output mode, the user ROM can be rewritten by a parallel programmer supporting the M16C/29 group. Contact your parallel programmer manufacturer for more information on the parallel pro- grammer. Refer to the user’s manual included with your parallel programmer for instructions. 20.10.1 ROM Code Protect Function The ROM code protect function prevents the flash memory from being read or rewritten.
Page 387: Can I/O Mode
20. Flash Memory Version 20.11 CAN I/O Mode Note The CAN I/O mode is not available in M16C/29 T-ver./V-ver. In CAN I/O mode, the user ROM area can be rewritten while the MCU is mounted on-board by using a CAN programmer which is applicable for the M16C/29 group.
Page 388 20. Flash Memory Version Table 20.9 Pin Functions for CAN I/O Mode Name Description Apply the voltage guaranteed for Program and Erase to Vcc pin and 0 Power input V to Vss pin. Connect to Vcc pin. Reset input RESET Reset input pin.
Page 389 20. Flash Memory Version SCLK M16C/29 Group (64-pin package) (Flash memory version) (PLQ0064KB-A (64P6Q-A)) Mode setup method Signal Value CNVss Reset Vss to Vcc Connect oscillator circuit SCLK NOTE: 1. Set following either or both in serial I/O mode while the RESET pin is held “L”. •Connect the CE pin to V •Connect the RP pin to V and the P1...
Page 390 20. Flash Memory Version M16C/29 Group (80-pin package) (Flash memory version) (PLQP0080KB-A (80P6Q-A)) SCLK Mode setup method Signal Value CNVss Reset Vss to Vcc Connect oscillator circuit SCLK NOTE: 1. Set following either or both in serial I/O mode while the RESET pin is held “L”. •Connect the CE pin to V •Connect the RP pin to V and the P1...
Page 391: Example Of Circuit Application In Can I/O Mode
20. Flash Memory Version 20.11.2 Example of Circuit Application in CAN I/O Mode Figure 20.21 shows example of circuit application in CAN I/O mode. Refer to the user’s manual for CAN programmer to handle pins controlled by a CAN programmer. (Note 1) SCLK (CE)
Page 392: Electrical Characteristics
21. Electrical Characteristics (Normal-version) 21. Electrical Characteristics 21.1 Normal version Table 21.1 Absolute Maximum Ratings 4 - < < ° 5 ° ° ° ° NOTE: 1. Refer to Table 1.6. page 366...
Page 393 21. Electrical Characteristics (Normal-version) Table 21.2 Recommended Operating Conditions (Note 1) " ( ) " L " ) " " ( ) " " ( ) " L " ) " L " ) " l l i l l i l l i l l i l l i...
Page 394 21. Electrical Characteristics (Normal-version) Table 21.3 A/D Conversion Characteristics (Note 1) s t i ± n i l y t i ± ± ± ± ± l a i n i l y t i ± ± ± t s i kΩ...
Page 395 21. Electrical Characteristics (Normal-version) Table 21.4 Flash Memory Version Electrical Characteristics for 100/1000 E/W cycle products [Program Space and Data Space in U3 and U5: Program Space in U7 and U9] µs ° ) ° ) µs z i l Table 21.5 Flash Memory Version Electrical Characteristics 10000 E/W cycle products (Option) [Data Space in U7 and U9...
Page 396 21. Electrical Characteristics (Normal-version) Table 21.6 Low Voltage Detection Circuit Electrical Characteristics (Note 1, Note 3) > < l a i Table 21.7 Power Supply Circuit Timing Characteristics z i l µs z i l l l i µs µs µs d(P-R) Wait time to stabilize internal...
Page 397 21. Electrical Characteristics (Normal-version) = 5V Table 21.8 Electrical Characteristics (Note 1) " ( ) " µA " ( ) " " ( ) " e i l " ( ) " e i l L " ) " µA L "...
Page 398 21. Electrical Characteristics (Normal-version) = 5V Table 21.9 Electrical Characteristics (2) (Note 1) l l i l l i µA µA l l i µA µA µA l l i ) 2 ( µA t i a a l l o i t y t i µA...
Page 399 21. Electrical Characteristics (Normal-version) = 5V Timing Requirements = 5V, V = 0V, at Topr = – 20 to 85 C / – 40 to 85 C unless otherwise specified) Table 21.10 External Clock Input (X input) " ( ) " L "...
Page 400 21. Electrical Characteristics (Normal-version) = 5V Timing Requirements = 5V, V = 0V, at Topr = – 20 to 85 C / – 40 to 85 C unless otherwise specified) Table 21.11 Timer A Input (Counter Input in Event Counter Mode) Standard Symbol Parameter...
Page 401 21. Electrical Characteristics (Normal-version) = 5V Timing Requirements = 5V, V = 0V, at Topr = – 20 to 85 C / – 40 to 85 C unless otherwise specified) Table 21.17 Timer B Input (Counter Input in Event Counter Mode) Standard Symbol Parameter...
Page 402 21. Electrical Characteristics (Normal-version) = 5V Timing Requirements = 5V, V = 0V, at Topr = – 20 to 85 C / – 40 to 85 C unless otherwise specified) Table 21.23 Multi-master I C bus Line Standard clock mode High-speed clock mode Symbol Parameter...
Page 403 21. Electrical Characteristics (Normal-version) = 5V XIN input w(H) w(L) c(TA) w(TAH) TAiIN input w(TAL) c(UP) w(UPH) TAiOUT input w(UPL) TAiOUT input (Up/down input) During Event Counter Mode TAiIN input h(TIN-UP) su(UP-TIN) (When count on falling edge is selected) TAiIN input (When count on rising edge is selected) Two-Phase Pulse Input in Event Counter Mode...
Page 404 21. Electrical Characteristics (Normal-version) = 5V c(CK) w(CKH) CLKi w(CKL) h(C–Q) TxDi su(D–C) d(C–Q) h(C–D) RxDi w(INL) INTi input w(INH) Figure 21.2 Timing Diagram (2) = 5V HD:STA :STO HD:STA HD:DTA HIGH :DAT :STA Figure 21.3 Timing Diagram (3) page 378...
Page 405 21. Electrical Characteristics (Normal-version) = 3V Table 21.24 Electrical Characteristics (Note 1) " ( ) " " ( ) " µA e i l " ( ) " e i l L " ) " L " ) " µA e i l L "...
Page 406 21. Electrical Characteristics (Normal-version) = 3V Table 21.25 Electrical Characteristics (2) (Note 1) l l i µA µA l l i µA µA µA l l i ) 2 ( µA t i a a l l o i t y t i µA t i a...
Page 407 21. Electrical Characteristics (Normal-version) = 3V Timing Requirements = 3V, V = 0V, at Topr = – 20 to 85 C / – 40 to 85 C unless otherwise specified) Table 21.26 External Clock Input (X input) Standard Symbol Parameter Unit Min.
Page 408 21. Electrical Characteristics (Normal-version) = 3V Timing Requirements = 3V, V = 0V, at Topr = – 20 to 85 C / – 40 to 85 C unless otherwise specified) Table 21.27 Timer A Input (Counter Input in Event Counter Mode) Standard Symbol Parameter...
Page 409 21. Electrical Characteristics (Normal-version) = 3V Timing Requirements = 3V, V = 0V, at Topr = – 20 to 85 C / – 40 to 85 C unless otherwise specified) Table 21.33 Timer B Input (Counter Input in Event Counter Mode) Standard Symbol Parameter...
Page 410 21. Electrical Characteristics (Normal-version) = 3V Timing Requirements = 3V, V = 0V, at Topr = – 20 to 85 C / – 40 to 85 C unless otherwise specified) Table 21.39 Multi-master I C bus Line Standard clock mode High-speed clock mode Symbol Parameter...
Page 411 21. Electrical Characteristics (Normal-version) = 3V XIN input w(H) w(L) c(TA) w(TAH) TAiIN input w(TAL) c(UP) w(UPH) TAiOUT input w(UPL) TAiOUT input (Up/down input) During Event Counter Mode TAiIN input h(TIN-UP) su(UP-TIN) (When count on falling edge is selected) TAiIN input (When count on rising edge is selected) Two-Phase Pulse Input in Event Counter Mode...
Page 412 21. Electrical Characteristics (Normal-version) = 3V c(CK) w(CKH) CLKi w(CKL) h(C–Q) TxDi su(D–C) d(C–Q) h(C–D) RxDi w(INL) INTi input w(INH) Figure 21.5 Timing Diagram (2) = 3V HD:STA :STO HD:STA HD:DTA HIGH :DAT :STA Figure 21.6 Timing Diagram (3) page 386...
Page 413: T Version
21. Electrical Characteristics (T-version) 21.2 T version Table 21.40 Absolute Maximum Ratings 4 - < < ° 5 ° ° ° ° page 387...
Page 414 21. Electrical Characteristics (T-version) Table 21.41 Recommended Operating Conditions (Note 1) " ( ) " L " ) " " ( ) " " ( ) " L " ) " L " ) " l l i l l i l l i l l i l l i...
Page 415 21. Electrical Characteristics (T-version) Table 21.42 A/D Conversion Characteristics (Note 1) s t i ± n i l y t i ± ± ± ± ± l a i n i l y t i ± ± ± t s i kΩ...
Page 416 21. Electrical Characteristics (T-version) Table 21.43 Flash Memory Version Electrical Characteristics for 100/1000 E/W cycle products [Program Space and Data Space in U3; Program Space in U7] µs ° ) ° ) µs z i l Table 21.44 Flash Memory Version Electrical Characteristics for 10000 E/W cycle products [Data Space in U7 , 3 (...
Page 417 21. Electrical Characteristics (T-version) Table 21.45 Power Supply Circuit Timing Characteristics z i l z i l l l i µs µs µs d(P-R) Wait time to stabilize internal supply voltage when power-on d(ROC) td(P-R) td(ROC) Wait time to stabilize internal on-chip oscillator when power- RESET Interrupt for...
Page 418 21. Electrical Characteristics (T-version) = 5V Table 21.46 Electrical Characteristics (Note 1) " ( ) " µA " ( ) " " ( ) " e i l " ( ) " e i l L " ) " µA L "...
Page 419 21. Electrical Characteristics (T-version) = 5V Table 21.47 Electrical Characteristics (2) (Note 1) l l i l l i µA µA l l i µA µA µA l l i µA t i a ) 2 ( a l l o i t y t i ) 2 (...
Page 420 21. Electrical Characteristics (T-version) = 5V Timing Requirements = 5V, V = 0V, at Topr = – 40 to 85 C unless otherwise specified) Table 21.48 External Clock Input (X input) " ( ) " L " ) " page 394...
Page 421 21. Electrical Characteristics (T-version) = 5V Timing Requirements = 5V, V = 0V, at Topr = – 40 to 85 C unless otherwise specified) Table 21.49 Timer A Input (Counter Input in Event Counter Mode) Standard Symbol Parameter Unit Min. Max.
Page 422 21. Electrical Characteristics (T-version) = 5V Timing Requirements = 5V, V = 0V, at Topr = – 40 to 85 C unless otherwise specified) Table 21.55 Timer B Input (Counter Input in Event Counter Mode) Standard Symbol Parameter Unit Min. Max.
Page 423 21. Electrical Characteristics (T-version) = 5V Timing Requirements = 5V, V = 0V, at Topr = – 40 to 85 C unless otherwise specified) Table 21.61 Multi-master I C bus Line Standard clock mode High-speed clock mode Symbol Parameter Unit Min.
Page 424 21. Electrical Characteristics (T-version) = 5V XIN input w(H) w(L) c(TA) w(TAH) TAiIN input w(TAL) c(UP) w(UPH) TAiOUT input w(UPL) TAiOUT input (Up/down input) During Event Counter Mode TAiIN input h(TIN-UP) su(UP-TIN) (When count on falling edge is selected) TAiIN input (When count on rising edge is selected) Two-Phase Pulse Input in Event Counter Mode...
Page 425 21. Electrical Characteristics (T-version) = 5V c(CK) w(CKH) CLKi w(CKL) h(C–Q) TxDi su(D–C) d(C–Q) h(C–D) RxDi w(INL) INTi input w(INH) Figure 21.8 Timing Diagram (2) = 5V HD:STA :STO HD:STA HD:DTA HIGH :DAT :STA Figure 21.9 Timing Diagram (3) page 399...
Page 426 21. Electrical Characteristics (T-version) = 3V Table 21.62 Electrical Characteristics (Note) " ( ) " " ( ) " µA e i l " ( ) " e i l L " ) " L " ) " µA e i l L "...
Page 427 21. Electrical Characteristics (T-version) = 3V Table 21.63 Electrical Characteristics (2) (Note 1) l l i µA µA l l i µA µA µA l l i ) 2 ( µA t i a a l l o i t y t i µA t i a...
Page 428 21. Electrical Characteristics (T-version) = 3V Timing Requirements = 3V, V = 0V, at Topr = – 40 to 85 C unless otherwise specified) Table 21.64 External Clock Input (X input) Standard Symbol Parameter Unit Min. Max. External clock input cycle time External clock input HIGH pulse width External clock input LOW pulse width w(L)
Page 429 21. Electrical Characteristics (T-version) = 3V Timing Requirements = 3V, V = 0V, at Topr = – 40 to 85 C unless otherwise specified) Table 21.65 Timer A Input (Counter Input in Event Counter Mode) Standard Symbol Parameter Unit Min. Max.
Page 430 21. Electrical Characteristics (T-version) = 3V Timing Requirements = 3V, V = 0V, at Topr = – 40 to 85 C unless otherwise specified) Table 21.71 Timer B Input (Counter Input in Event Counter Mode) Standard Symbol Parameter Unit Min. Max.
Page 431 21. Electrical Characteristics (T-version) = 3V Timing Requirements = 3V, V = 0V, at Topr = – 40 to 85 C unless otherwise specified) Table 21.77 Multi-master I C bus Line Standard clock mode High-speed clock mode Symbol Parameter Unit Min.
Page 432 21. Electrical Characteristics (T-version) = 3V XIN input w(H) w(L) c(TA) w(TAH) TAiIN input w(TAL) c(UP) w(UPH) TAiOUT input w(UPL) TAiOUT input (Up/down input) During Event Counter Mode TAiIN input h(TIN-UP) su(UP-TIN) (When count on falling edge is selected) TAiIN input (When count on rising edge is selected) Two-Phase Pulse Input in Event Counter Mode...
Page 433 21. Electrical Characteristics (T-version) = 3V c(CK) w(CKH) CLKi w(CKL) h(C–Q) TxDi d(C–Q) su(D–C) h(C–D) RxDi w(INL) INTi input w(INH) Figure 21.11 Timing Diagram (2) = 3V HD:STA :STO HD:STA HD:DTA HIGH :DAT :STA Figure 21.12 Timing Diagram (3) page 407...
Page 434: Version
21. Electrical Characteristics (V-version) 21.3 V Version Table 21.78 Absolute Maximum Ratings 4 - < < ° 5 8 < < ° 5 ° ° ° ° page 408...
Page 435 21. Electrical Characteristics (V-version) Table 21.79 Recommended Operating Conditions " ( ) " L " ) " " ( ) " " ( ) " L " ) " L " ) " l l i ° ° l l i l l i l l i l l i...
Page 436 21. Electrical Characteristics (V-version) Table 21.80 A/D Conversion Characteristics s t i ± n i l y t i ± ± ± l a i n i l y t i ± ± ± t s i kΩ µs φ &...
Page 437 21. Electrical Characteristics (V-version) Table 21.81 Flash Memory Version Electrical Characteristics for 100/1000 E/W cycle products [Program Space and Data Space in U3; Program Space in U7] µs ° ) ° ) µs z i l Table 21.82 Flash Memory Version Electrical Characteristics for 10000 E/W cycle products [Data Space in U7 , 3 (...
Page 438 21. Electrical Characteristics (V-version) Table 21.83 Power Supply Circuit Timing Characteristics z i l z i l l l i µs µs µs d(P-R) Wait time to stabilize internal supply voltage when power-on d(ROC) td(P-R) td(ROC) Wait time to stabilize internal on-chip oscillator when power- RESET Interrupt for...
Page 439 21. Electrical Characteristics (V-version) = 5V Table 21.84 Electrical Characteristics " ( ) " µA " ( ) " " ( ) " e i l " ( ) " e i l L " ) " µA L " ) "...
Page 440 21. Electrical Characteristics (V-version) = 5V Table 21.85 Electrical Characteristics (2) l l i l l i µA µA l l i µA µA µA l l i µA t i a ) 2 ( a l l o i t y t i ) 2 ( µA...
Page 441 21. Electrical Characteristics (V-version) = 5V Timing Requirements ° (Vcc=5V, Vss=0V, at Topr=-40 to 125 C unless otherwise specified) Table 21.86 External Clock Input (XIN input) ° ° ° ° ° ° " ( ) " ° ° ° ° L "...
Page 442 21. Electrical Characteristics (V-version) = 5V Timing Requirements ° =5V, V =0V, at Topr=-40 to 125 C unless otherwise specified) Table 21.87 Timer A Input (Counter Input in Event Counter Mode) " ( ) " L " ) " Table 21.88 Timer A Input (Gating Input in Timer Mode) "...
Page 443 21. Electrical Characteristics (V-version) = 5V Timing Requirements ° =5V, V =0V, at Topr=-40 to 125 C unless otherwise specified) Table 21.93 Timer B Input (Counter Input in Event Counter Mode) " ( ) " L " ) " " ( ) "...
Page 444 21. Electrical Characteristics (V-version) = 5V Timing Requirements ° =5V, V =0V, at Topr=-40 to 125 C unless otherwise specified) Table 21.99 Multi-master I C Bus Line Standard clock mode High-speed clock mode Symbol Parameter Unit Min. Max. Min. Max. tBUF µs Bus free time...
Page 445 21. Electrical Characteristics (V-version) = 5V XIN input tw(H) tw(L) c(TA) w(TAH) input w(TAL) c(UP) w(UPH) input w(UPL) input (Counter increment/ decrement input) In event counter mode input –UP) (When count on falling edge) su(UP–T input (When count on rising edge) Two-phase pulse input in event counter mode c(TA)
Page 446 21. Electrical Characteristics (V-version) = 5V c(CK) w(CKH) CLKi w(CKL) h(C–Q) TxDi su(D–C) d(C–Q) h(C–D) RxDi w(INL) INTi input w(INH) Figure 21.14 Timing Diagram (2) = 5V HD:STA :STO HD:STA HD:DTA HIGH :DAT :STA Figure 21.15 Timing Diagram (3) page 420...
Page 447: Usage Notes
22. Usage Notes 22. Usage Notes 22.1 SFRs 22.1.1 For 80-Pin Package Set the IFSR20 bit in the IFSR2A register to 0 after reset and set bits PACR2 to PACR0 in the PACR register to 011 22.1.2 For 64-Pin Package Set the IFSR20bit in the IFSR2A register to 0 after reset and set bits PACR2 to PACR0 in the PACR register to 010 22.1.3 Register Setting...
Page 448: Clock Generation Circuit
22. Usage Notes 22.2 Clock Generation Circuit 22.2.1 PLL Frequency Synthesizer Stabilize supply voltage so that the standard of the power supply ripple is met. Standard Symbol Unit Parameter Min. Typ. Max. Power supply ripple allowable frequency(V (ripple) Power supply ripple allowabled amplitude =5V) p-p(ripple) voltage...
Page 449: Power Control
22. Usage Notes 22.2.2 Power Control 1. When exiting stop mode by hardware reset, the device will startup using the on-chip oscillator. 2. Set the MR0 bit in the TAiMR register(i=0 to 4) to 0 (pulse is not output) to use the timer A to exit stop mode.
Page 450 22. Usage Notes 5. Wait until the main clock oscillation stabilization time, before switching the CPU clock source to the main clock. Similarly, wait until the sub clock oscillates stably before switching the CPU clock source to the sub clock. 6.
Page 451: Protection
22. Usage Notes 22.3 Protection Set the PRC2 bit to 1 (write enabled) and then write to any address, and the PRC2 bit will be cleared to 0 (write protected). The registers protected by the PRC2 bit should be changed in the next instruction after setting the PRC2 bit to 1.
Page 452: Interrupts
22. Usage Notes 22.4 Interrupts 22.4.1 Reading Address 00000 Do not read the address 00000 in a program. When a maskable interrupt request is accepted, the CPU reads interrupt information (interrupt number and interrupt request priority level) from the address 00000 during the interrupt sequence.
Page 453: Int Interrupt
22. Usage Notes Changing the interrupt source (2,3) Disable interrupts Change the interrupt generate factor (including a mode change of peripheral function) Use the MOV instruction to clear the IR bit to 0 (interrupt not requested) (2,3) Enable interrupts End of change IR bit: A bit in the interrupt control register for the interrupt whose interrupt generate factor is to be changed NOTES:...
Page 454: Rewrite The Interrupt Control Register
22. Usage Notes 22.4.6 Rewrite the Interrupt Control Register (1) The interrupt control register for any interrupt should be modified in places where no requests for that interrupt may occur. Otherwise, disable the interrupt before rewriting the interrupt control register. (2) To rewrite the interrupt control register for any interrupt after disabling that interrupt, be careful with the instruction to be used.
Page 455: Dmac
22. Usage Notes 22.5 DMAC 22.5.1 Write to DMAE Bit in DMiCON Register When both of the conditions below are met, follow the steps below. (a) Conditions • The DMAE bit is set to 1 again while it remains set (DMAi is in an active state). •...
Page 456: Timers
22. Usage Notes 22.6 Timers 22.6.1 Timer A 22.6.1.1 Timer A (Timer Mode) 1. The timer remains idle after reset. Set the mode, count source, counter value, etc. using the TAiMR (i = 0 to 4) register and the TAi register before setting the TAiS bit in the TABSR register to 1 (count starts).
Page 457 22. Usage Notes 22.6.1.3 Timer A (One-shot Timer Mode) 1. The timer remains idle after reset. Set the mode, count source, counter value, etc. using the TAiMR (i = 0 to 4) register, the TAi register, bits TA0TGL and TA0TGH in the ONSF register and the TRGSR register before setting the TAiS bit in the TABSR register to 1 (count starts).
Page 458 22. Usage Notes 22.6.1.4 Timer A (Pulse Width Modulation Mode) 1. The timer remains idle after reset. Set the mode, count source, counter value, etc. using bits TA0TGL and TA0TGH in the TAiMR (i = 0 to 4) register, the TAi register, the ONSF register and the TRGSR register before setting the TAiS bit in the TABSR register to 1 (count starts).
Page 459: Timer B
22. Usage Notes 22.6.2 Timer B 22.6.2.1 Timer B (Timer Mode) 1. The timer remains idle after reset. Set the mode, count source, counter value, etc. using the TBiMR (i = 0 to 2) register and TBi register before setting the TBiS bit in the TABSR register to 1 (count starts).
Page 460: Three-Phase Motor Control Timer Function
22. Usage Notes 6. When a count is started and the first effective edge is input, an undefined value is transferred to the reload register. At this time, timer Bi interrupt request is not generated. 7. A value of the counter is undefined at the beginning of a count. MR3 may be set to 1 and timer Bi interrupt request may be generated between a count start and an effective edge input.
Page 461: Timer S
22. Usage Notes 22.7 Timer S 22.7.1 Rewrite the G1IR Register Bits in the G1IR register are not automatically set to 0 (no interrupt requested) even if a requested inter- rupt is acknowledged. Set each bit to 0 by program after the interrupt requests are verified. The IC/OC interrupt is generated when any bit in the G1IR register is set to 1 (interrupt requested) after all the bits are set to 0.
Page 462: Rewrite The Icociic Register
22. Usage Notes 22.7.2 Rewrite the ICOCiIC Register When the interrupt request to the ICOCiIC register is generated during the instruction process, the IR bit may not be set to 1 (interrupt requested) and the interrupt request may not be acknowledged. At that time, when the bit in the G1IR register is held to 1 (interrupt requested), the following IC/OC interrupt request will not be generated.
Page 463: Serial I/O
22. Usage Notes 22.8 Serial I/O 22.8.1 Clock-Synchronous Serial I/O 22.8.1.1 Transmission/reception _______ ________ 1. With an external clock selected, and choosing the RTS function, the output level of the RTSi pin goes to “L” when the data-receivable status becomes ready, which informs the transmission side ________ that the reception has become ready.
Page 464: Uart Mode
22. Usage Notes 22.8.2 UART Mode 22.8.2.1 Special Mode 1 (I C bus Mode) When generating start, stop and restart conditions, set the STSPSEL bit in the U2SMR4 register to 0 and wait for more than half cycle of the transfer clock before setting each condition generate bit (STAREQ, RSTAREQ and STPREQ) from 0 to 1.
Page 465: A/D Converter
22. Usage Notes 22.9 A/D Converter 1. Set registers ADCON0 (except bit 6), ADCON1, ADCON2 and ADTRGCON when A/D conversion is stopped (before a trigger occurs). 2. When the VCUT bit in ADCON1 register is changed from 0 (Vref not connected) to 1 (Vref connected), start A/D conversion after passing 1 µs or longer.
Page 466 22. Usage Notes 8. If the CPU reads the ADi register (i = 0 to 7) at the same time the conversion result is stored in the ADi register after completion of A/D conversion, an incorrect value may be stored in the ADi register. This problem occurs when a divide-by-n clock derived from the main clock or a subclock is selected for CPU clock.
Page 467: Multi-Master I 2 C Bus Interface
22. Usage Notes 22.10 Multi-Master I C bus Interface 22.10.1 Writing to the S00 Register When the start condition is not generated, the SCL pin may output the short low-signal ("L") by setting the S00 register. Set the register when the SCL pin outputs an "L" signal. 22.10.2 AL Flag When the arbitration lost is generated and the AL flag in the S10 register is set to 1 (detected), the AL flag can be cleared to 0 (not detected) by writing a transmit data to the S00 register.
Page 468: Can Module
22. Usage Notes 22.11 CAN Module 22.11.1 Reading C0STR Register The CAN module on the M16C/29 Group updates the status of the C0STR register in a certain period. When the CPU and the CAN module access to the C0STR register at the same time, the CPU has the access priority;...
Page 469 22. Usage Notes CPU read signal Updating period of CAN module CPU reset signal C0STR register b8: State_Reset bit 0: CAN operation mode : When the CAN module’s State_Reset bit updating period matches the CPU’s read 1: CAN reset/initial- period, it does not enter reset mode, for the CPU read has the higher priority. ization mode Figure 22.5 When Updating Period of CAN Module Matches Access Period from CPU Wait time...
Page 470: Can Transceiver In Boot Mode
22. Usage Notes 22.11.2 CAN Transceiver in Boot Mode When programming the flash memory in boot mode via CAN bus, the operation mode of CAN transceiver should be set to “high-speed mode” or “normal operation mode”. If the operation mode is controlled by the MCU, CAN transceiver must be set the operation mode to “high-speed mode”...
Page 471: Programmable I/O Ports
22. Usage Notes 22.12 Programmable I/O Ports _____ 1. If a low-level signal is applied to the SD pin when the IVPCR1 bit in the TB2SC register is set to 1 _____ (three-phase output forcible cutoff by input on SD pin enabled), the P7 to P7 , P8 and P8...
Page 472: Electric Characteristic Differences Between Mask Rom
22. Usage Notes 22.13 Electric Characteristic Differences Between Mask ROM and Flash Memory Version Flash memory version and mask ROM version may have different characteristics, operating margin, noise tolerated dose, noise width dose in electrical characteristics due to internal ROM, different layout pattern, etc.
Page 473: Mask Rom Version
22. Usage Notes 22.14 Mask ROM Version 22.14.1 Internal ROM Area In the masked ROM version, do not write to internal ROM area. Writing to the area may increase power consumption. 22.14.2 Reserved Bit The b3 to b0 in addresses 0FFFFF are reserved bits.
Page 474: Flash Memory Version
22. Usage Notes 22.15 Flash Memory Version 22.15.1 Functions to Inhibit Rewriting Flash Memory Rewrite ID codes are stored in addresses 0FFFDF , 0FFFE3 , 0FFFEB , 0FFFEF , 0FFFF3 , 0FFFF7 and 0FFFFB . If wrong data are written to theses addresses, the flash memory cannot be read or written in standard serial I/O mode.
Page 475: Interrupts
22. Usage Notes 22.15.9 Interrupts EW Mode 0 • Any interrupt which has a vector in the variable vector table can be used providing that its vector is transferred into the RAM area. _______ • The NMI and watchdog timer interrupts can be used because the FMR0 register and FMR1 register are initialized when one of those interrupts occurs.
Page 476: Definition Of Programming/Erasure Times
22. Usage Notes 22.15.14 Definition of Programming/Erasure Times "Number of programs and erasure" refers to the number of erasure per block. If the number of program and erasure is n (n=100 1,000 10,000) each block can be erased n times. For example, if a 2K byte block A is erased after writing 1 word data 1024 times, each to a different address, this is counted as one program and erasure.
Page 477: Noise
22. Usage Notes 22.16 Noise Connect a bypass capacitor (approximately 0.1µF) across the V and V pins using the shortest and thicker possible wiring. Figure 22.8 shows the bypass capacitor connection. M16C/29 Group Connecting Pattern Connecting Pattern Bypass Capacitor Figure 22.8 Bypass Capacitor Connection page 451...
Page 478: Instruction For A Device Use
22. Usage Notes 22.17 Instruction for a Device Use When handling a device, extra attention is necessary to prevent it from crashing during the electrostatic discharge period. page 452...
Page 479 Appendix 1. Package Dimensions Appendix 1. Package Dimensions JEITA Package Code RENESAS Code Previous Code MASS[Typ.] P-LQFP64-10x10-0.50 PLQP0064KB-A 64P6Q-A / FP-64K / FP-64KV 0.3g NOTE) *2" INCLUDE TRIM OFFSET. Reference Symbol 10.0 10.1 10.0 10.1 Terminal cross section 11.8 12.0 12.2...
Page 480 Appendix 2. Functional Comparison Appendix 2. Functional Comparison Appendix 2.1 Difference between M16C/28 Group and M16C/29 Group (Normal-ver.) ) . r ) . r a l i s t i a l i ) t i ) t i t s i c t i a l i ) t i...
Page 481 Appendix 2. Functional Comparison Appendix 2.2 Difference between M16C/28 and M16C/29 Group (T-ver./V-ver.) ) . r ) . r t s i c t i a l i ) t i t s i c t i a l i ) t i t s i a l i...
Page 482 Register Index Register Index DM0IC 76 DM0SL 93 AD0 to AD7 226 DM1CON 94 ADCON0 to ADCON2 224 DM1IC 76 ADIC 76 DM1SL 94 ADSTAT0 226 DTT 129 ADTRGCON 225 AIER 88 FMR0 341 FMR1 341 BCNIC 76 FMR4 342 BTIC 76 G1BCR0 142 C01ERRIC 76...
Page 483 Register Index S4BRG 218 S4C 218 KUPIC 76 S4D0 262 S4IC 76 S4TRR 218 NDDR 327 SAR0 95 SAR1 95 SCLDAIC 76 ONSF 105 TA0 to TA4 104 P0 to P3 324 TA0IC to TA4IC 76 P17DDR 327 TA0MR to TA4MR 103 P6 to P10 324 TA11 130 PACR 177, 326...
Page 484 Register Index VCR1 39 VCR2 39 WDC 90 WDTS 90 page 458...
Page 485 REVISION HISTORY M16C/29 Hardware Manual Rev. Date Description Page Summary 0.70 Mar/ 29/Y04 “1. Overview” and “1.1. Application” are partly revised. 2, 3 Table 1.2.1 and 1.2.2 are partly revised. 8, 9 Figure 1.5.1 and 1.5.2 are partly revised. Table 1.6.1 is revised. Figure 4.8 is partly revised.
Page 486 REVISION HISTORY M16C/29 Hardware Manual Rev. Date Description Page Summary “Figure 12.3.9 PFCR register and TPRC register” is deleted. Figure 12.3.1.2.1 and the section 12.3.1.2.4 are partly revised. Section “Three-phase/Port Output Switch Function” and “Figure 12.3.2.1 PFCR register and TPRC register” are added. “UART 2 special mode register 2”...
Page 487 REVISION HISTORY M16C/29 Hardware Manual Rev. Date Description Page Summary Figure 21.9.1 is partly revised. Figure 21.9.2 is partly revised. Section “21.10.1 ROM Code Protect Function” is partly revised. Section “21.11.1 ROM Code Protect Function” is partly revised. Table 21.11.1 is revised. Figure 21.11.1 is revised.
Page 488 REVISION HISTORY M16C/29 Hardware Manual Rev. Date Description Page Summary Table 21.1 is partly revised. Section “21.4.2 EW1 Mode” is partly revised. 0.80 Sep/03/Y04 Table 1.2.1 and Table 1.2.2 are partly revised. Table 1.4.1 to Table 1.4.3 are partly revised. Figure 1.4.1 is partly revised.
Page 489 REVISION HISTORY M16C/29 Hardware Manual Rev. Date Description Page Summary “9.3 Interrupt Control” is partly revised. ______ _______ “9.6 INT Interrupt” and “9.7 NMI Interrupt” are partly revised. “9.8 Key Input Interrupt” and “9.9 CAN0 Wake-up Interrupt” are partly revised. “10.
Page 490 REVISION HISTORY M16C/29 Hardware Manual Rev. Date Description Page Summary Overview • Table 1.1 and 1.2 Performance Outline Voltage detection circuit are modified, note 3 is modified 4 - 5 • Figure 1.1 and 1.2 Block Diagrams are updated 6 - 7 •...
Page 491 REVISION HISTORY M16C/29 Hardware Manual Rev. Date Description Page Summary • Figure 7.11 State Transition to Stop Mode and Wait Mode modified, Note 7 is added • Figure 7.12 State Transition in Normal Mode modified, note 5 deleted, note 6 and 7 are simplified •...
Page 492 REVISION HISTORY M16C/29 Hardware Manual Rev. Date Description Page Summary note 1 is added • Figure 13.21 Prescaler Function and Gate Function Note 1 modified • Table 13.10 SR Waveform Output Mode Specifications Specification modified • Figure 13.24 Set/Reset Waveform Output Mode Description for (1) Free-run- ning operation modified, register names modified •...
Page 493 REVISION HISTORY M16C/29 Hardware Manual Rev. Date Description Page Summary • Figure 14.31 Transmit and Received Timing in SIM Mode partially modified • 14.2 SI/O3 and SI/O4 Note added • Figure 14.36 S3C and S4C Registers Note 5 is added •...
Page 494 REVISION HISTORY M16C/29 Hardware Manual Rev. Date Description Page Summary • Figure 16.3 S00 Register Note is modified • Figure 16.4 S1D0 Register Reserved bit map modified • Figure 16.5 S10 Register b7-b6 modified • Figure 16.7 S4D0 Register Bit reserved map is modified •...
Page 495 REVISION HISTORY M16C/29 Hardware Manual Rev. Date Description Page Summary • Table 19.1 Unassigned Pin Handling in Single-chip Mode Note 5 added Flash Memory Version • 20.1 Flash Memory Performance Description partially deleted • Table 20.14 Flash Memory Version Specifications Note 3 added •...
Page 496 REVISION HISTORY M16C/29 Hardware Manual Rev. Date Description Page Summary • Table 21.41 Recommended Operating Conditions V and V are modified • Table 21.42 A/D Conversion Characeristics t deleted, note 4 added SAMP • Table 21.43 Flash Memory Version Electrical Characteristics: Standard val- ues of Program and Erase Endrance cycle modified, tps added •...
Page 497 REVISION HISTORY M16C/29 Hardware Manual Rev. Date Description Page Summary products (U7, U9) added • 22.15.16 Boot Mode added • 22.16 Noise added • 20.17 Instruction fo Device Use added Appendix 1. Package Dimensions • Dimensions are updated 454-455 Appendix 2. Functional Comparison added 1.11 Dec.11,2006 Clock Generation Circuit...
Page 498 REVISION HISTORY M16C/29 Hardware Manual Rev. Date Description Page Summary • Tables 1.6 to 1.8 Product Codes modified 19, 20 • Table 1.14 Pin Description pin description on I/O ports modified Reset • Figure 5.2 Reset Sequence Vcc and ROC timings modified Processor Mode •...
Page 499 REVISION HISTORY M16C/29 Hardware Manual Rev. Date Description Page Summary 4 deleted • Table 21.63 Elctrical Characteristics measurement condition modified, note 4 deleted •Tables 21.81 and 21.82 Flash Memory Version Electrical Characteristics note 10 modified •Timing figure for td(P-R) and td(ROC) modified •Table 21.85 Electrical Characteristics measurment condition modified, note 4 deleted Usage Notes...
Page 500 RENESAS 16-BIT SINGLE-CHIP MICROCOMPUTER HARDWARE MANUAL M16C/29 Group Publication Data : Rev.0.70 Mar. 29, 2004 Rev.1.12 Mar. 30, 2007 Published by : Sales Strategic Planning Div. Renesas Technology Corp. © 2007. Renesas Technology Corp., All rights reserved. Printed in Japan.
Page 501 M16C/29 Group Hardware Manual 1753, Shimonumabe, Nakahara-ku, Kawasaki-shi, Kanagawa 211-8668 Japan REJ09B0101-0112...

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