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M16C/64A Group
23.3.3
Special Mode 1 (I
2
I
C mode is compatible with the simplified I
Table 23.16 and Table 23.17 list the Registers Used and Settings in I
Mode Functions. Figure 23.18 shows the I
As shown in Table 23.18, the MCU is placed in I
1 and bits SMD2 to SMD0 in the UiMR register to 010b. Because SDAi transmit output has a delay circuit
attached, SDAi output does not change state until SCLi goes low and remains stably low.
I 2 C Mode Specifications
Table 23.14
Item
Data format
Transfer clock
Transmit/receive clock
Reception start conditions
Interrupt request
generation timing
Error detection
Selectable functions
i = 0 to 2, 5 to 7
Notes:
1.
These requirements do not have to be set in any particular order. When transmission/reception is
started as a slave and the TXEPT bit in the UiC0 register is 1 (no data present in transmit register),
meet the last requirement when the external clock is high.
2.
If an overrun error occurs, the received data of the UiRB register will be undefined.
R01UH0136EJ0210 Rev.2.10
Jul 31, 2012
2
C Mode)
2
C interface. Table 23.14 lists the I
2
C Mode Block Diagram.
2
C mode by setting the IICM bit in the UiSMR register to
Character bit length: 8 bits
•
Master mode
The CKDIR bit in the UiMR register is 0 (internal clock): fj / (2(n+1))
fj = f1SIO, f2SIO, f8SIO, f32SIO
n = setting value of the UiBRG register (03h to FFh)
•
Slave mode
The CKDIR bit is 1 (external clock): input from the SCLi pin
To start transmission, satisfy the following requirements
•
The TE bit in the UiC1 register is 1 (transmission enabled)
•
The TI bit in the UiC1 register is 0 (data present in UiTB register)
To start reception, satisfy the following requirements
•
The RE bit in the UiC1 register is 1 (reception enabled)
•
The TE bit in the UiC1 register is 1 (transmission enabled)
•
The TI bit in the UiC1 register is 0 (data present in the UiTB register)
When a start condition, stop condition, ACK (acknowledge), or NACK (not-
acknowledge) is detected.
(2)
Overrun error
This error occurs if the serial interface starts receiving the next unit of data
before reading the UiRB register and receives the eighth bit of the unit of
next data.
•
Arbitration lost
Timing at which the ABT bit in the UiRB register is updated can be selected.
•
SDAi digital delay
No digital delay or a delay of 2 to 8 UiBRG count source clock cycles can
be selected.
•
Clock phase setting
With or without clock delay can be selected.
23. Serial Interface UARTi (i = 0 to 2, 5 to 7)
2
C Mode Specifications.
2
C Mode. Table 23.18 lists the I
Specification
(1)
2
C
(1)
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