Renesas M16C/64A Series User Manual page 580

M16C/64A Group
PED (SDAMM/port function switch bit) (b2)
PEC (SCLMM/port function switch bit) (b3)
Bits PEC and PED are enabled when the ES0 bit in the S1D0 register is 1 (I
When the PEC bit is set to 1 (output port), the P7_1 bit value is output from the SCLMM pin regardless
of the internal SCL output signal and PD7_1 bit value. When the PED bit is set to 1 (output port), the
P7_0 bit value is output from the SDAMM pin regardless of the internal SDA output signal and PD7_0
bit value.
The signal level on the bus is input to the internal SDA and internal SCL.
When bits P7_1 to P7_0 in the P7 register are read after setting bits PD7_1 and PD7_0 in the PD7
register to 0 (input mode), the level on the bus can be read regardless of the values set to bits PED and
PEC. Table 25.7 lists SCLMM and SDAMM Pin Functions.
Table 25.7 SCLMM and SDAMM Pin Functions
S1D0 Register
Pin
P7_1/SCLMM
P7_0/SDAMM
–: 0 or 1
SDAM (Internal SDA output monitor bit) (b4)
SCLM (Internal SCL output monitor bit) (b5)
The internal SDA and SCL output signal levels are the same as the output level of the I
before it has any effect from the external device output. Bits SDAM and SCLM are read only bits. If
necessary, set these bits to 0.
ICK1 and ICK0 (I
Rewrite these bits when the ES0 bit in the S1D0 register is 0 (I
by setting all the bits ICK1 to ICK0, bits ICK4 to ICK2 in the S4D0 register, and the PCLK0 bit in the
PCLKR register. Refer to 25.3.1.2 "Bit Rate and Duty Cycle".
2
Table 25.8 I C-bus System Clock Select Bits
S4D0 Register
ICK4 Bit ICK3 Bit
0
0
0
0
0
0
1
–: 0 or 1
Only set the values listed above.
R01UH0136EJ0210 Rev.2.10
Jul 31, 2012
S3D0 Register
ES0 bit PED bit
0 -
-
1
-
0 -
0
1
1
2
C-bus system clock select bit) (b7-b6)
ICK2 Bit
0 0
0 0
0 0
0 1
1 0
1 1
0 0
PEC bit
- I/O port or other peripheral pins
0 SCLMM (SCL input/output)
1 Output port (output P7_1 bit value)
- I/O port or other peripheral pins
- SDAMM (SDA input/output)
- Output port (output P7_0 bit value)
2
C interface disabled). fVIIC is selected
S3D0 Register
ICK1 Bit ICK0 Bit
0 0
0 1
1 0
– –
– –
– –
– –
2
25. Multi-master I C-bus Interface
2
C interface enabled).
Pin Function
2
C interface
fVIIC
fIIC divided-by-2
fIIC divided-by-4
fIIC divided-by-8
fIIC divided-by-2.5
fIIC divided-by-3
fIIC divided-by-5
fIIC divided-by-6
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