Page 1 On April 1 , 2010, NEC Electronics Corporation merged with Renesas Technology Corporation, and Renesas Electronics Corporation took over all the business of both companies. Therefore, although the old company name remains in this document, it is a valid Renesas Electronics document. We appreciate your understanding.
Page 2 Renesas Electronics. Renesas Electronics shall not be in any way liable for any damages or losses incurred by you or third parties arising from the use of any Renesas Electronics product for an application categorized as “Specific”...
Page 3 User’s Manual V850/SA1 32-Bit Single-chip Microcontroller Hardware µ µ PD703014A PD70F3015B µ µ PD703014AY PD70F3015BY µ µ PD703014B PD70F3017A µ µ PD703014BY PD70F3017AY µ PD703015A µ PD703015AY µ PD703015B µ PD703015BY µ PD703017A µ PD703017AY Document No. U12768EJ4V1UD00 (4th edition) Date Published August 2005 N CP(K) ©...
Page 4 [MEMO] User’s Manual U12768EJ4V1UD...
Page 5 NOTES FOR CMOS DEVICES VOLTAGE APPLICATION WAVEFORM AT INPUT PIN Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the CMOS device stays in the area between V (MAX) and V (MIN) due to noise, etc., the device may malfunction.
Page 6 Windows is either a registered trademark or a trademark of Microsoft Corporation in the United States and/or other countries. These commodities, technology or software, must be exported in accordance with the export administration regulations of the exporting country. Diversion contrary to the law of that country is prohibited. •...
Page 7 Regional Information Some information contained in this document may vary from country to country. Before using any NEC Electronics product in your application, pIease contact the NEC Electronics office in your country to obtain a list of authorized representatives and distributors. They will verify: •...
Page 8 µ Deletion of PD703014AGC, 703014AYGC, 703015AGC, and 703015AYGC p. 27 Addition of Table 1-1 List of V850/SA1 Products p. 28 Addition of description to minimum instruction execution time in 1.2 Features p. 30 Deletion and addition of products in 1.4 Ordering Information p.
Page 9 Addition of Caution in CHAPTER 16 FLASH MEMORY p. 398 Change of description in 16.1.1 Erasing unit p. 400 Addition of Figure 16-1 Wiring Example of V850/SA1 Flash Writing Adapter (FA-100GC-8EU) p. 401 Addition of Table 16-1 Wiring Table of V850/SA1 Flash Writing Adapter (FA-100GC-8EU) p. 402 Addition of Figure 16-2 Wiring Example of V850/SA1 Flash Writing Adapter (FA-121F1-EA6) p.
Page 10 INTRODUCTION Readers This manual is intended for users who wish to understand the functions of the V850/SA1 µ PD703014A, 703014AY, 703014B, 703014BY 703015A, 703015AY, 703015B, 703015BY, 703017A, 703017AY, 70F3015B, 70F3015BY, 70F3017A, 70F3017AY) and design application systems using the V850/SA1. Purpose This manual is intended to give users an understanding of the hardware functions described in the Organization below.
Page 11 Conventions Data significance: Higher digits on the left and lower digits on the right Active low representation: xxx (overscore over pin or signal name) Memory map address: Higher addresses on the top and lower addresses on the bottom Note: Footnote for items marked with Note in the text Caution: Information requiring particular attention Remark: Supplementary information Numerical representation:...
Page 12 Related Documents The related documents indicated in this publication may include preliminary versions. However, preliminary versions are not marked as such. Documents related to V850/SA1 Document Name Document No. V850 Series Architecture User’s Manual U10243E V850/SA1 Application Note U13851E V850/SA1 Hardware User’s Manual This manual V850 Series Flash Memory Self Programming User’s Manual...
Page 13: Table Of Contents
CONTENTS CHAPTER 1 INTRODUCTION .........................27 General ............................27 Features.............................28 Applications ..........................30 Ordering Information .......................30 Pin Configuration ........................31 Function Blocks ........................34 1.6.1 Internal block diagram ......................... 34 1.6.2 Internal units..........................35 CHAPTER 2 PIN FUNCTIONS........................38 List of Pin Functions........................38 Pin States ..........................43 Description of Pin Functions ....................44 Pin I/O Circuits and Recommended Connection of Unused Pins........55 Pin I/O Circuits..........................57...
Page 14 Memory Block Function......................92 Wait Function ..........................93 4.5.1 Programmable wait function ......................93 4.5.2 External wait function ........................94 4.5.3 Relationship between programmable wait and external wait ............94 Idle State Insertion Function ....................95 Bus Hold Function........................96 4.7.1 Outline of function........................96 4.7.2 Bus hold procedure ........................97 4.7.3 Operation in power save mode....................97 Bus Timing ..........................98...
Page 15 Interrupt Control Register Bit Manipulation Instructions During DMA Transfer.....137 CHAPTER 6 CLOCK GENERATION FUNCTION ................138 General ............................138 Configuration ..........................139 Clock Output Function......................139 6.3.1 Control registers........................140 Power Save Functions ......................143 6.4.1 General ............................. 143 6.4.2 HALT mode ..........................144 6.4.3 IDLE mode ..........................
Page 16 Operation..........................211 8.4.1 Operation as watch timer......................211 8.4.2 Operation as interval timer ......................211 8.4.3 Cautions ............................212 CHAPTER 9 WATCHDOG TIMER ....................... 213 Functions..........................213 Configuration ......................... 215 Watchdog Timer Control Register ..................215 Operation..........................218 9.4.1 Operating as watchdog timer.....................218 9.4.2 Operating as interval timer ......................219 Standby Function Control Register ..................
Page 17 11.4 Operation..........................316 11.4.1 Basic operation ......................... 316 11.4.2 Input voltage and conversion result................... 318 11.4.3 A/D converter operation mode ....................319 11.5 Notes on Using A/D Converter....................322 11.6 How to Read A/D Converter Characteristics Table.............326 CHAPTER 12 DMA FUNCTIONS......................330 12.1 Functions ..........................330 12.2 Features...........................330 12.3 Configuration ..........................331 12.4 Control Registers ........................332...
Page 18 CHAPTER 15 RESET FUNCTION ....................... 397 15.1 General ........................... 397 15.2 Pin Operations ........................397 CHAPTER 16 FLASH MEMORY ......................398 16.1 Features..........................398 16.1.1 Erasing unit ..........................398 16.2 Writing by Flash Programmer ....................399 16.3 Programming Environment ....................404 16.4 Communication System......................
Page 19 CHAPTER 19 RECOMMENDED SOLDERING CONDITIONS ............462 APPENDIX A NOTES ON TARGET SYSTEM DESIGN..............466 APPENDIX B REGISTER INDEX......................468 APPENDIX C LIST OF INSTRUCTION SETS ..................473 APPENDIX D INDEX ..........................480 APPENDIX E REVISION HISTORY .......................486 User’s Manual U12768EJ4V1UD...
Page 20 LIST OF FIGURES (1/6) Figure No. Title Page CPU Register Set ............................60 CPU Address Space............................66 Image on Address Space ..........................67 Program Space..............................68 Data Space ..............................68 Memory Map..............................69 Internal ROM Area (64 KB)..........................70 Internal ROM Area (128 KB)..........................70 Internal ROM/Internal Flash Memory Area (256 KB) ..................71 3-10 Internal RAM Area (4 KB) ..........................73 3-11...
Page 21 LIST OF FIGURES (2/6) Figure No. Title Page 5-13 Illegal Opcode ............................... 129 5-14 Exception Trap Processing..........................130 5-15 RETI Instruction Processing .......................... 131 5-16 Pipeline Operation at Interrupt Request Acknowledgement ................135 5-17 Pipeline Flow and Interrupt Request Signal Generation Timing ..............137 Clock Generator ............................
Page 22 LIST OF FIGURES (3/6) Figure No. Title Page 7-27 Data Hold Timing of Capture Register ......................185 7-28 Operation Timing of OVFn Flag ........................186 7-29 Block Diagram of TM2 to TM5 ........................190 7-30 Timing of Interval Timer Operation ........................197 7-31 Timing of External Event Counter Operation (When Rising Edge Is Set) ............200 7-32 Timing of Square Wave Output Operation .....................201 7-33...
Page 23 LIST OF FIGURES (4/6) Figure No. Title Page 10-22 Example of Slave to Master Communication (When 9-Clock Wait Is Selected for Both Master and Slave) ..............................283 10-23 Block Diagram of UARTn ..........................287 10-24 Settings of ASIMn (Operation Stop Mode) ....................294 10-25 ASIMn Setting (UART Mode) ........................
Page 24 14-21 Block Diagram of P120 ..........................392 15-1 System Reset Timing.............................397 16-1 Wiring Example of V850/SA1 Flash Writing Adapter (FA100GC-8EU) ............400 16-2 Wiring Example of V850/SA1 Flash Writing Adapter (FA-121F1-EA6) ............402 16-3 Environment for Writing Programs to Flash Memory ..................404 16-4 Communication with Dedicated Flash Programmer (UART0)................404...
Page 25 LIST OF FIGURES (6/6) Figure No. Title Page 16-17 Timing to Apply Voltage to V Pin ........................ 416 16-18 Area Configuration............................422 16-19 Flow of Erasing Flash Memory ........................428 16-20 Successive Writing Flow..........................429 16-21 Internal Verify Flow............................430 16-22 Flow of Acquiring Flash Information ......................
Page 26 LIST OF TABLES (1/3) Table No. Title Page List of V850/SA1 Products..........................27 Pin I/O Buffer Power Supplies .........................38 Operating States of Pins in Each Operating Mode ..................43 Program Registers............................61 System Register Numbers ..........................62 Interrupt/Exception Table..........................72 Bus Control Pins ..............................89 Number of Access Clocks..........................90 Bus Priority ..............................105...
Page 27 Alternate Function of Port 12......................... 390 14-13 Setting When Port Pin Is Used for Alternate Function .................. 393 16-1 Wiring Table of V850/SA1 Flash Writing Adapter (FA-100GC-8EU) ............. 401 16-2 Wiring Table of V850/SA1 Flash Writing Adapter (FA-121F1-EA6)............... 403 16-3 Signal Generation of Dedicated Flash Programmer (PG-FP3 or PG-FP4) ............
Page 28 LIST OF TABLES (3/3) Table No. Title Page 16-13 Errors During Self-Programming........................421 16-14 Flash Information ............................421 19-1 Surface Mounting Type Soldering Conditions....................462 Symbols in Operand Description ........................473 Symbols Used for Opcode ..........................474 Symbols Used for Operation Description .......................474 Symbols Used for Flag Operation........................475 Condition Codes ............................475 User’s Manual U12768EJ4V1UD...
Page 29: Chapter 1 Introduction
CHAPTER 1 INTRODUCTION The V850/SA1 is a low-power series product in the NEC Electronics V850 Series of single-chip microcontrollers designed for real-time control. 1.1 General The V850/SA1 is a 32-bit single-chip microcontroller that includes the V850 Series CPU core, and peripheral functions such as ROM/RAM, a timer/counter, a serial interface, an A/D converter, and a DMA controller.
Page 30: Features
CHAPTER 1 INTRODUCTION 1.2 Features Number of instructions Minimum instruction execution time 50 ns (@20 MHz operation with main clock (f 58.8 ns (@17 MHz operation with main clock (f µ 30.5 s (@32.768 kHz operation with subclock (f 32 bits × 32 registers General-purpose registers Signed multiplication (16 ×...
Page 31 CHAPTER 1 INTRODUCTION Serial interface (SIO) Asynchronous serial interface (UART) Clocked serial interface (CSI) µ C bus interface (I C) ( PD703014AY, 703014BY, 703015AY, 703015BY, 703017AY, 70F3015BY, and 70F3017AY only) UART: 1 channel CSI: 1 channel UART/CSI: 1 channel C/CSI: 1 channel UART dedicated baud rate generator: 2 channels A/D converter 10-bit resolution: 12 channels...
Page 32: Applications
100-pin plastic LQFP (fine pitch) (14×14) 256 KB (flash memory) Remarks 1. “×××” indicates ROM code suffix. 2. The V850/SA1 does not include any ROMless versions. 3. Products with -A at the end of the part number are lead-free products. User’s Manual U12768EJ4V1UD...
Page 33: Pin Configuration
CHAPTER 1 INTRODUCTION 1.5 Pin Configuration 100-pin plastic LQFP (fine pitch) (14 × 14) µ µ µ • • • PD703014BGC-×××-8EU PD703017AGC-×××-8EU PD70F3017AGC-8EU µ µ µ • • • PD703014BGC-×××-8EU-A PD703017AGC-×××-8EU-A PD70F3017AGC-8EU-A • µ • µ • µ PD703014BYGC-×××-8EU PD703017AYGC-×××-8EU PD70F3017AYGC-8EU µ...
Page 34 CHAPTER 1 INTRODUCTION 121-pin plastic FBGA (12 × 12) µ µ µ • • • PD703014AF1-×××-EA6 PD703015AYF1-×××-EA6 PD70F3015BF1-EA6-A µ µ µ • • • PD703014AF1-×××-EA6-A PD703015AYF1-×××-EA6-A PD70F3015BYF1-EA6-A µ µ µ • • • PD703014AYF1-×××-EA6 PD703015BF1-×××-EA6-A PD70F3017AF1-EA6 µ µ µ • •...
Page 35 CHAPTER 1 INTRODUCTION Pin Identification A1 to A21: Address bus P90 to P96: Port 9 AD0 to AD15: Address/data bus P100 to P107: Port 10 ADTRG: A/D trigger input P110 to P114: Port 11 ANI0 to ANI11: Analog input P120 Port 12 ASCK0, ASCK1: Asynchronous serial clock...
Page 36: Function Blocks
CHAPTER 1 INTRODUCTION 1.6 Function Blocks 1.6.1 Internal block diagram HLDRQ (P96) INTC Instruction HLDAK (P95) INTP0 to INTP6 queue ASTB (P94) Note DSTB/RD (P93) TI00, TI01, 32-bit barrel Multiplier R/W/WRH (P92) TI10, TI11 16 × 16 → 32 Timer/counter register UBEN (P91) TO0, TO1...
Page 37: Internal Units
CHAPTER 1 INTRODUCTION 1.6.2 Internal units (1) CPU The CPU uses five-stage pipeline control to enable single-clock execution of address calculations, arithmetic logic operations, data transfers, and almost all other instruction processing. Other dedicated on-chip hardware, such as the multiplier (16 bits × 16 bits → 32 bits) and the 32-bit barrel shifter help accelerate processing of complex instructions.
Page 38 When used as an interval timer, it generates a maskable interrupt request (INTWDTM) after an overflow occurs. (10) Serial interface (SIO) The V850/SA1 includes four serial interface channels: for the asynchronous serial interface (UART0, UART1), clocked serial interface (CSI0 to CSI2), and I C bus interface. One of these channels is switchable between the UART and CSI and another is switchable between CSI and I C.
Page 39 CHAPTER 1 INTRODUCTION (14) Ports As shown below, the following ports have general-purpose port functions and control pin functions. Port Port Function Control Function Port 0 8-bit I/O General- NMI, external interrupt, A/D converter trigger, RTP trigger purpose port Port 1 6-bit I/O Serial interface Port 2...
Page 40: Chapter 2 Pin Functions
CHAPTER 2 PIN FUNCTIONS 2.1 List of Pin Functions The names and functions of the pins of the V850/SA1 are described below divided into port pins and non-port pins. There are three types of power supplies for the pin I/O buffers: AV...
Page 41 CHAPTER 2 PIN FUNCTIONS (2/3) Pin Name PULL Function Alternate Function Port 3 TI00 8-bit I/O port TI01 Input/output mode can be specified in 1-bit units. TI10 TI11 TO0/A13 TO1/A14 TI4/TO4/A15 TI5/TO5 Port 4 8-bit I/O port Input/output mode can be specified in 1-bit units. Port 5 8-bit I/O port Input/output mode can be specified in 1-bit units.
Page 42 CHAPTER 2 PIN FUNCTIONS (3/3) Pin Name PULL Function Alternate Function Input Port 7 ANI0 8-bit input port ANI1 ANI2 ANI3 ANI4 ANI5 ANI6 ANI7 Input Port 8 ANI8 4-bit input port ANI9 ANI10 ANI11 Port 9 LBEN/WRL 7-bit I/O port UBEN Input/output mode can be specified in 1-bit units.
Page 43 CHAPTER 2 PIN FUNCTIONS (2) Non-port pins (1/2) Pin Name PULL Function Alternate Function A1 to A4 Output Lower address bus used for external memory expansion P110 to P113 A5 to A12 P100/RTP0 to P107/RTP7 P34/TO0 P35/TO1 P36/TI4/TO4 A16 to A21 Output Higher address bus used for external memory expansion P60 to P65...
Page 44 CHAPTER 2 PIN FUNCTIONS (2/2) Pin Name PULL Function Alternate Function SCK1 Serial clock I/O (3-wire type) for CSI0 to CSI2 P15/ASCK0 SCK2 Note 1 Serial clock I/O for I P12/SCK0 Note 1 Serial transmit/receive data I/O for I P10/SI0 Note 1 Input Serial receive data input (3-wire type) for CSI0 to CSI2...
Page 45: Pin States
CHAPTER 2 PIN FUNCTIONS 2.2 Pin States The operating states of various pins are described below with reference to their operating modes. Table 2-2. Operating States of Pins in Each Operating Mode Operating State Note 1 Reset HALT Mode/ IDLE Mode/ Bus Hold Bus Cycle Note 2...
Page 46: Description Of Pin Functions
CHAPTER 2 PIN FUNCTIONS 2.3 Description of Pin Functions (1) P00 to P07 (Port 0) ··· 3-state I/O P00 to P07 constitute an 8-bit I/O port that can be set to input or output in 1-bit units. P00 to P07 can also function as an NMI input, external interrupt request inputs, external trigger for the A/D converter, and external trigger for the real-time output port.
Page 47 CHAPTER 2 PIN FUNCTIONS (2) P10 to P15 (Port 1) ··· 3-state I/O P10 to P15 constitute a 6-bit I/O port that can be set to input or output in 1-bit units. P10 to P15 can also function as input or output pins for the serial interface. P10 to P12, P14, and P15 can be selected as normal output or N-ch open-drain output.
Page 48 CHAPTER 2 PIN FUNCTIONS (3) P20 to P27 (Port 2) ··· 3-state I/O P20 to P27 constitute an 8-bit I/O port that can be set to input or output in 1-bit units. P20 to P27 can also function as input or output pins for the serial interface, and input or output pins for the timer/counter.
Page 49 CHAPTER 2 PIN FUNCTIONS (4) P30 to P37 (Port 3) ··· 3-state I/O P30 to P37 constitute an 8-bit I/O port that can be set to input or output in 1-bit units. P30 to P37 can also function as input or output pins for the timer/counter, and an address bus (A13 to A15) when memory is expanded externally.
Page 50 CHAPTER 2 PIN FUNCTIONS (5) P40 to P47 (Port 4) ··· 3-state I/O P40 to P47 constitute an 8-bit I/O port that can be set to input or output pins in 1-bit units. P40 to P47 can also function as a time division address/data bus (AD0 to AD7) when memory is expanded externally.
Page 51 CHAPTER 2 PIN FUNCTIONS (7) P60 to P65 (Port 6) ··· 3-state I/O P60 to P65 constitute a 6-bit I/O port that can be set to input or output in 1-bit units. P60 to P65 can also function as an address bus (A16 to A21) when memory is expanded externally. When the port 6 is accessed in 8-bit units, the higher 2 bits of port 6 are ignored when they are written to and 00 is read when they are read.
Page 52 CHAPTER 2 PIN FUNCTIONS (9) P90 to P96 (Port 9) ··· 3-state I/O P90 to P96 constitute a 7-bit I/O port that can be set to input or output pins in 1-bit units. P90 to P96 can also function as control signal output pins and bus hold control signal output pins when memory is expanded externally.
Page 53 (vii) HLDRQ (Hold request) ··· input This is an input pin by which an external device requests the V850/SA1 to release the address bus, data bus, and control bus. This pin accepts asynchronous input for CLKOUT. When this pin is active, the address bus, data bus, and control bus are set to high impedance status.
Page 54 CHAPTER 2 PIN FUNCTIONS (10) P100 to P107 (Port 10) ··· 3-state I/O P100 to P107 constitute an 8-bit I/O port that can be set to input or output in 1-bit units. P100 to P107 can also function as a real-time output port and an address bus (A5 to A12) when memory is expanded externally.
Page 55 CHAPTER 2 PIN FUNCTIONS (12) P120 (Port 12) ··· 3-state I/O P120 is a 1-bit I/O port that can be set to input or output in 1-bit units. P120 can also function as a control signal (WAIT) pin when a wait is inserted in the bus cycle. Port function P120 can be set to input or output using the port 12 mode register (PM12).
Page 56 CHAPTER 2 PIN FUNCTIONS (22) V (Power supply) This is the positive power supply pin. All V pins should be connected to a positive power source. (23) V (Ground) This is the ground pin. All V pins should be grounded. (24) V (Programming power supply) This is the positive power supply pin used for flash memory programming mode.
Page 57: Pin I/O Circuits And Recommended Connection Of Unused Pins
CHAPTER 2 PIN FUNCTIONS 2.4 Pin I/O Circuits and Recommended Connection of Unused Pins (1/2) Alternate Function I/O Circuit Type Recommended Connection Method Input: Independently connect to V or V via a resistor. Output: Leave open. P01 to P04 INTP0 to INTP3 INTP4/ADTRG INTP5/RTPTRG INTP6...
Page 58 CHAPTER 2 PIN FUNCTIONS (2/2) Alternate Function I/O Circuit Type Recommended Connection Method P100 to P107 RTP0/A5 to RTP7/A12 Input: Independently connect to V or V via a resistor. Output: Leave open. P110 to P113 A1 to A4 P114 16-A Connect to V P120 WAIT...
Page 59: Pin I/O Circuits
CHAPTER 2 PIN FUNCTIONS 2.5 Pin I/O Circuits (1/2) Type 2 Type 5-A Pullup P-ch enable Data P-ch IN/OUT Output N-ch disable Schmitt-triggered input with hysteresis characteristics Input enable Type 4 Type 8-A pullup Data P-ch enable P-ch Data P-ch Output N-ch disable...
Page 60 CHAPTER 2 PIN FUNCTIONS (2/2) Type 10-A Type 26 Pullup Pullup P-ch P-ch enable enable Data Data P-ch P-ch IN/OUT IN/OUT Open drain Open drain N-ch Output N-ch Output disable disable Type 16-A User’s Manual U12768EJ4V1UD...
Page 61: Chapter 3 Cpu Functions
CHAPTER 3 CPU FUNCTIONS The CPU of the V850/SA1 is based on RISC architecture and executes most instructions in one clock cycle by using a 5-stage pipeline. 3.1 Features • Minimum instruction execution time: 50 ns (@ internal 20 MHz operation) 58.8 ns (@ internal 17 MHz operation)
Page 62: Cpu Register Set
3.2 CPU Register Set The CPU registers of the V850/SA1 can be classified into two categories: a general-purpose program register set and a dedicated system register set. All the registers have a 32 bits width. For details, refer to V850 Series Architecture User’s Manual.
Page 63: Program Register Set
CHAPTER 3 CPU FUNCTIONS 3.2.1 Program register set The program register set includes general-purpose registers and a program counter. (1) General-purpose registers Thirty-two general-purpose registers, r0 to r31, are available. Any of these registers can be used as a data variable or address variable.
Page 64: System Register Set
CHAPTER 3 CPU FUNCTIONS 3.2.2 System register set System registers control the status of the CPU and hold interrupt information. Table 3-2. System Register Numbers System Register Name Usage Operation EIPC Interrupt status saving registers These registers save the PC and PSW when an exception or interrupt occurs.
Page 65 CHAPTER 3 CPU FUNCTIONS (2) Program status word (PSW) (1/2) After reset: 00000020H ID SAT CY Reserved field (fixed to 0). Non-maskable interrupt (NMI) servicing status NMI servicing not under execution. NMI servicing under execution. This flag is set (1) when an NMI is acknowledged, and disables multiple interrupts.
Page 66 CHAPTER 3 CPU FUNCTIONS (2/2) Note Saturation detection of operation result of saturation operation instruction Not saturated. This flag is not cleared (0) if the result of saturated operation instruction execution is not saturated while this flag is set (1). To clear (0) this flag, write the PSW directly.
Page 67: Operation Modes
CHAPTER 3 CPU FUNCTIONS 3.3 Operation Modes The V850/SA1 has the following operation modes. (1) Normal operation mode (single-chip mode) After the system has been released from the reset status, the pins related to the bus interface are set to port mode, execution branches to the reset entry address of the internal ROM, and instruction processing written in the internal ROM is started.
Page 68: Address Space
3.4 Address Space 3.4.1 CPU address space The CPU of the V850/SA1 is of 32-bit architecture and supports up to 4 GB of linear address space (data space) during operand addressing (data access). When referencing instruction addresses, linear address space (program space) of up to 16 MB is supported (physical address space: 4 MB).
Page 69: Image
CHAPTER 3 CPU FUNCTIONS 3.4.2 Image The CPU supports 4 GB of “virtual” addressing space, or 256 memory blocks, each containing 16 MB memory locations. In actuality, the same 16 MB block is accessed regardless of the values of bits 31 to 24 of the CPU address.
Page 70: Wraparound Of Cpu Address Space
CHAPTER 3 CPU FUNCTIONS 3.4.3 Wraparound of CPU address space (1) Program space Of the 32 bits of the PC (program counter), the higher 8 bits are fixed to 0, and only the lower 24 bits are valid. Even if a carry or borrow occurs from bit 23 to bit 24 as a result of branch address calculation, the higher 8 bits ignore the carry or borrow and remain 0.
Page 71: Memory Map
CHAPTER 3 CPU FUNCTIONS 3.4.4 Memory map The V850/SA1 reserves areas as shown below. Figure 3-6. Memory Map Single-chip mode Single-chip mode (external expansion mode) xxFFFFFFH On-chip peripheral On-chip peripheral 4 KB I/O area I/O area xxFFF000H xxFFEFFFH 12 KB...
Page 72: Area
CHAPTER 3 CPU FUNCTIONS 3.4.5 Area (1) Internal ROM/internal flash memory area An area of 1 MB maximum is reserved for the internal ROM/internal flash memory area. (a) Memory map µ <1> PD703014A, 703014AY, 703014B, 703014BY 64 KB is provided at addresses xx000000H to xx00FFFFH. Addresses xx010000H to xx0FFFFFH are access-prohibited area.
Page 73: Internal Rom/Internal Flash Memory Area (256 Kb)
CHAPTER 3 CPU FUNCTIONS µ <3> PD703017A, 703017AY, 70F3017A, 70F3017AY 256 KB is provided at addresses xx000000H to xx03FFFFH. Addresses xx040000H to xx0FFFFFH are access-prohibited area. Figure 3-9. Internal ROM/Internal Flash Memory Area (256 KB) xx0FFFFFH Access-prohibited area xx040000H xx03FFFFH Internal ROM/ internal flash memory xx000000H...
Page 74 CHAPTER 3 CPU FUNCTIONS (b) Interrupt/exception table The V850/SA1 increases the interrupt response speed by assigning handler addresses corresponding to interrupts/exceptions. The collection of these handler addresses is called an interrupt/exception table, which is located in the internal ROM/on-chip flash memory area. When an interrupt/exception request is granted, execution jumps to the handler address, and the program written at that memory address is executed.
Page 75: Internal Ram Area (4 Kb)
CHAPTER 3 CPU FUNCTIONS (2) Internal RAM area Up to 12 KB is reserved for the internal RAM area. µ PD703014A, 703014AY, 703014B, 703014BY, 703015A, 703015AY, 703015B, 703015BY, 70F3015B, 70F3015BY 4 KB is provided at addresses xxFFE000H to xxFFEFFFH. Addresses xxFFC000H to xxFFDFFFH are access-prohibited area. Figure 3-10.
Page 76: On-Chip Peripheral I/O Area
A 4 KB area of addresses FFF000H to FFFFFFH is reserved as an on-chip peripheral I/O area. The V850/SA1 is provided with a 1 KB area of addresses FFF000H to FFF3FFH as a physical on-chip peripheral I/O area, and its image can be seen on the rest of the area (FFF400H to FFFFFFH).
Page 77: External Memory Area (When Expanded To 64 Kb, 256 Kb, Or 1 Mb)
CHAPTER 3 CPU FUNCTIONS (4) External memory area The V850/SA1 can use an area of up to 16 MB (xx100000H to xxFFBFFFH) for external memory accesses (in single-chip mode: during external expansion). 64 KB, 256 KB, 1 MB, or 4 MB of physical external memory can be allocated when the external expansion mode is specified.
Page 78: External Memory Area (When Expanded To 4 Mb)
CHAPTER 3 CPU FUNCTIONS Figure 3-14. External Memory Area (When Expanded to 4 MB) xxFFFFFFH On-chip peripheral I/O Internal RAM xxFFBFFFH Image xxC00000H Physical external memory xxBFFFFFH 3FFFFFH Image External memory xx800000H xx7FFFFFH 000000H Image xx400000H xx3FFFFFH Image xx100000H xx0FFFFFH Internal ROM xx000000H User’s Manual U12768EJ4V1UD...
Page 79: External Expansion Mode
3.4.6 External expansion mode The V850/SA1 allows external devices to be connected to the external memory space by using the pins of ports 4, 5, 6, and 9. To connect an external device, the port pins must be set to the external expansion mode by using the memory expansion mode register (MM).
Page 80 CHAPTER 3 CPU FUNCTIONS (2) Memory address output mode register (MAM) This register sets the mode of each pin of ports 3, 10, and 11. Separate output can be set for the address bus (A1 to A15) in the external expansion mode. Separate bus output is output to P34 to P36, P100 to P107, and P110 to P113.
Page 81: Recommended Use Of Address Space
8 MB address spaces 00000000H to 007FFFFFH and FF800000H to FFFFFFFFH of the 4 GB CPU are used as the data space. With the V850/SA1, the 16 MB physical address space is seen as 256 images in the 4 GB CPU address space.
Page 82: Recommended Memory Map
CHAPTER 3 CPU FUNCTIONS Figure 3-16. Recommended Memory Map Program space Data space FFFFFFFFH On-chip peripheral I/O area FFFFF400H FFFFF3FFH FFFFF000H FFFFEFFFH Internal xxFFFFFFH RAM area On-chip peripheral I/O area FFFFC000H xxFFF400H FFFFBFFFH xxFFF3FFH External xxFFF000H memory area xxFFEFFFH FF800000H Internal FF7FFFFFH RAM area...
Page 83: Peripheral I/O Registers
CHAPTER 3 CPU FUNCTIONS 3.4.8 Peripheral I/O registers (1/5) Bit Units for Manipulation After Reset Address Function Register Name Symbol 1 Bit 8 Bits 16 Bits √ √ Note FFFFF000H Port 0 √ √ Note FFFFF002H Port 1 √ √ Note FFFFF004H Port 2...
Page 84 CHAPTER 3 CPU FUNCTIONS (2/5) Bit Units for Manipulation After Reset Address Function Register Name Symbol 1 Bit 8 Bits 16 Bits √ √ FFFFF084H Pull-up resistor option register 2 √ √ FFFFF086H Pull-up resistor option register 3 √ √ FFFFF094H Pull-up resistor option register 10 PU10...
Page 85 CHAPTER 3 CPU FUNCTIONS (3/5) Bit Units for Manipulation After Reset Address Function Register Name Symbol 1 Bit 8 Bits 16 Bits √ √ FFFFF136H Interrupt control register DMAIC1 √ √ FFFFF138H Interrupt control register DMAIC2 √ √ FFFFF13AH Interrupt control register WTIC √...
Page 86 CHAPTER 3 CPU FUNCTIONS (4/5) Bit Units for Manipulation After Reset Address Function Register Name Symbol 1 Bit 8 Bits 16 Bits √ FFFFF21EH Prescaler mode register 11 PRM11 √ FFFFF240H 8-bit counter 2 √ FFFFF242H 8-bit compare register 2 CR20 √...
Page 87 CHAPTER 3 CPU FUNCTIONS (5/5) Bit Units for Manipulation After Reset Address Function Register Name Symbol 1 Bit 8 Bits 16 Bits √ √ FFFFF2C4H Serial clock select register 2 CSIS2 √ √ FFFFF300H Asynchronous serial interface mode register 0 ASIM0 √...
Page 88: Specific Registers
The write access of these specific registers is executed in a specific sequence, and if abnormal write operations occur, it is checked by the PRERR bit of the system status register (SYS). The V850/SA1 has three specific registers, the power save control register (PSC), processor clock control register (PCC), and flash programming mode control register (FLPMC).
Page 89 CHAPTER 3 CPU FUNCTIONS Cautions 2. Always stop the DMA prior to accessing specific registers. When data is set to the PSC register in order to set the IDLE mode or software STOP mode, a dummy instruction must be inserted so that the routine after releasing the IDLE/software STOP mode is executed correctly.
Page 90 CHAPTER 3 CPU FUNCTIONS (1) Command register (PRCMD) The command register (PRCMD) is a register used when write-accessing a specific register to prevent incorrect writing to the specific register due to the erroneous program execution. This register can be written in 8-bit units. It becomes undefined in a read cycle. Occurrence of illegal write operations can be checked by the PRERR bit of the SYS register.
Page 91: Chapter 4 Bus Control Function
CHAPTER 4 BUS CONTROL FUNCTION The V850/SA1 is provided with an external bus interface function by which external memories such as ROM and RAM, and I/O can be connected. 4.1 Features • Address bus (capable of separate output) • 16-bit data bus •...
Page 92: Control Register
CHAPTER 4 BUS CONTROL FUNCTION 4.2.2 Control register (1) System control register (SYC) This register switches the control signals for bus interface. The system control register can be read/written in 8-bit or 1-bit units. After reset: 00H Address: FFFFF064H Symbol Bus Interface Control DSTB, R/W, LBEN, UBEN signal output Note...
Page 93: Bus Width
CHAPTER 4 BUS CONTROL FUNCTION 4.3.2 Bus width The CPU carries out peripheral I/O access and external memory access in 8-bit, 16-bit, or 32-bit units. The following shows the operation for each access. (1) Byte access (8 bits) Byte access is divided into two types, access to even addresses and access to odd addresses. Figure 4-1.
Page 94: Memory Block Function
CHAPTER 4 BUS CONTROL FUNCTION 4.4 Memory Block Function The 16 MB memory space is divided into memory blocks of 1 MB units. The programmable wait function and bus cycle operation mode can be independently controlled for every two memory blocks. Figure 4-4.
Page 95: Wait Function
CHAPTER 4 BUS CONTROL FUNCTION 4.5 Wait Function 4.5.1 Programmable wait function To facilitate interfacing with low-speed memories and I/O devices, up to 3 data waits can be inserted in a bus cycle that starts every two memory blocks. The number of waits can be programmed by using the data wait control register (DWC). Immediately after the system has been reset, a state in which three data waits are inserted is automatically programmed for all memory blocks.
Page 96: External Wait Function
CHAPTER 4 BUS CONTROL FUNCTION 4.5.2 External wait function When an extremely slow device, I/O, or asynchronous system is connected, any number of wait states can be inserted in a bus cycle by sampling the external wait pin (WAIT) to synchronize with the external device. The external wait signal is data wait only, and does not affect the access times of the internal ROM, internal RAM, and on-chip peripheral I/O areas, similar to programmable wait.
Page 97: Idle State Insertion Function
CHAPTER 4 BUS CONTROL FUNCTION 4.6 Idle State Insertion Function To facilitate interfacing with low-speed memory devices and meeting the data output float delay time on memory read accesses every two blocks, one idle state (TI) can be inserted into the current bus cycle after the T3 state. The following bus cycle starts after one idle state.
Page 98: Bus Hold Function
CHAPTER 4 BUS CONTROL FUNCTION 4.7 Bus Hold Function 4.7.1 Outline of function When the MM3 bit of the memory expansion mode register (MM) is set (1), the HLDRQ and HLDAK pin functions of P95 and P96 become valid. When the HLDRQ pin becomes active (low) indicating that another bus master is requesting acquisition of the bus, Note the external address/data bus and strobe pins go into a high-impedance state , and the bus is released (bus hold...
Page 99: Bus Hold Procedure
CHAPTER 4 BUS CONTROL FUNCTION 4.7.2 Bus hold procedure The procedure of the bus hold function is illustrated below. Figure 4-7. Bus Hold Procedure <1>HLDRQ = 0 acknowledged Normal status <2>All bus cycle start requests held pending <3>End of current bus cycle <4>Bus idle status <5>HLDAK = 0 Bus hold status...
Page 100: Bus Timing
CHAPTER 4 BUS CONTROL FUNCTION 4.8 Bus Timing The V850/SA1 can execute read/write control for an external device using the following two modes. • Mode using DSTB, R/W, LBEN, UBEN, and ASTB signals • Mode using RD, WRL, WRH, and ASTB signals Set these modes by using the BIC bit of the system control register (SYC) (refer to 4.2.2 (1) System control...
Page 101 CHAPTER 4 BUS CONTROL FUNCTION Figure 4-8. Memory Read (2/4) (b) 1 wait CLKOUT (output) Address A16 to A21 (output) Address A1 to A15 (output) AD0 to AD15 Address Data (I/O) ASTB (output) R/W (output) WRH, WRL (output) DSTB, RD (output) UBEN, LBEN (output) WAIT (input) Remarks 1.
Page 102 CHAPTER 4 BUS CONTROL FUNCTION Figure 4-8. Memory Read (3/4) (c) 0 waits, idle state CLKOUT (output) Address A16 to A21 (output) Address A1 to A15 (output) AD0 to AD15 Address Data (I/O) ASTB (output) R/W (output) WRH, WRL (output) DSTB, RD (output) UBEN, LBEN (output) WAIT (input)
Page 103 CHAPTER 4 BUS CONTROL FUNCTION Figure 4-8. Memory Read (4/4) (d) 1 wait, idle state CLKOUT (output) Address A16 to A21 (output) Address A1 to A15 (output) AD0 to AD15 Address Data (I/O) ASTB (output) R/W (output) WRH, WRL (output) DSTB, RD (output) UBEN, LBEN (output) WAIT (input)
Page 104: Memory Write
CHAPTER 4 BUS CONTROL FUNCTION Figure 4-9. Memory Write (1/2) (a) 0 waits CLKOUT (output) A16 to A21 (output) Address A1 to A15 (output) Address AD0 to AD15 Note Address Data (I/O) ASTB (output) R/W (output) RD (output) DSTB (output) WRH, WRL (output) UBEN, LBEN (output) WAIT (input)
Page 105 CHAPTER 4 BUS CONTROL FUNCTION Figure 4-9. Memory Write (2/2) (b) 1 wait CLKOUT (output) A16 to A21 (output) Address A1 to A15 (output) Address AD0 to AD15 Note Address Data (I/O) ASTB (output) R/W (output) RD (output) DSTB (output) WRH, WRL (output) UBEN, LBEN (output) WAIT (input)
Page 106: Bus Hold Timing
CHAPTER 4 BUS CONTROL FUNCTION Figure 4-10. Bus Hold Timing CLKOUT (output) HLDRQ (input) Note 1 HLDAK (output) A16 to A21 (output) Address Address A1 to A15 (output) Address Address AD0 to AD15 Undefined Address Address Data (I/O) ASTB (output) Note 2 R/W (output) DSTB, RD,...
Page 107: Bus Priority
CHAPTER 4 BUS CONTROL FUNCTION 4.9 Bus Priority There are four external bus cycles: bus hold, memory access, instruction fetch (branch), and instruction fetch (continuous). The bus hold cycle is given the highest priority, followed by memory access, instruction fetch (branch), and instruction fetch (continuous) in that order.
Page 108: Chapter 5 Interrupt/Exception Processing Function
CHAPTER 5 INTERRUPT/EXCEPTION PROCESSING FUNCTION 5.1 Outline The V850/SA1 is provided with a dedicated interrupt controller (INTC) for interrupt servicing and realizes a high- powered interrupt function that can service interrupt requests from a total of 30 sources. An interrupt is an event that occurs independently of program execution, and an exception is an event that is dependent on program execution.
Page 109 CHAPTER 5 INTERRUPT/EXCEPTION PROCESSING FUNCTION Table 5-1. Interrupt Source List (1/2) Interrupt Classifi- Default Interrupt Exception Handler Restored Type Name Trigger Control cation Priority Source Code Address Register − − − Reset Interrupt RESET Reset input 0000H 00000000H Undefined − −...
Page 110 CHAPTER 5 INTERRUPT/EXCEPTION PROCESSING FUNCTION Table 5-1. Interrupt Source List (2/2) Interrupt Classifi- Default Interrupt Exception Handler Restored Type Name Trigger Control cation Priority Source Code Address Register Maskable Interrupt INTSER1 UART1 serial error UART1 01E0H 000001E0H nextPC SERIC1 INTSR1 UART1 receive end UART1 01F0H...
Page 111: Non-Maskable Interrupts
Non-maskable interrupt requests are acknowledged unconditionally, even in the interrupt disabled (DI) status. NMI requests are not subject to priority control and take precedence over all the other interrupts. The V850/SA1 includes the following two non-maskable interrupt requests. • NMI pin input (NMI) •...
Page 112: Operation
CHAPTER 5 INTERRUPT/EXCEPTION PROCESSING FUNCTION 5.2.1 Operation If a non-maskable interrupt request is generated, the CPU performs the following processing, and transfers control to the handler routine. <1> Saves the restored PC to FEPC. <2> Saves the current PSW to FEPSW. <3>...
Page 113: Acknowledging Non-Maskable Interrupt Request
CHAPTER 5 INTERRUPT/EXCEPTION PROCESSING FUNCTION Figure 5-2. Acknowledging Non-Maskable Interrupt Request (a) If a new NMI request is generated while an NMI service routine is being executed Main routine (PSW. NP = 1) NMI request NMI request NMI request held pending because PSW. NP = 1 Pending NMI request processed (b) If a new NMI request is generated twice while an NMI service routine is being executed Main routine...
Page 114: Restore
CHAPTER 5 INTERRUPT/EXCEPTION PROCESSING FUNCTION 5.2.2 Restore Execution is restored from non-maskable interrupt servicing by the RETI instruction. Operation of RETI instruction When the RETI instruction is executed, the CPU performs the following processing, and transfers control to the address of the restored PC. (1) Restores the values of the PC and PSW from FEPC and FEPSW, respectively, because the EP bit of PSW is 0 and the NP bit of PSW is 1.
Page 115: Np Flag
CHAPTER 5 INTERRUPT/EXCEPTION PROCESSING FUNCTION 5.2.3 NP flag The NP flag is a status flag that indicates that non-maskable interrupt (NMI) servicing is under execution. This flag is set when an NMI interrupt request has been acknowledged, and masks all interrupt requests to prohibit multiple interrupts from being acknowledged.
Page 116: Edge Detection Function Of External Interrupt Request Input Pin
CHAPTER 5 INTERRUPT/EXCEPTION PROCESSING FUNCTION 5.2.5 Edge detection function of external interrupt request input pin The NMI pin valid edge can be selected from the following four types: falling edge, rising edge, both edges, or neither edge. Rsing edge specification register 0 (EGP0) and falling edge specification register 0 (EGN0) specify the valid edge of the external interrupt.
Page 117: Maskable Interrupts
5.3 Maskable Interrupts Maskable interrupt requests can be masked by interrupt control registers. The V850/SA1 has 30 maskable interrupt sources (refer to 5.1.1 Features). If two or more maskable interrupt requests are generated at the same time, they are acknowledged according to the default priority.
Page 118: Maskable Interrupt Servicing
CHAPTER 5 INTERRUPT/EXCEPTION PROCESSING FUNCTION Figure 5-5. Maskable Interrupt Servicing INT input Mask? PSW. ID = 0 Interrupt enable mode? Priority higher than INTC acknowledged that of interrupt currently serviced? Priority higher than that of other interrupt request? Highest default priority of interrupt requests with the same priority? Maskable interrupt request...
Page 119: Restore
CHAPTER 5 INTERRUPT/EXCEPTION PROCESSING FUNCTION 5.3.2 Restore To restore execution from maskable interrupt servicing, the RETI instruction is used. Operation of RETI instruction When the RETI instruction is executed, the CPU performs the following steps, and transfers control to the address of the restored PC.
Page 120: Priorities Of Maskable Interrupts
CHAPTER 5 INTERRUPT/EXCEPTION PROCESSING FUNCTION 5.3.3 Priorities of maskable interrupts The V850/SA1 provides multiple interrupt servicing in which an interrupt is acknowledged while another interrupt is being serviced. Multiple interrupts can be controlled by priority levels. There are two types of priority level control: control based on the default priority levels, and control based on the programmable priority levels which are specified by the interrupt priority level specification bit (xxPRn).
Page 121: Example Of Multiple Interrupt Servicing
CHAPTER 5 INTERRUPT/EXCEPTION PROCESSING FUNCTION Figure 5-7. Example of Multiple Interrupt Servicing (1/2) Main routine Servicing of a Servicing of b Interrupt Interrupt request a request b Interrupt request b is acknowledged because the priority of (level 3) (level 2) b is higher than that of a and interrupts are enabled.
Page 122 CHAPTER 5 INTERRUPT/EXCEPTION PROCESSING FUNCTION Figure 5-7. Example of Multiple Interrupt Servicing (2/2) Main routine Servicing of i Servicing of k Interrupt request j Interrupt request i (level 3) (level 2) Interrupt request j is held pending because its Interrupt request k priority is lower than that of i.
Page 123: Example Of Servicing Interrupt Requests Generated Simultaneously
CHAPTER 5 INTERRUPT/EXCEPTION PROCESSING FUNCTION Figure 5-8. Example of Servicing Interrupt Requests Generated Simultaneously Main routine Interrupt request a (level 2) Note 1 Interrupt request b (level 1) Interrupt requests b and c are Servicing of interrupt request b • Note 2 Interrupt request c (level 1) acknowledged first according to their...
Page 124: Interrupt Control Register (Xxicn)
CHAPTER 5 INTERRUPT/EXCEPTION PROCESSING FUNCTION 5.3.4 Interrupt control register (xxICn) An interrupt control register is assigned to each maskable interrupt and sets the control conditions for each maskable interrupt request. The interrupt control register can be read/written in 8-bit or 1-bit units. Cautions 1.
Page 125 CHAPTER 5 INTERRUPT/EXCEPTION PROCESSING FUNCTION After reset: 47H Address: FFFFF100H to FFFFF13AH Symbol xxICn xxIFn xxMKn xxPRn2 xxPRn1 xxPRn0 Note xxIFn Interrupt Request Flag Interrupt request not generated Interrupt request generated xxMKn Interrupt Mask Flag Interrupt servicing enabled Interrupt servicing disabled (pending) xxPRn2 xxPRn1 xxPRn0...
Page 126 CHAPTER 5 INTERRUPT/EXCEPTION PROCESSING FUNCTION Table 5-2. Interrupt Control Register (xxICn) Address Register FFFFF100H WDTIC WDTIF WDTMK WDTPR2 WDTPR1 WDTPR0 FFFFF102H PIC0 PIF0 PMK0 PPR02 PPR01 PPR00 FFFFF104H PIC1 PIF1 PMK1 PPR12 PPR11 PPR10 FFFFF106H PIC2 PIF2 PMK2 PPR22 PPR21 PPR20 FFFFF108H PIC3...
Page 127: In-Service Priority Register (Ispr)
CHAPTER 5 INTERRUPT/EXCEPTION PROCESSING FUNCTION 5.3.5 In-service priority register (ISPR) This register holds the priority level of the maskable interrupt currently acknowledged. When an interrupt request is acknowledged, the bit of this register corresponding to the priority level of that interrupt is set to 1 and remains set while the interrupt is serviced.
Page 128: Id Flag
CHAPTER 5 INTERRUPT/EXCEPTION PROCESSING FUNCTION 5.3.6 ID flag The interrupt disable status flag (ID) of the PSW controls the enabling and disabling of maskable interrupt requests. As a status flag, it also displays the current maskable interrupt acknowledgment status. Figure 5-9. Interrupt Disable Flag (ID) After reset: 00000020H Symbol NP EP ID SAT CY OV...
Page 129: Software Exceptions
CHAPTER 5 INTERRUPT/EXCEPTION PROCESSING FUNCTION 5.4 Software Exceptions A software exception is generated when the CPU executes the TRAP instruction, and can be always acknowledged. • TRAP instruction format: TRAP vector (where vector is 0 to 1FH) For details of the instruction function, refer to the V850 Series Architecture User’s Manual. 5.4.1 Operation If a software exception occurs, the CPU performs the following processing, and transfers control to the handler routine.
Page 130: Restore
CHAPTER 5 INTERRUPT/EXCEPTION PROCESSING FUNCTION 5.4.2 Restore To restore or return execution from the software exception service routine, the RETI instruction is used. Operation of RETI instruction When the RETI instruction is executed, the CPU performs the following steps, and transfers control to the address of the restored PC.
Page 131: Ep Flag
The exception trap is an interrupt that is requested when illegal execution of an instruction takes place. In the V850/SA1, an illegal opcode exception (ILGOP: Illegal Opcode Trap) is considered as an exception trap. • Illegal opcode exception: Occurs if the sub opcode field of the instruction to be executed next is not a valid opcode.
Page 132: Operation
CHAPTER 5 INTERRUPT/EXCEPTION PROCESSING FUNCTION 5.5.2 Operation If an exception trap occurs, the CPU performs the following processing, and transfers control to the handler routine. (1) Saves the restored PC to EIPC. (2) Saves the current PSW to EIPSW. (3) Writes an exception code (0060H) to the lower 16 bits (EICC) of ECR. (4) Sets the EP and ID bits of the PSW.
Page 133: Restore
CHAPTER 5 INTERRUPT/EXCEPTION PROCESSING FUNCTION 5.5.3 Restore To restore or return execution from the exception trap, the RETI instruction is used. Operation of RETI instruction When the RETI instruction is executed, the CPU performs the following processing, and transfers control to the address of the restored PC.
Page 134: Priority Control
CHAPTER 5 INTERRUPT/EXCEPTION PROCESSING FUNCTION 5.6 Priority Control 5.6.1 Priorities of interrupts and exceptions Table 5-3. Priorities of Interrupts and Exceptions RESET TRAP ILGOP RESET × ← ← ← × ↑ ← ← × ↑ ↑ ← TRAP × ↑ ↑...
Page 135 CHAPTER 5 INTERRUPT/EXCEPTION PROCESSING FUNCTION (1) To acknowledge maskable interrupts in service program Service program of maskable interrupt or exception • Save EIPC to memory or register • Save EIPSW to memory or register • EI instruction (enables interrupt acknowledgement) ←...
Page 136 CHAPTER 5 INTERRUPT/EXCEPTION PROCESSING FUNCTION Priorities of maskable interrupts (High) Level 0 > Level 1 > Level 2 > Level 3 > Level 4 > Level 5 > Level 6 > Level 7 (Low) Interrupt servicing that has been suspended as a result of multiple interrupt servicing is resumed after the interrupt servicing of the higher priority has been completed and the RETI instruction has been executed.
Page 137: Interrupt Latency Time
CHAPTER 5 INTERRUPT/EXCEPTION PROCESSING FUNCTION 5.7 Interrupt Latency Time The following table describes the V850/SA1 interrupt latency time (from interrupt request generation to start of interrupt servicing). Figure 5-16. Pipeline Operation at Interrupt Request Acknowledgement 7 to 14 system clocks...
Page 138: Interrupt Request Valid Timing After Ei Instruction
CHAPTER 5 INTERRUPT/EXCEPTION PROCESSING FUNCTION 5.8.1 Interrupt request valid timing after EI instruction When an interrupt request signal is generated (IF flag = 1) in the status in which the DI instruction is executed (interrupts disabled) and interrupts are not masked (MK flag = 0), seven system clocks are required from the execution of the EI instruction (interrupts enabled) to the interrupt request acknowledgement by the CPU.
Page 139: Interrupt Control Register Bit Manipulation Instructions During Dma Transfer
CHAPTER 5 INTERRUPT/EXCEPTION PROCESSING FUNCTION Figure 5-17. Pipeline Flow and Interrupt Request Signal Generation Timing (a) When DI instruction is executed at eighth clock after EI instruction execution (interrupt request is acknowledged) ei signal intrq signal intrq signal is generated (b) When DI instruction is executed at seventh clock after EI instruction execution (interrupt request is not acknowledged) ei signal...
Page 140: Chapter 6 Clock Generation Function
CHAPTER 6 CLOCK GENERATION FUNCTION 6.1 General The clock generator is a circuit that generates the clock pulses that are supplied to the CPU and peripheral hardware. There are two types of clock oscillators. (1) Main clock oscillator This oscillator has an oscillation frequency of 2 to 20 MHz. Oscillation can be stopped by setting the software STOP mode or by setting the processor clock control register (PCC).
Page 141: Configuration
CHAPTER 6 CLOCK GENERATION FUNCTION 6.2 Configuration Figure 6-1. Clock Generator Subclock XT1/P114 Clock supplied to oscillator watch timer, etc. IDLE MFRC IDLE control CK2 to CK0 Main clock IDLE Prescaler HALT oscillator control /2 f /4 f HALT CPU clock control STP, Clock supplied to...
Page 142: Control Registers
CHAPTER 6 CLOCK GENERATION FUNCTION 6.3.1 Control registers (1) Processor clock control register (PCC) This is a specific register. It can be written to only when a specified combination of sequences is used (see 3.4.9 Specific registers). This register can be read/written in 8-bit or 1-bit units. After reset: Address: FFFFF074H MFRC...
Page 143 CHAPTER 6 CLOCK GENERATION FUNCTION (a) Example of main clock operation → subclock operation setup <1> CK2 ← 1: Bit manipulation instructions are recommended. Do not change CK1 and CK0. <2> Subclock operation: The maximum number of the following instructions is required before subclock operation after the CK2 bit is set.
Page 144 CHAPTER 6 CLOCK GENERATION FUNCTION (2) Power save control register (PSC) This is a specific register. It can be written to only when a specified combination of sequences is used (see 3.4.9 Specific registers). This register can be read/written in 8-bit or 1-bit units. After reset: Address: FFFFF070H DCLK1...
Page 145: Power Save Functions
CHAPTER 6 CLOCK GENERATION FUNCTION (3) Oscillation stabilization time select register (OSTS) This register can be read/written in 8-bit units. After reset: Address: FFFFF380H OSTS OSTS2 OSTS1 OSTS0 OSTS2 OSTS1 OSTS0 Note Selection of Oscillation Stabilization Time µ (819.2 (3.3 ms) (6.6 ms) (13.1 ms) (26.2 ms)
Page 146: Halt Mode
CHAPTER 6 CLOCK GENERATION FUNCTION (3) Software STOP mode This mode stops the entire system by stopping the main clock oscillator. The subclock continues to be supplied to keep on-chip peripheral functions operating. If a subclock is not used, ultra low power consumption mode (current that flows through the on-chip feedback resistor of the subclock oscillator and leakage current only are flowing) is set.
Page 147 CHAPTER 6 CLOCK GENERATION FUNCTION Table 6-1. Operating Statuses in HALT Mode (1/2) HALT Mode Setting When CPU Operates with Main Clock When CPU Operates with Subclock When subclock does When subclock exists When main clock’s When main clock’s Item not exist oscillation continues oscillation is stopped...
Page 148 CHAPTER 6 CLOCK GENERATION FUNCTION Table 6-1. Operating Statuses in HALT Mode (2/2) HALT Mode Setting When CPU Operates with Main Clock When CPU Operates with Subclock When subclock does When subclock exists When main clock’s When main clock’s Item not exist oscillation continues oscillation is stopped...
Page 149: Idle Mode
CHAPTER 6 CLOCK GENERATION FUNCTION 6.4.3 IDLE mode (1) Settings and operating states This mode stops the entire system except the watch timer by stopping the on-chip main clock supply while the clock oscillator is still operating. Supply to the subclock continues. When this mode is released, there is no need for the oscillator to wait for the oscillation stabilization time, so normal operation can be resumed quickly.
Page 150: Software Stop Mode
CHAPTER 6 CLOCK GENERATION FUNCTION Table 6-2. Operating Statuses in IDLE Mode (2/2) IDLE Mode Settings When Subclock Exists When Subclock Does Not Exist Item Port function Held External bus interface Stopped External Operating interrupt INTP0 to INTP3 Operating request INTP4 to INTP6 Stopped AD0 to AD15...
Page 151 CHAPTER 6 CLOCK GENERATION FUNCTION Table 6-3. Operating Statuses in Software STOP Mode Software STOP Mode When Subclock Exists When Subclock Does Not Exist Settings Item Stopped Clock generator Oscillation for main clock is stopped and oscillation for subclock continues Clock supply to CPU and on-chip peripheral functions is stopped 16-bit timer (TM0) Operates when INTWTI is selected for count...
Page 152: Oscillation Stabilization Time
CHAPTER 6 CLOCK GENERATION FUNCTION 6.5 Oscillation Stabilization Time The following shows the methods for specifying the length of the oscillation stabilization time required to stabilize the oscillator following release of software STOP mode. (1) Release non-maskable interrupt or by unmasked interrupt request Software STOP mode is released by a non-maskable interrupt or an unmasked interrupt request.
Page 153: Cautions On Power Save Function
CHAPTER 6 CLOCK GENERATION FUNCTION 6.6 Cautions on Power Save Function (1) While an instruction is being executed on internal ROM To set the power save mode (IDLE mode or software STOP mode) while an instruction is being executed on the internal ROM, insert a NOP instruction as a dummy instruction to correctly execute the routine after releasing the power save mode.
Page 154 CHAPTER 6 CLOCK GENERATION FUNCTION (2) While an instruction is being executed on external ROM (i) Do not set the power save mode (IDLE or software STOP mode) while an instruction is being executed on the external ROM. (ii) To set the power save mode (IDLE or software STOP mode) while an instruction is being executed on the external ROM, handle as follows.
Page 155: Chapter 7 Timer/Counter Function
CHAPTER 7 TIMER/COUNTER FUNCTION 7.1 16-Bit Timers (TM0, TM1) 7.1.1 Outline • 16-bit capture/compare registers: 2 (CRn0, CRn1) • Independent capture/trigger inputs: 2 (TIn0, TIn1) • Support of output of capture/match interrupt request signals (INTTMn0, INTTMn1) • Event input (shared with TIn0) via digital noise eliminator and support of edge specification •...
Page 156: Block Diagram Of Tm0 And Tm1
CHAPTER 7 TIMER/COUNTER FUNCTION Figure 7-1. Block Diagram of TM0 and TM1 Internal bus Capture/compare control CRCn2 CRCn1 CRCn0 register n (CRCn) INTTMn0 16-bit capture/compare Noise Tln1 register n0 (CRn0) eliminator Match Note Count clock 16-bit timer register Clear (TMn) Output controller Match...
Page 157: Configuration
CHAPTER 7 TIMER/COUNTER FUNCTION (6) One-shot pulse output Can output a one-shot pulse with any output pulse width. 7.1.3 Configuration Timers 0 and 1 consist of the following hardware. Table 7-1. Configuration of Timers 0 and 1 Item Configuration 16 bits × 2 (TM0, TM1) Timer registers Capture/compare registers: 16 bits ×...
Page 158 CHAPTER 7 TIMER/COUNTER FUNCTION (2) Capture/compare registers 00, 10 (CR00, CR10) CRn0 is a 16-bit register that functions as a capture register and as a compare register. Whether this register functions as a capture or compare register is specified by using bit 0 (CRCn0) of the CRCn register. (a) When using CRn0 as compare register The value set to CRn0 is always compared with the count value of the TMn register.
Page 159 CHAPTER 7 TIMER/COUNTER FUNCTION (3) Capture/compare registers 01, 11 (CR01, CR11) This is a 16-bit register that can be used as a capture register and a compare register. Whether it is used as a capture register or compare register is specified by bit 2 (CRCn2) of the CRCn register. (a) When using CRn1 as compare register The value set to CRn1 is always compared with the count value of TMn.
Page 160: Timer 0, 1 Control Registers
CHAPTER 7 TIMER/COUNTER FUNCTION 7.1.4 Timer 0, 1 control registers The following four types of registers control timers 0 and 1. • 16-bit timer mode control register n (TMCn) • Capture/compare control register n (CRCn) • 16-bit timer output control register n (TOCn) •...
Page 161 CHAPTER 7 TIMER/COUNTER FUNCTION After reset: 00H Address: FFFFF208H, FFFFF218H TMCn TMCn3 TMCn2 TMCn1 OVFn (n = 0, 1) Operation Mode and Clear TOn Output Timing TMCn3 TMCn2 TMCn1 Generation of Interrupt Mode Selection Selection Operation stops (TMn is Not affected Not generated cleared to 0) Free-running mode...
Page 162 CHAPTER 7 TIMER/COUNTER FUNCTION (2) Capture/compare control registers 0, 1 (CRC0, CRC1) CRCn controls the operation of capture/compare register n (CRn0 and CRn1). CRCn is set by a 1-bit or 8-bit memory manipulation instruction. RESET input clears CRC0 and CRC1 to 00H. After reset: 00H R/W Address: FFFFF20AH, FFFFF21AH CRCn...
Page 163 CHAPTER 7 TIMER/COUNTER FUNCTION (3) 16-bit timer output control registers 0, 1 (TOC0, TOC1) TOCn controls the operation of the timer n output controller by setting or resetting the R-S flip-flop (LV0), enabling or disabling reverse output, enabling or disabling output of timer n, enabling or disabling one-shot pulse output operation, and selecting the output trigger for the one-shot pulse by software.
Page 164 CHAPTER 7 TIMER/COUNTER FUNCTION (4) Prescaler mode registers 0, 01 (PRM0, PRM01) PRM0 and PRM01 select the count clock of the 16-bit timer (TM0) and the valid edge of TI0n input. PRM0 and PRM01 are set by an 8-bit memory manipulation instruction. RESET input clears PRM0 and PRM01 to 00H.
Page 165 CHAPTER 7 TIMER/COUNTER FUNCTION Cautions 1. When selecting the valid edge of TI00 as the count clock, do not specify the valid edge of TI00 to clear and start the timer and as a capture trigger. 2. Before setting data to the PRM0 and PRM01 registers, always stop the timer operation. 3.
Page 166 CHAPTER 7 TIMER/COUNTER FUNCTION (5) Prescaler mode registers 1, 11 (PRM1, PRM11) PRM1 and PRM11 select the count clock of the 16-bit timer (TM1) and the valid edge of TI1n input. PRM1 and PRM11 are set by an 8-bit memory manipulation instruction. RESET input clears PRM1 and PRM11 to 00H.
Page 167 CHAPTER 7 TIMER/COUNTER FUNCTION Cautions 1. When selecting the valid edge of TI10 as the count clock, do not specify the valid edge of TI10 to clear and start the timer and as a capture trigger. 2. Before setting data to the PRM1 and PRM11 registers, always stop the timer operation. 3.
Page 168: 16-Bit Timer Operation
CHAPTER 7 TIMER/COUNTER FUNCTION 7.2 16-Bit Timer Operation 7.2.1 Operation as interval timer (16 bits) TMn operates as an interval timer when 16-bit timer mode control register n (TMCn) and capture/compare control register n (CRCn) are set as shown in Figure 7-2. In this case, TMn repeatedly generates an interrupt at the time interval specified by the count value set in advance to 16-bit capture/compare register n0 (CRn0).
Page 169: Configuration Of Interval Timer
CHAPTER 7 TIMER/COUNTER FUNCTION Figure 7-3. Configuration of Interval Timer 16-bit capture/compare register n0 (CRn0) INTTMn0 Note Count clock 16-bit timer register n (TMn) OVFn Noise TIn0 eliminator Clear circuit fxx/2 Note The count clock is set by the PRMn and PRMn1 registers. Remarks 1.
Page 170: Ppg Output Operation
CHAPTER 7 TIMER/COUNTER FUNCTION 7.2.2 PPG output operation TMn can be used for PPG (Programmable Pulse Generator) output by setting 16-bit timer mode control register n (TMCn) and capture/compare control register n (CRCn) as shown in Figure 7-5. The PPG output function outputs a square wave from the TOn pin at the cycle specified by the count value set in advance to 16-bit capture/compare register n0 (CRn0) and the pulse width specified by the count value set in advance to 16-bit capture/compare register n1 (CRn1).
Page 171: Pulse Width Measurement
CHAPTER 7 TIMER/COUNTER FUNCTION 7.2.3 Pulse width measurement 16-bit timer register n (TMn) can be used to measure the pulse widths of the signals input to the TIn0 and TIn1 pins. Measurement can be carried out with TMn used as a free-running counter or by restarting the timer in synchronization with the edge of the signal input to the TIn0 pin.
Page 172: Configuration For Pulse Width Measurement With Free-Running Counter
CHAPTER 7 TIMER/COUNTER FUNCTION Figure 7-7. Configuration for Pulse Width Measurement with Free-Running Counter Note Count clock 16-bit timer register n (TMn) OVFn 16-bit capture/compare register n1 TIn0 (CRn1) INTTMn1 Internal bus Note The count clock is set by the PRMn and PRMn1 registers. Remarks 1.
Page 173: Control Register Settings For Measurement Of Two Pulse Widths With Free-Running Counter
CHAPTER 7 TIMER/COUNTER FUNCTION (2) Measurement of two pulse widths with free running counter The pulse widths of the two signals respectively input to the TIn0 and TIn1 pins can be measured when 16-bit timer register n (TMn) is used as a free-running counter (refer to Figure 7-9). When the edge specified by bits 4 and 5 (ESn00 and ESn01) of prescaler mode register n (PRMn) is input to the TIn0 pin, the value of TMn is loaded to 16-bit capture/compare register n1 (CRn1) and an external interrupt request signal (INTTMn1) is set.
Page 174: Crn1 Capture Operation With Rising Edge Specified
CHAPTER 7 TIMER/COUNTER FUNCTION • Capture operation (free running mode) The following figure illustrates the operation of the capture register when the capture trigger is input. Figure 7-10. CRn1 Capture Operation with Rising Edge Specified Count clock – – – N + 1 TIn0 Rising edge...
Page 175: Registers
CHAPTER 7 TIMER/COUNTER FUNCTION (3) Pulse width measurement with free running counter and two capture registers When 16-bit timer register n (TMn) is used as a free running counter (refer to Figure 7-19), the pulse width of the signal input to the TIn0 pin can be measured. When the edge specified by bits 4 and 5 (ESn00 and ESn01) of prescaler mode register n (PRMn) is input to the TIn0 pin, the value of TMn is loaded to 16-bit capture/compare register n1 (CRn1), and an external interrupt request signal (INTTMn1) is set.
Page 176: Timing Of Pulse Width Measurement With Free-Running Counter And
CHAPTER 7 TIMER/COUNTER FUNCTION Figure 7-13. Timing of Pulse Width Measurement with Free-Running Counter and Two Capture Registers (with Rising Edge Specified) Count clock TMn count 0000H 0001H D0 + 1 D1 D1 + 1 FFFFH 0000H D2 + 1 value TIn0 pin input Value loaded...
Page 177: Control Register Settings For Pulse Width Measurement By Restarting
CHAPTER 7 TIMER/COUNTER FUNCTION Figure 7-14. Control Register Settings for Pulse Width Measurement by Restarting (a) 16-bit timer mode control registers 0, 1 (TMC0, TMC1) TMCn3 TMCn2 TMCn1 OVFn TMCn Clears and starts at valid edge of TIn0 pin. (b) Capture/compare control registers 0, 1 (CRC0, CRC1) CRCn2 CRCn1 CRCn0...
Page 178: Operation As External Event Counter
CHAPTER 7 TIMER/COUNTER FUNCTION 7.2.4 Operation as external event counter TMn can be used as an external event counter that counts the number of clock pulses input to the TIn0 pin from an external source by using 16-bit timer register n (TMn). Each time the valid edge specified by prescaler mode register n (PRMn) has been input, TMn is incremented.
Page 179: Configuration Of External Event Counter
CHAPTER 7 TIMER/COUNTER FUNCTION Figure 7-17. Configuration of External Event Counter 16-bit capture/compare register n0 (CRn0) Match INTTMn0 Clear Note Count clock 16-bit timer/counter n (TMn) OVFn fxx/2 Noise eliminator 16-bit capture/compare Valid edge of TIn0 register n1 (CRn1) Internal bus Note The count clock is set by the PRMn and PRMn1 registers.
Page 180: Operation To Output Square Wave
CHAPTER 7 TIMER/COUNTER FUNCTION 7.2.5 Operation to output square wave TMn can be used to output a square wave with any frequency at the interval specified by the count value set in advance to 16-bit capture/compare register n0 (CRn0). By setting bits 0 (TOEn) and 1 (TOCn1) of 16-bit timer output control register n (TOCn) to 1, the output status of the TOn pin is reversed at the interval specified by the count value set in advance to CRn1.
Page 181: Operation To Output One-Shot Pulse
CHAPTER 7 TIMER/COUNTER FUNCTION Figure 7-20. Timing of Square Wave Output Operation Count clock TMn count value 0000H 0001H 0002H – 0000H 0001H 0002H – 0000H CRn0 INTTMn0 TOn pin output Remark n = 0, 1 7.2.6 Operation to output one-shot pulse TMn can output a one-shot pulse in synchronization with a software trigger and an external trigger (TIn0 pin input).
Page 182: Control Register Settings For One-Shot Pulse Output With Software Trigger
CHAPTER 7 TIMER/COUNTER FUNCTION Figure 7-21. Control Register Settings for One-Shot Pulse Output with Software Trigger (a) 16-bit timer mode control registers 0, 1 (TMC0, TMC1) TMCn3 TMCn2 TMCn1 OVFn TMCn Free-running mode (b) Capture/compare control registers 0, 1 (CRC0, CRC1) CRCn2 CRCn1 CRCn0...
Page 183: Timing Of One-Shot Pulse Output Operation With Software Trigger
CHAPTER 7 TIMER/COUNTER FUNCTION Figure 7-22. Timing of One-Shot Pulse Output Operation with Software Trigger Set 0CH to TMCn (TMn count starts) Count clock TMn count 0000H 0001H N + 1 0000H – – 0000H 0001H value CRn1 set value CRn0 set value OSPTn...
Page 184: Control Register Settings For One-Shot Pulse Output With External Trigger
CHAPTER 7 TIMER/COUNTER FUNCTION Figure 7-23. Control Register Settings for One-Shot Pulse Output with External Trigger (a) 16-bit timer mode control registers 0, 1 (TMC0, TMC1) TMCn3 TMCn2 TMCn1 OVFn TMCn Clears and starts at valid edge of TIn0 pin. (b) Capture/compare control registers 0, 1 (CRC0, CRC1) CRCn2 CRCn1...
Page 185: Timing Of One-Shot Pulse Output Operation With External Trigger (With Rising Edge Specified)
CHAPTER 7 TIMER/COUNTER FUNCTION Figure 7-24. Timing of One-Shot Pulse Output Operation with External Trigger (with Rising Edge Specified) Set 08H to TMCn (TMn count starts) Count clock TMn count 0000H 0001H 0000H N + 1 N + 2 – –...
Page 186: Cautions
CHAPTER 7 TIMER/COUNTER FUNCTION 7.2.7 Cautions (1) Error on starting timer An error of up to 1 clock occurs before the match signal is generated after the timer has been started. This is because 16-bit timer register n (TMn) is started asynchronously to the count pulse. Figure 7-25.
Page 187: Data Hold Timing Of Capture Register
CHAPTER 7 TIMER/COUNTER FUNCTION (4) Data hold timing of capture register If the valid edge is input to the TIn0 pin while 16-bit capture/compare register n1 (CRn1) is being read, CRn1 performs a capture operation, but this capture value is not guaranteed. However, the interrupt request signal (INTTMn1) is set as a result of detection of the valid edge.
Page 188: Operation Timing Of Ovfn Flag
CHAPTER 7 TIMER/COUNTER FUNCTION (7) Operation of OVFn flag (a) OVFn flag set The OVFn flag is set to 1 in the following case in addition to when the TMn register overflows: Select the mode in which the timer is cleared and started on a match between TMn and CRn0. ↓...
Page 189 CHAPTER 7 TIMER/COUNTER FUNCTION (b) Acknowledgement of TIn0 and TIn1 pins When the timer is stopped, input signals to the TIn0 and TIn1 pins are not acknowledged, regardless of the CPU operation. (c) One-shot pulse output The one-shot pulse output operates correctly only in free-running mode or in clear & start mode at the valid edge of the TIn0 pin.
Page 190 CHAPTER 7 TIMER/COUNTER FUNCTION (12) Edge detection (a) When the TIn0 or TIn1 pin is high level immediately after a system reset When the TIn0 or TIn1 pin is high level immediately after a system reset, if the valid edge of the TIn0 or TIn1 pin is specified as the rising edge or both rising and falling edges, and the operation of 16-bit timer/counter n (TMn) is then enabled, the rising edge will be detected immediately.
Page 191: 8-Bit Timers (Tm2 To Tm5)
CHAPTER 7 TIMER/COUNTER FUNCTION 7.3 8-Bit Timers (TM2 to TM5) 7.3.1 Outline • 8-bit compare registers: 4 (CRn0) Can be used as 16-bit compare registers by connecting in cascade (2 max.). • Compare match/overflow interrupt request signal (INTTMn) output enabled •...
Page 192: Configuration
CHAPTER 7 TIMER/COUNTER FUNCTION Figure 7-29. Block Diagram of TM2 to TM5 Internal bus 8-bit compare Selector INTTMn register n (CRn0) Match Note 2 8-bit counter n (TMn) Note 1 Count clock Clear Invert level Selector TCLn3 TCLn2 TCLn1 TCLn0 TCEn TMCn6 TMCn4 LVSn LVRn TMCn1 TOEn Timer clock select register Timer mode control...
Page 193 CHAPTER 7 TIMER/COUNTER FUNCTION (1) 8-bit counters 2 to 5 (TM2 to TM5) TMn is an 8-bit read-only register that counts the count pulses. The counter is incremented in synchronization with the rising edge of the count clock. Through cascade connection, TM2 and TM3, and TM4 and TM5 can be used as 16-bit timers. When using TMm and TMm + 1 in cascade as a 16-bit timer, the timer can be read using a 16-bit memory manipulation instruction.
Page 194: Timer N Control Register
CHAPTER 7 TIMER/COUNTER FUNCTION 7.3.4 Timer n control register The following two types of registers control timer n. • Timer clock select registers n and n1 (TCLn, TCLn1) • 8-bit timer mode control register n (TMCn) User’s Manual U12768EJ4V1UD...
Page 195 CHAPTER 7 TIMER/COUNTER FUNCTION (1) Timer clock select registers 2 to 5, 21 to 51 (TCL2 to TCL5 and TCL21 to TCL51) These registers set the count clock of timer n. TCLn and TCLn1 are set by an 8-bit memory manipulation instruction. RESET input sets these registers to 00H.
Page 196 CHAPTER 7 TIMER/COUNTER FUNCTION (2/2) After reset: 00H Address: FFFFF264H, FFFFF274H TCLn TCLn2 TCLn1 TCLn0 (n = 4, 5) After reset: 00H Address: FFFFF26EH, FFFFF27EH TCLn1 TCLn3 (n = 4, 5) Count Clock Selection TCLn3 TCLn2 TCLn1 TCLn0 Count Clock 20 MHz 17 MHz 10 MHz...
Page 197 CHAPTER 7 TIMER/COUNTER FUNCTION (2) 8-bit timer mode control registers 2 to 5 (TMC2 to TMC5) The TMCn register makes the following six settings. (1) Controls counting by 8-bit counter n (TMn) (2) Selects the operating mode of 8-bit counter n (TMn) (3) Selects the individual mode or cascade connection mode (4) Sets the state of the timer output flip-flop (5) Controls the timer flip-flop or selects the active level in the PWM (free-running) mode...
Page 198 CHAPTER 7 TIMER/COUNTER FUNCTION After reset: Address: TMC2 FFFFF246H TMC4 FFFFF266H TMC3 FFFFF256H TMC5 FFFFF276H TMCn TMCn6 TCEn TMCn4 LVSn LVRn TMCn1 TOEn (n = 2 to 5) TCEn TMn Count Operation Control Counting is disabled after the counter is cleared to 0 (prescaler disabled) Start count operation TMCn6 TMn Operating Mode Selection...
Page 199: 8-Bit Timer Operation
CHAPTER 7 TIMER/COUNTER FUNCTION 7.4 8-Bit Timer Operation 7.4.1 Operation as interval timer (8-bit operation) The timer operates as an interval timer that repeatedly generates interrupts at the interval of the count preset by 8-bit compare register n (CRn0). If the count in 8-bit counter n (TMn) matches the value set in CRn0, the value of TMn is cleared to 0 and continues counting.
Page 200 CHAPTER 7 TIMER/COUNTER FUNCTION Figure 7-30. Timing of Interval Timer Operation (2/3) When CRn0 = 00H Count clock CRn0 TCEn INTTMn Interval time Remark n = 2 to 5 When CRn0 = FFH Count clock FEH FFH FEH FFH CRn0 TCEn INTTMn Interrupt acknowledgement...
Page 201 CHAPTER 7 TIMER/COUNTER FUNCTION Figure 7-30. Timing of Interval Timer Operation (3/3) Operated by CRn0 transition (M < N) Count clock CRn0 TCEn INTTMn CRn0 transition TMn overflows since M < N Remark n = 2 to 5 Operated by CRn0 transition (M > N) Count clock –...
Page 202: Operation As External Event Counter
CHAPTER 7 TIMER/COUNTER FUNCTION 7.4.2 Operation as external event counter The external event counter counts the number of external clock pulses that are input to TIn. Each time a valid edge specified by timer clock select register n, n1 (TCLn, TCLn1) is input, TMn is incremented. The edge setting can be selected as either the rising or falling edge.
Page 203: Operation As Square Wave Output (8-Bit Resolution)
CHAPTER 7 TIMER/COUNTER FUNCTION 7.4.3 Operation as square wave output (8-bit resolution) A square wave with any frequency is output at the interval preset by 8-bit compare register n (CRn0). By setting bit 0 (TOEn) of 8-bit timer mode control register n (TMCn) to 1, the output state of TOn is inverted with the count preset in CRn0 as the interval.
Page 204: Operation As 8-Bit Pwm Output
CHAPTER 7 TIMER/COUNTER FUNCTION 7.4.4 Operation as 8-bit PWM output By setting bit 6 (TMCn6) of 8-bit timer mode control register n (TMCn) to 1, the timer operates as a PWM output. Pulses with the duty factor determined by the value set to 8-bit compare register n (CRn0) are output from TOn. Set the width of the active level of the PWM pulse to CRn0.
Page 205: Timing Of Pwm Output
CHAPTER 7 TIMER/COUNTER FUNCTION Basic operation of PWM output Figure 7-33. Timing of PWM Output Basic operation (active level = H) Count clock N + 1 CRn0 TCEn INTTMn Active level Active level Active level When CRn0 = 00H Count clock 00H 01H CRn0 TCEn...
Page 206: Timing Of Operation Based On Crn0 Transition
CHAPTER 7 TIMER/COUNTER FUNCTION Operation based on CRn0 transitions Figure 7-34. Timing of Operation Based on CRn0 Transition When the CRn0 value changes from N to M before TMn overflows Count clock N + 1 N + 2 00H 01H 02H M+1 M+2 00H 01H 02H M+1 M+2...
Page 207: Operation As Interval Timer (16 Bits)
7.4.5 Operation as interval timer (16 bits) (1) Cascade connection (16-bit timer) mode The V850/SA1 provides 16-bit registers that can be used only when connected in cascade. The following registers are available. TM2 to TM3 cascade connection: 16-bit counter TM23 (Address: FFFFF24AH)
Page 208: Cascade Connection Mode With 16-Bit Resolution
CHAPTER 7 TIMER/COUNTER FUNCTION The following shows a timing example of the cascade connection mode with 16-bit resolution. Figure 7-35. Cascade Connection Mode with 16-Bit Resolution Count clock FFH 00H FFH 00H – CR20 CR30 TCE2 TCE3 INTTM2 Interval time Enable operation starting count Interrupt generation level inverted Operation...
Page 209: Cautions
CHAPTER 7 TIMER/COUNTER FUNCTION 7.4.6 Cautions (1) Error when timer starts An error of up to 1 clock occurs in the time until the match signal is generated after the timer starts. The reason is that 8-bit counter n (TMn) starts asynchronously to the count pulse. Figure 7-36.
Page 210: Chapter 8 Watch Timer
CHAPTER 8 WATCH TIMER 8.1 Functions The watch timer has the following functions. • Watch timer • Interval timer The watch timer and interval timer functions can be used at the same time. The block diagram of the watch timer is shown below. Figure 8-1.
Page 211: Configuration
CHAPTER 8 WATCH TIMER (1) Watch timer The watch timer generates an interrupt request signal (INTWT) at time intervals of 0.5 seconds by using the main clock or subclock. (2) Interval timer The watch timer generates an interrupt request (INTWTI) at time intervals specified in advance. Table 8-1.
Page 212: Watch Timer Control Register
CHAPTER 8 WATCH TIMER 8.3 Watch Timer Control Register The watch timer mode control register (WTM) controls the watch timer. (1) Watch timer mode control register (WTM) This register enables or disables the count clock and operation of the watch timer, sets the interval time of the prescaler, controls the operation of the 5-bit counter, and sets the interrupt time of the watch timer.
Page 213: Operation
CHAPTER 8 WATCH TIMER 8.4 Operation 8.4.1 Operation as watch timer The watch timer operates at time intervals of 0.5 seconds with the subclock (32.768 kHz) or main clock (16.777 MHz). The watch timer generates an interrupt request at fixed time intervals. The count operation of the watch timer is started when bits 0 (WTM0) and 1 (WTM1) of the watch timer mode control register (WTM) are set to 1.
Page 214: Cautions
CHAPTER 8 WATCH TIMER Figure 8-2. Operation Timing of Watch Timer/Interval Timer 5-bit counter Overflow Overflow Start Count clock f Watch timer interrupt INTWT Interrupt time of watch timer (0.5 s) Interrupt time of watch timer (0.5 s) Interval timer interrupt INTWTI Interval time Interval time...
Page 215: Chapter 9 Watchdog Timer
CHAPTER 9 WATCHDOG TIMER 9.1 Functions The watchdog timer has the following functions. Figure 9-1 shows a block diagram of the watchdog timer. • Watchdog timer • Interval timer • Selecting the oscillation stabilization time Caution Use the watchdog timer mode register (WDTM) to select the watchdog timer mode or the interval timer mode.
Page 216 CHAPTER 9 WATCHDOG TIMER (1) Watchdog timer mode This mode detects a program loop. When a loop is detected, a non-maskable interrupt can be generated. Table 9-1. Loop Detection Time of Watchdog Timer Loop Detection Time Clock = 10 MHz = 2 MHz = 20 MHz = 17 MHz...
Page 217: Configuration
CHAPTER 9 WATCHDOG TIMER 9.2 Configuration The watchdog timer consists of the following hardware. Table 9-3. Watchdog Timer Configuration Item Configuration Control registers Oscillation stabilization time select register (OSTS) Watchdog timer clock select register (WDCS) Watchdog timer mode register (WDTM) 9.3 Watchdog Timer Control Register Three registers control the watchdog timer.
Page 218 CHAPTER 9 WATCHDOG TIMER (2) Watchdog timer clock select register (WDCS) This register selects the overflow time of the watchdog timer and the interval timer. WDCS is set by an 8-bit memory manipulation instruction. RESET input sets WDCS to 00H. After reset: 00H Address: FFFFF382H WDCS...
Page 219 CHAPTER 9 WATCHDOG TIMER (3) Watchdog timer mode register (WDTM) This register sets the operating mode of the watchdog timer, and enables and disables counting. WDTM is set by a 1-bit or 8-bit memory manipulation instruction. RESET input sets WDTM to 00H. After reset: 00H Address: FFFFF384H WDTM...
Page 220: Operation
CHAPTER 9 WATCHDOG TIMER 9.4 Operation 9.4.1 Operating as watchdog timer Set bit 4 (WDTM4) of the watchdog timer mode register (WDTM) to 1 to operate as a watchdog timer to detect a program loop. Setting bit 7 (RUN) of WDTM to 1 starts the count operation. After counting starts, if RUN is set to 1 again within the set time interval for loop detection, the watchdog timer is cleared and counting starts again.
Page 221: Operating As Interval Timer
CHAPTER 9 WATCHDOG TIMER 9.4.2 Operating as interval timer Set bit 4 (WDTM4) to 0 in the watchdog timer mode register (WDTM) to operate the watchdog timer as an interval timer that repeatedly generates interrupts with a preset count value as the interval. When operating as an interval timer, the interrupt mask flag (WDTMK) of the WDTIC register and the priority setting flag (WDTPR0 to WDTPR2) become valid, and a maskable interrupt (INTWDTM) can be generated.
Page 222: Standby Function Control Register
CHAPTER 9 WATCHDOG TIMER 9.5 Standby Function Control Register (1) Oscillation stabilization time select register (OSTS) The wait time from releasing the software STOP mode until the oscillation stabilizes is controlled by the oscillation stabilization time select register (OSTS). OSTS is set by an 8-bit memory manipulation instruction. RESET input sets OSTS to 04H.
Page 223: Chapter 10 Serial Interface Function
CHAPTER 10 SERIAL INTERFACE FUNCTION 10.1 Overview The V850/SA1 supports the following on-chip serial interfaces. Note • Channel 0: 3-wire serial I/O (CSI0)/I C bus interface (I • Channel 1: 3-wire serial I/O (CSI1)/Asynchronous serial interface (UART0) • Channel 2: 3-wire serial I/O (CSI2) •...
Page 224: Configuration
CHAPTER 10 SERIAL INTERFACE FUNCTION 10.2.1 Configuration CSIn consists of the following hardware. Table 10-1. Configuration of CSIn Item Configuration Registers Serial I/O shift registers 0 to 2 (SIO0 to SIO2) Control registers Serial clock select registers 0 to 2 (CSIS0 to CSIS2) Serial operation mode registers 0 to 2 (CSIM0 to CSIM2) Figure 10-1.
Page 225: Csin Control Registers
CHAPTER 10 SERIAL INTERFACE FUNCTION 10.2.2 CSIn control registers CSIn uses the following registers for control functions. • Serial clock select register n (CSISn) • Serial operation mode register n (CSIMn) (1) Serial clock select registers 0 to 2 (CSIS0 to CSIS2), serial operation mode registers 0 to 2 (CSIM0 to CSIM2) The CSISn register is used to set of the serial clock serial interface channel n.
Page 226 CHAPTER 10 SERIAL INTERFACE FUNCTION After reset: 00H Address: CSIS0 FFFFF2A4H CSIS1 FFFFF2B4H CSIS2 FFFFF2C4H CSISn SCLn2 After reset: 00H Address: CSIM0 FFFFF2A2H CSIM1 FFFFF2B2H CSIM2 FFFFF2C2H CSIMn CSIEn MODEn SCLn1 SCLn0 (n = 0 to 2) SIOn Operation Enable/Disable Specification CSIEn Shift Register Operation Serial Counter...
Page 227: Operations
CHAPTER 10 SERIAL INTERFACE FUNCTION 10.2.3 Operations CSIn has the following two operation modes. • Operation stop mode • 3-wire serial I/O mode (1) Operation stop mode Serial transfers are not performed in this mode, enabling a reduction in power consumption. In operation stop mode, if the SIn, SOn, and SCKn pins are also used as I/O ports, they can be used as normal I/O ports as well.
Page 228: Settings Of Csimn (3-Wire Serial I/O Mode)
CHAPTER 10 SERIAL INTERFACE FUNCTION (2) 3-wire serial I/O mode 3-wire serial I/O mode is useful when connecting to a peripheral I/O device that includes a clocked serial interface, a display controller, etc. This mode executes data transfers via three lines: a serial clock line (SCKn), serial output line (SOn), and serial input line (SIn).
Page 229: Timing Of 3-Wire Serial I/O Mode
CHAPTER 10 SERIAL INTERFACE FUNCTION (b) Communication operations In 3-wire serial I/O mode, data is transmitted and received in 8-bit units. Each bit of data is transmitted or received in synchronization with the serial clock. Serial I/O shift register n (SIOn) is shifted in synchronization with the falling edge of the serial clock. Transmission data is held in the SOn latch and is output from the SOn pin.
Page 230: I C Bus (Interface I C)
CHAPTER 10 SERIAL INTERFACE FUNCTION 10.3 I C Bus Interface (I To use the I C bus function, set the P10/SDA and P12/SCL pins to N-ch open-drain output. The products that incorporate I C are shown below. µ PD703014AY, 703014BY, 703015AY, 703015BY, 703017AY, 70F3015BY, 70F3017AY C has the following two modes.
Page 231: Block Diagram Of I 2 C
CHAPTER 10 SERIAL INTERFACE FUNCTION Figure 10-5. Block Diagram of I Internal bus IIC status register 0 (IICS0) MSTS ACKD IIC control register 0 (IICC0) Slave address register 0 (SVA0) IICE LREL WREL SPIE WTIM ACKE Match CLEAR signal Noise eliminator SO latch IIC shift register 0 (IIC0)
Page 232: C Bus
CHAPTER 10 SERIAL INTERFACE FUNCTION The following shows a serial bus configuration example. Figure 10-6. Serial Bus Configuration Example Using I C Bus Master CPU1 Master CPU2 Serial data bus Slave CPU2 Slave CPU1 Serial clock Address 1 Address 2 Slave CPU3 Address 3 Slave IC...
Page 233: Configuration
CHAPTER 10 SERIAL INTERFACE FUNCTION 10.3.1 Configuration C consists of the following hardware. Table 10-2. Configuration of I Item Configuration Registers IIC shift register 0 (IIC0) Slave address register 0 (SVA0) Control registers IIC control register 0 (IICC0) IIC status register 0 (IICS0) IIC clock select register 0 (IICCL0) IIC function expansion register 0 (IICX0) IIC shift register 0 (IIC0)
Page 234 CHAPTER 10 SERIAL INTERFACE FUNCTION Serial clock counter This counter counts the serial clocks that are output and the serial clocks that are input during transmit/receive operations and is used to verify that 8-bit data was transmitted or received. Interrupt request signal generator This circuit controls the generation of interrupt request signal (INTIIC0).
Page 235: C Control Registers
CHAPTER 10 SERIAL INTERFACE FUNCTION 10.3.2 I C control registers C is controlled by four types of registers. • IIC control register 0 (IICC0) • IIC status register 0 (IICS0) • IIC function expansion register 0 (IICX0) • IIC clock select register 0 (IICCL0) The following registers are also used.
Page 236 CHAPTER 10 SERIAL INTERFACE FUNCTION (1) IIC control register 0 (IICC0) IICC0 is used to enable/disable I C operations, set wait timing, and set other I C operations. IICC0 can be set by a 1-bit or 8-bit memory manipulation instruction. RESET input sets IICC0 to 00H.
Page 237 CHAPTER 10 SERIAL INTERFACE FUNCTION (2/4) WREL Wait Cancellation Control Wait not canceled Wait canceled. This setting is automatically cleared after wait is canceled. Note Condition for clearing (WREL = 0) Condition for setting (WREL = 1) • Automatically cleared after execution •...
Page 238 CHAPTER 10 SERIAL INTERFACE FUNCTION (3/4) Start Condition Trigger Start conditions not generated. When bus is released (in STOP mode): Generate a start condition (for starting as master). The SDA line is changed from high level to low level and then the start condition is generated. Next, after the rated amount of time has elapsed, SCL is changed to low level.
Page 239 CHAPTER 10 SERIAL INTERFACE FUNCTION (4/4) Stop Condition Trigger Stop condition is not generated. Stop condition is generated (termination of master device’s transfer). After the SDA line goes to low level, either set the SCL line to high level or wait until it goes to high level.
Page 240 CHAPTER 10 SERIAL INTERFACE FUNCTION (2) IIC status register 0 (IICS0) IICS0 indicates the status of the I C bus. IICS0 can be set by a 1-bit or 8-bit memory manipulation instruction. IICS0 is a read-only register. RESET input sets IICS0 to 00H. (1/3) After reset: 00H Address: FFFFF342H...
Page 241 CHAPTER 10 SERIAL INTERFACE FUNCTION (2/3) Detection of Extension Code Reception Extension code was not received. Extension code was received. Condition for clearing (EXC = 0) Condition for setting (EXC = 1) • When a start condition is detected • When the higher four bits of the received address •...
Page 242 CHAPTER 10 SERIAL INTERFACE FUNCTION (3/3) ACKD Detection of ACK ACK was not detected. ACK was detected. Condition for clearing (ACKD = 0) Condition for setting (ACKD = 1) • When a stop condition is detected • After the SDA line is set to low level at the rising •...
Page 243 CHAPTER 10 SERIAL INTERFACE FUNCTION (3) IIC clock select register 0 (IICCL0), IIC function expansion register 0 (IICX0) The IICCL0 and IICX0 registers are used to set the transfer clock for the I C bus. The IICCL0 and IICX0 registers can be set by an 8-bit or 1-bit memory manipulation instruction. RESET input sets these registers to 00H.
Page 244 CHAPTER 10 SERIAL INTERFACE FUNCTION (2/2) Selection Clock Range of Settable Main Clock Operation Mode Frequency (f 2.0 MHz to 4.19 MHz Standard mode (SMC = 0) 4.19 MHz to 8.38 MHz /172 8.38 MHz to 17 MHz TM2 output/66 TM2 setting 4.0 MHz to 8.38 MHz High-speed mode...
Page 245: I C Bus Mode Functions
CHAPTER 10 SERIAL INTERFACE FUNCTION 10.3.3 C bus mode functions Pin configuration The serial clock pin (SCL) and serial data bus pin (SDA) are configured as follows. SCL ....This pin is used for serial clock input and output. This pin is an N-ch open-drain output for both master and slave devices. Input is Schmitt input. SDA ....
Page 246: C Bus Definitions And Control Methods
CHAPTER 10 SERIAL INTERFACE FUNCTION 10.3.4 I C bus definitions and control methods The following section describes the I C bus’s serial data communication format and the signals used by the I C bus. Figure 10-8 shows the transfer timing for the “start condition”, “data”, and “stop condition” output via the I C bus’s serial data bus.
Page 247: Address
CHAPTER 10 SERIAL INTERFACE FUNCTION (2) Addresses The 7 bits of data that follow the start condition are defined as an address. An address is a 7-bit data segment that is output in order to select one of the slave devices that are connected to the master device via bus lines.
Page 248: Transfer Direction Specification
CHAPTER 10 SERIAL INTERFACE FUNCTION (3) Transfer direction specification In addition to the 7-bit address data, the master device transmits 1-bit data that specifies the transfer direction. When this transfer direction specification bit has a value of 0, it indicates that the master device is transmitting data to a slave device.
Page 249: Ack Signal
CHAPTER 10 SERIAL INTERFACE FUNCTION (4) Acknowledge signal (ACK) The acknowledge signal (ACK) is used by the transmitting and receiving devices to confirm serial data reception. The receiving device returns one ACK signal for every 8 bits of data it receives. The transmitting device normally receives an ACK signal after transmitting 8 bits of data.
Page 250: Stop Condition
CHAPTER 10 SERIAL INTERFACE FUNCTION When the local address is received, an ACK signal is automatically output in synchronization with the falling edge of the SCL’s eighth clock regardless of the ACKE value. No ACK signal is output if the received address is not a local address.
Page 251: Wait Signal
CHAPTER 10 SERIAL INTERFACE FUNCTION (6) Wait signal (WAIT) The wait signal (WAIT) is used to notify the communication partner that a device (master or slave) is preparing to transmit or receive data (i.e., is in a wait state). Setting the SCL pin to low level notifies the communication partner of the wait status. When the wait status has been canceled for both the master and slave devices, the next data transfer can begin.
Page 252 CHAPTER 10 SERIAL INTERFACE FUNCTION Figure 10-14. Wait Signal (2/2) (b) When master and slave devices both have a nine-clock wait (master: transmission, slave: reception, and ACKE = 1) Master and slave both wait Master after output of ninth clock IIC0 data write (cancel wait) IIC0 Slave...
Page 253: C Interrupt Request (Intiic0)
CHAPTER 10 SERIAL INTERFACE FUNCTION 10.3.5 I C interrupt request (INTIIC0) The following shows the value of IIC status register 0 (IICS0) at the INTIIC0 interrupt request generation timing and at the INTIIC0 interrupt timing. Remark The interrupt control register of INTIIC0 is alternately used as the interrupt control register (CSIC0) of INTCSI0.
Page 254 CHAPTER 10 SERIAL INTERFACE FUNCTION (b) Start ~ Address ~ Data ~ Start ~ Address ~ Data ~ Stop (restart) <1> When WTIM = 0 STT = 1 SPT = 1 ↓ ↓ AD6-AD0 D7-D0 AD6-AD0 D7-D0 ▲1 ▲2 ▲3 ▲4 ▲5 ▲6...
Page 255 CHAPTER 10 SERIAL INTERFACE FUNCTION (c) Start ~ Code ~ Data ~ Data ~ Stop (extension code transmission) <1> When WTIM = 0 SPT = 1 ↓ AD6-AD0 D7-D0 D7-D0 ▲1 ▲2 ▲3 ▲4 ∆5 ▲1: IICS0 = 1010X110B ▲2: IICS0 = 1010X000B ▲3: IICS0 = 1010X000B (WTIM = 1) ▲4: IICS0 = 1010XX00B ∆...
Page 256 CHAPTER 10 SERIAL INTERFACE FUNCTION (2) Slave device operation (when receiving slave address data (matches SVA0)) (a) Start ~ Address ~ Data ~ Data ~ Stop <1> When WTIM = 0 AD6-AD0 D7-D0 D7-D0 ▲1 ▲2 ▲3 ∆4 ▲1: IICS0 = 0001X110B ▲2: IICS0 = 0001X000B ▲3: IICS0 = 0001X000B ∆...
Page 257 CHAPTER 10 SERIAL INTERFACE FUNCTION (b) Start ~ Address ~ Data ~ Start ~ Address ~ Data ~ Stop <1> When WTIM = 0 (after restart, matches SVA0) AD6-AD0 D7-D0 AD6-AD0 D7-D0 ▲1 ▲2 ▲3 ▲4 ∆5 ▲1: IICS0 = 0001X110B ▲2: IICS0 = 0001X000B ▲3: IICS0 = 0001X110B ▲4: IICS0 = 0001X000B...
Page 258 CHAPTER 10 SERIAL INTERFACE FUNCTION (c) Start ~ Address ~ Data ~ Start ~ Code ~ Data ~ Stop <1> When WTIM = 0 (after restart, extension code reception) AD6-AD0 D7-D0 AD6-AD0 D7-D0 ▲1 ▲2 ▲3 ▲4 ∆5 ▲1: IICS0 = 0001X110B ▲2: IICS0 = 0001X000B ▲3: IICS0 = 0010X010B ▲4: IICS0 = 0010X000B...
Page 259 CHAPTER 10 SERIAL INTERFACE FUNCTION (d) Start ~ Address ~ Data ~ Start ~ Address ~ Data ~ Stop <1> When WTIM = 0 (after restart, does not match address (= not extension code)) AD6-AD0 D7-D0 AD6-AD0 D7-D0 ▲1 ▲2 ▲3 ∆4 ▲1: IICS0 = 0001X110B...
Page 260 CHAPTER 10 SERIAL INTERFACE FUNCTION (3) Slave device operation (when receiving extension code) (a) Start ~ Code ~ Data ~ Data ~ Stop <1> When WTIM = 0 AD6-AD0 D7-D0 D7-D0 ▲1 ▲2 ▲3 ∆4 ▲1: IICS0 = 0010X010B ▲2: IICS0 = 0010X000B ▲3: IICS0 = 0010X000B ∆...
Page 261 CHAPTER 10 SERIAL INTERFACE FUNCTION (b) Start ~ Code ~ Data ~ Start ~ Address ~ Data ~ Stop <1> When WTIM = 0 (after restart, matches SVA0) AD6-AD0 D7-D0 AD6-AD0 D7-D0 ▲1 ▲2 ▲3 ▲4 ∆5 ▲1: IICS0 = 0010X010B ▲2: IICS0 = 0010X000B ▲3: IICS0 = 0001X110B ▲4: IICS0 = 0001X000B...
Page 262 CHAPTER 10 SERIAL INTERFACE FUNCTION (c) Start ~ Code ~ Data ~ Start ~ Code ~ Data ~ Stop <1> When WTIM = 0 (after restart, extension code reception) AD6-AD0 D7-D0 AD6-AD0 D7-D0 ▲1 ▲2 ▲3 ▲4 ∆5 ▲1: IICS0 = 0010X010B ▲2: IICS0 = 0010X000B ▲3: IICS0 = 0010X010B ▲4: IICS0 = 0010X000B...
Page 263 CHAPTER 10 SERIAL INTERFACE FUNCTION (d) Start ~ Code ~ Data ~ Start ~ Address ~ Data ~ Stop <1> When WTIM = 0 (after restart, does not match address (= not extension code)) AD6-AD0 D7-D0 AD6-AD0 D7-D0 ▲1 ▲2 ▲3 ∆4 ▲1: IICS0 = 0010X010B...
Page 264 CHAPTER 10 SERIAL INTERFACE FUNCTION (4) Operation without communication (a) Start ~ Code ~ Data ~ Data ~ Stop AD6-AD0 D7-D0 D7-D0 ∆1 ∆ 1: IICS0 = 00000001B ∆: Generated only when SPIE = 1 Remark (5) Arbitration loss operation (operation as slave after arbitration loss) (a) When arbitration loss occurs during transmission of slave address data <1>...
Page 265 CHAPTER 10 SERIAL INTERFACE FUNCTION (b) When arbitration loss occurs during transmission of extension code <1> When WTIM = 0 AD6-AD0 D7-D0 D7-D0 ▲1 ▲2 ▲3 ∆4 ▲1: IICS0 = 0110X010B (Example: when ALD is read during interrupt servicing) ▲2: IICS0 = 0010X000B ▲3: IICS0 = 0010X000B ∆...
Page 266 CHAPTER 10 SERIAL INTERFACE FUNCTION Operation when arbitration loss occurs (no communication after arbitration loss) (a) When arbitration loss occurs during transmission of slave address data AD6-AD0 D7-D0 D7-D0 ▲1 ∆2 ▲1: IICS0 = 01000110B (Example: when ALD is read during interrupt servicing) ∆...
Page 267 CHAPTER 10 SERIAL INTERFACE FUNCTION (c) When arbitration loss occurs during data transfer <1> When WTIM = 0 AD6-AD0 D7-D0 D7-D0 ▲1 ▲2 ∆3 ▲1: IICS0 = 10001110B ▲2: IICS0 = 01000000B (Example: when ALD is read during interrupt servicing) ∆...
Page 268 CHAPTER 10 SERIAL INTERFACE FUNCTION (d) When loss occurs due to restart condition during data transfer <1> Not extension code (Example: does not match SVA0) AD6-AD0 D7-Dn AD6-AD0 D7-D0 ▲1 ▲2 ∆3 ▲1: IICS0 = 1000X110B ▲2: IICS0 = 01000110B (Example: when ALD is read during interrupt servicing) ∆...
Page 269 CHAPTER 10 SERIAL INTERFACE FUNCTION (e) When loss occurs due to stop condition during data transfer AD6-AD0 D7-Dn ▲1 ∆2 ▲1: IICS0 = 1000X110B ∆ 2: IICS0 = 01000001B ▲: Always generated Remark ∆: Generated only when SPIE = 1 X: don’t care Dn = D6 to D0 (f) When arbitration loss occurs due to low-level data when attempting to generate a restart condition...
Page 270 CHAPTER 10 SERIAL INTERFACE FUNCTION (g) When arbitration loss occurs due to a stop condition when attempting to generate a restart condition When WTIM = 1 STT = 1 ↓ AD6-AD0 D7-D0 ▲1 ▲2 ∆3 ▲1: IICS0 = 1000X110B ▲2: IICS0 = 1000XX00B ∆...
Page 271: Interrupt Request (Intiic0) Generation Timing And Wait Control
CHAPTER 10 SERIAL INTERFACE FUNCTION 10.3.6 Interrupt request (INTIIC0) generation timing and wait control The setting of bit 3 (WTIM) of IIC control register 0 (IICC0) determines the timing by which INTIIC0 is generated and the corresponding wait control, as shown below. Table 10-3.
Page 272: Address Match Detection Method
CHAPTER 10 SERIAL INTERFACE FUNCTION 10.3.7 Address match detection method In I C bus mode, the master device can select a particular slave device by transmitting the corresponding slave address. Address match detection is performed automatically by hardware. An interrupt request (INTIIC0) occurs when a local address has been set to slave address register 0 (SVA0) and when the address set to SVA0 matches the slave address sent by the master device, or when an extension code has been received.
Page 273: Arbitration
CHAPTER 10 SERIAL INTERFACE FUNCTION 10.3.10 Arbitration When several master devices simultaneously output a start condition (when STT is set to 1 before STD is set to Note ), communication among the master devices is performed as the number of clocks is adjusted until the data differs. This kind of operation is called arbitration.
Page 274: Wakeup Function
CHAPTER 10 SERIAL INTERFACE FUNCTION Table 10-5. Status During Arbitration and Interrupt Request Generation Timing Status During Arbitration Interrupt Request Generation Timing Note 1 At falling edge of eighth or ninth clock following byte transfer During address transmission Read/write data after address transmission During extension code transmission Read/write data after extension code transmission During data transmission...
Page 275: Communication Reservation
CHAPTER 10 SERIAL INTERFACE FUNCTION 10.3.12 Communication reservation To start master device communications when not currently using the bus, a communication reservation can be made to enable transmission of a start condition when the bus is released. There are two modes under which the bus is not used.
Page 276: Communication Reservation Timing
CHAPTER 10 SERIAL INTERFACE FUNCTION The communication reservation timing is shown below. Figure 10-16. Communication Reservation Timing Write to Program processing IIC0 Set SPD Communication Hardware processing reservation and INTIIC0 Output by master with bus mastership IIC0: IIC shift register 0 STT0: Bit 1 of IIC control register 0 (IICC0) STD0:...
Page 277: Communication Reservation Flow Chart
CHAPTER 10 SERIAL INTERFACE FUNCTION The communication reservation flow chart is illustrated below. Figure 10-18. Communication Reservation Flow Chart SET1 STT ; Sets STT flag (communication reservation). ; Defines that communication reservation is in effect Define communication reservation (defines and sets user flag to any part of RAM). ;...
Page 278: Cautions
CHAPTER 10 SERIAL INTERFACE FUNCTION 10.3.13 Cautions After a reset, when changing from a mode in which no stop condition has been detected (the bus has not been released) to a master device communication mode, first generate a stop condition to release the bus, then perform master device communication.
Page 279: Communication Operations
CHAPTER 10 SERIAL INTERFACE FUNCTION 10.3.14 Communication operations Master operations The following is a flow chart of the master operations. Figure 10-19. Master Operation Flow Chart START ← IICCL0 Select transfer clock. ← IICC0 IICE = SPIE = WTIM = 1 STT = 1 ;...
Page 280: Slave Operation Flow Chart
CHAPTER 10 SERIAL INTERFACE FUNCTION Slave operation The following is a flow chart of the slave operations. Figure 10-20. Slave Operation Flow Chart START ← ××H IICC0 IICE = 1 INTIIC0 = 1? EXC = 1? Communicate? COI = 1? LREL = 1 No (receive) TRC = 1?
Page 281: Timing Of Data Communication
CHAPTER 10 SERIAL INTERFACE FUNCTION 10.3.15 Timing of data communication When using I C bus mode, the master device outputs an address via the serial bus to select one of several slave devices as its communication partner. After outputting the slave address, the master device transmits the TRC bit (bit 3 of IIC status register 0 (IICS0)) that specifies the data transfer direction and then starts serial communication with the slave device.
Page 282: Example Of Master To Slave Communication (When 9-Clock Wait Is Selected For Both Master And Slave)
CHAPTER 10 SERIAL INTERFACE FUNCTION Figure 10-21. Example of Master to Slave Communication (When 9-Clock Wait Is Selected for Both Master and Slave) (1/3) (a) Start condition ~ address Processing by master device ← ← IIC0 IIC0 address IIC0 data ACKD WTIM ACKE...
Page 283 CHAPTER 10 SERIAL INTERFACE FUNCTION Figure 10-21. Example of Master to Slave Communication (When 9-Clock Wait Is Selected for Both Master and Slave) (2/3) (b) Data Processing by master device ← ← IIC0 data IIC0 data IIC0 ACKD WTIM ACKE MSTS WREL INTIIC0...
Page 284 CHAPTER 10 SERIAL INTERFACE FUNCTION Figure 10-21. Example of Master to Slave Communication (When 9-Clock Wait Is Selected for Both Master and Slave) (3/3) (c) Stop condition Processing by master device ← ← IIC0 data IIC0 address IIC0 ACKD WTIM ACKE MSTS WREL...
Page 285 CHAPTER 10 SERIAL INTERFACE FUNCTION Figure 10-22. Example of Slave to Master Communication (When 9-Clock Wait Is Selected for Both Master and Slave) (1/3) (a) Start condition ~ address Processing by master device ← ← IIC0 IIC0 address IIC0 FFH Note ACKD WTIM ACKE...
Page 286 CHAPTER 10 SERIAL INTERFACE FUNCTION Figure 10-22. Example of Slave to Master Communication (When 9-Clock Wait Is Selected for Both Master and Slave) (2/3) (b) Data Processing by master device IIC0 ← FFH Note IIC0 ← FFH Note IIC0 ACKD WTIM ACKE MSTS...
Page 287 CHAPTER 10 SERIAL INTERFACE FUNCTION Figure 10-22. Example of Slave to Master Communication (When 9-Clock Wait Is Selected for Both Master and Slave) (3/3) (c) Stop condition Processing by master device ← ← IIC0 IIC0 FFH Note IIC0 address ACKD WTIM ACKE MSTS...
Page 288: Asynchronous Serial Interface (Uart0, Uart1)
CHAPTER 10 SERIAL INTERFACE FUNCTION 10.4 Asynchronous Serial Interface (UART0, UART1) UARTn (n = 0, 1) has the following two operation modes. (1) Operation stop mode This mode is used when serial transfers are not performed. It can therefore be used to reduce power consumption.
Page 289 CHAPTER 10 SERIAL INTERFACE FUNCTION Figure 10-23. Block Diagram of UARTn Internal bus Receive buffer registers 0, 1 (RXB0, RXB1) Receive shift registers RXD0, RXD1 0, 1 (RX0, RX1) Transmit shift registers TXD0, TXD1 0, 1 (TXS0, TXS1) Receive control INTSR0, parity check INTSR1 INTST0, Transmit control parity addition INTST1 Baud rate generator to f Selector TMx output ASCK0, ASCK1 Remark TMx output is as follows: UART0: TM3 UART1: TM2 (1) Transmit shift registers 0, 1 (TXS0, TXS1) TXSn is the register for setting transmit data.
Page 290: Uartn Control Registers
CHAPTER 10 SERIAL INTERFACE FUNCTION (4) Transmission controller The transmission controller controls transmit operations, such as adding a start bit, parity bit, and stop bit to data that is written to transmit shift register n (TXSn), based on the values set to asynchronous serial interface mode register n (ASIMn).
Page 291 CHAPTER 10 SERIAL INTERFACE FUNCTION After reset: 00H Address: FFFFF300H, FFFFF310H ASIMn TXEn RXEn PS1n PS0n UCLn ISRMn (n = 0, 1) RXDn/Pxx Pin TXDn/Pxx Pin TXEn RXEn Operation Mode Function Function Operation stop Port function Port function UART mode (receive only) Serial function Port function UART mode (transmit only)
Page 292 CHAPTER 10 SERIAL INTERFACE FUNCTION (2) Asynchronous serial interface status registers 0, 1 (ASIS0, ASIS1) When a receive error occurs in UART mode, these registers indicate the type of error. ASISn can be read using an 8-bit or 1-bit memory manipulation instruction. RESET input sets these registers to 00H.
Page 293 CHAPTER 10 SERIAL INTERFACE FUNCTION (3) Baud rate generator control registers 0, 1 (BRGC0, BRGC1) These registers set the serial clock for UARTn. BRGCn can be set by an 8-bit memory manipulation instruction. RESET input sets these registers to 00H. After reset: 00H Address: FFFFF304H, FFFFF314H BRGCn...
Page 294 CHAPTER 10 SERIAL INTERFACE FUNCTION (4) Baud rate generator mode control registers 0, 01 (BRGMC0, BRGMC01) These registers set the UARTn source clock. BRGMC0 and BRGMC01 are set by an 8-bit memory manipulation instruction. RESET input sets these registers to 00H. After reset: 00H Address: FFFFF320H BRGMC01...
Page 295 CHAPTER 10 SERIAL INTERFACE FUNCTION (5) Baud rate generator mode control register 1 (BRGMC1) This register sets the UART1 source clock. BRGMC1 is set by an 8-bit memory manipulation instruction. RESET input sets this register to 00H. After reset: 00H Address: FFFFF31EH BRGMC1 TPS12...
Page 296: Operations
CHAPTER 10 SERIAL INTERFACE FUNCTION 10.4.3 Operations UARTn has the following two operation modes. • Operation stop mode • Asynchronous serial interface (UART) mode (1) Operation stop mode This mode is used when serial transfers are not performed. It can therefore be used to reduce power consumption.
Page 297 CHAPTER 10 SERIAL INTERFACE FUNCTION (2) Asynchronous serial interface (UART) mode This mode enables full-duplex operation in which one byte of data is transmitted and received after the start bit. The on-chip dedicated UARTn baud rate generator enables communications using a wide range of selectable baud rates.
Page 298 CHAPTER 10 SERIAL INTERFACE FUNCTION Figure 10-26. ASISn Setting (UART Mode) After reset: 00H Address: FFFFF302H, FFFFF312H ASISn OVEn (n = 0, 1) Parity error flag No parity error Parity error (Transmit data parity does not match) Framing error flag No framing error Note 1 Framing error...
Page 299 CHAPTER 10 SERIAL INTERFACE FUNCTION Figure 10-27. BRGCn Setting (UART Mode) After reset: 00H Address: FFFFF304H, FFFFF314H BRGCn MDLn7 MDLn6 MDLn5 MDLn4 MDLn3 MDLn2 MDLn1 MDLn0 (n = 0, 1) Input clock selection × × × − Setting prohibited • •...
Page 300 CHAPTER 10 SERIAL INTERFACE FUNCTION Figure 10-28. BRGMC0 and BRGMC01 Settings (UART Mode) After reset: 00H Address: FFFFF30EH BRGMC0 TPS02 TPS01 TPS00 After reset: 00H Address: FFFFF320H BRGMC01 TPS03 TPS03 TPS02 TPS01 TPS00 8-bit counter source clock selection − External clock (ASCK0) −...
Page 301 CHAPTER 10 SERIAL INTERFACE FUNCTION Figure 10-29. BRGMC1 Settings (UART Mode) After reset: 00H Address: FFFFF31EH BRGMC1 TPS12 TPS11 TPS10 TPS12 TPS11 TPS10 8-bit counter source clock selection − External clock (ASCK1) − TM2 output Cautions 1. If write is performed to the BRGMC1 register during communication processing, the output of the baud rate generator is disturbed and communication will not be performed normally.
Page 302 CHAPTER 10 SERIAL INTERFACE FUNCTION (b) Baud rate The transmit/receive clock for the baud rate to be generated is a signal generated by dividing the main clock. • Generation of baud rate transmit/receive clock using main clock The transmit/receive clock is obtained by dividing the main clock. The following equation is used to obtain the baud rate from the main clock.
Page 303 CHAPTER 10 SERIAL INTERFACE FUNCTION Table 10-8. Relationship Between Main Clock and Baud Rate Baud = 2 MHz = 4.194 MHz = 8.388 MHz = 17 MHz = 20 MHz Rate Error Error Error Error Error (bps) −4.26   ...
Page 304 CHAPTER 10 SERIAL INTERFACE FUNCTION (c) Communication operations (i) Data format As shown in Figure 10-31, the format of the transmit/receive data consists of a start bit, character bits, a parity bit, and one or more stop bits. Asynchronous serial interface mode register n (ASIMn) is used to set the character bit length, parity selection, and stop bit length within each data frame (n = 0, 1).
Page 305 CHAPTER 10 SERIAL INTERFACE FUNCTION (ii) Parity types and operations The parity bit is used to detect bit errors in transfer data. Usually, the same type of parity bit is used by the transmitting and receiving sides. When odd parity or even parity is set, errors in the parity bit (the odd- number bit) can be detected.
Page 306 CHAPTER 10 SERIAL INTERFACE FUNCTION (iii) Transmission The transmit operation is started when transmit data is written to transmit shift register n (TXSn). A start bit, parity bit, and stop bit(s) are automatically added to the data. Starting the transmit operation shifts out the data in TXSn, thereby emptying TXSn, after which a transmit completion interrupt (INTSTn) is issued.
Page 307 CHAPTER 10 SERIAL INTERFACE FUNCTION (iv) Reception The receive operation is enabled when “1” is set to bit 6 (RXEn) of asynchronous serial interface mode register n (ASIMn), and the input via the RXDn pin is sampled. The serial clock specified by baud rate generator control register n (BRGCn) is used when sampling the RXDn pin.
Page 308 CHAPTER 10 SERIAL INTERFACE FUNCTION (v) Receive error Three types of errors can occur during a receive operation: a parity error, framing error, and overrun error. When, as the result of data reception, an error flag is set in asynchronous serial interface status register n (ASISn), the receive error interrupt request (INTSERn) is generated.
Page 309: Standby Function
CHAPTER 10 SERIAL INTERFACE FUNCTION 10.4.4 Standby function (1) Operation in HALT mode Only serial transfer operations are performed normally. (2) Operation in IDLE and software STOP modes (a) When internal clock is selected as serial clock The operations of asynchronous serial interface mode register n (ASIMn), asynchronous serial status register n (ASISn), baud rate generator control register n (BRGCn), baud rage generator mode control registers n and 01 (BRGMCn, BRGMC01), transmit shift register n (TXSn), and receive buffer register n (RXBn) are stopped and their values immediately before the clock stopped are held.
Page 310: Chapter 11 A/D Converter
CHAPTER 11 A/D CONVERTER 11.1 Function The A/D converter converts analog input signals into digital values with a resolution of 10 bits, and can handle 12 channels of analog input signals (ANI0 to ANI11). (1) Hardware start Conversion is started by trigger input (ADTRG) (rising edge, falling edge, or both rising and falling edges can be specified).
Page 311 CHAPTER 11 A/D CONVERTER The block diagram is shown below. Figure 11-1. Block Diagram of A/D Converter ANI0 ANI1 ANI2 Sample & hold circuit ANI3 ANI4 Voltage comparator ANI5 ANI6 ANI7 ANI8 ANI9 ANI10 Successive ANI11 approximation register (SAR) Edge ADTRG Controller INTAD...
Page 312: Configuration
CHAPTER 11 A/D CONVERTER 11.2 Configuration The A/D converter consists of the following hardware. Table 11-1. Configuration of A/D Converter Item Configuration Analog input 12 channels (ANI0 to ANI11) Registers Successive approximation register (SAR) A/D conversion result register (ADCR) A/D conversion result register H (ADCRH): only higher 8 bits can be read Control registers A/D converter mode register (ADM)
Page 313 CHAPTER 11 A/D CONVERTER (6) ANI0 to ANI11 pins These are analog input pins for the 12 channels of the A/D converter, and are used to input analog signals to be converted into digital signals. Pins other than ones selected as the analog input by the analog input channel specification register (ADS) can be used as input ports.
Page 314: Control Registers
CHAPTER 11 A/D CONVERTER 11.3 Control Registers The A/D converter is controlled by the following registers. • A/D converter mode register (ADM) • Analog input channel specification register (ADS) (1) A/D converter mode register (ADM) This register specifies the conversion time of the input analog signal to be converted into a digital signal, starting or stopping the conversion, and an external trigger.
Page 315 CHAPTER 11 A/D CONVERTER (2/2) Note 1 Note 2 ADPS Selection of Conversion Time + Stabilization time 288/f 216/f 168/f 120/f 96/f 72/f 60/f 48/f 288/f + 144/f 216/f + 108/f 168/f + 84/f 120/f + 60/f 96/f + 48/f 72/f + 36/f 60/f...
Page 316 CHAPTER 11 A/D CONVERTER Table 11-2. A/D Conversion Time Selection Conversion Time Selection ADPS Conversion Time + Stabilization Time 20 MHz 17 MHz 13.5 MHz 8 MHz 2 MHz Setting µ µ µ µ 14.4 16.9 21.3 36.0 288/f prohibited Setting µ...
Page 317 CHAPTER 11 A/D CONVERTER (2) Analog input channel specification register (ADS) ADS specifies the port for inputting the analog voltage to be converted into a digital signal. ADS is set by a 1-bit or 8-bit memory manipulation instruction. RESET input sets ADS to 00H. After reset: Address: FFFFF3C2H ADS3...
Page 318: Operation
CHAPTER 11 A/D CONVERTER 11.4 Operation 11.4.1 Basic operation <1> Select one channel whose analog signal is to be converted into a digital signal by using the analog input channel specification register (ADS). <2> The sample & hold circuit samples the voltage input to the selected analog input channel. <3>...
Page 319 CHAPTER 11 A/D CONVERTER Figure 11-2. Basic Operation of A/D Converter Conversion time Sampling time Operation of Sampling A/D conversion A/D converter Conversion Undefined result Conversion ADCR result INTAD A/D conversion is successively executed until bit 7 (ADCS) of the A/D converter mode register (ADM) is reset to 0 by software.
Page 320: Input Voltage And Conversion Result
CHAPTER 11 A/D CONVERTER 11.4.2 Input voltage and conversion result The analog voltages input to the analog input pins (ANI0 to ANI11) and the result of the A/D conversion (contents of the A/D conversion result register (ADCR)) are related as follows. ×...
Page 321: A/D Converter Operation Mode
CHAPTER 11 A/D CONVERTER 11.4.3 A/D converter operation mode In this mode one of the analog input channels ANI0 to ANI11 is selected by the analog input channel specification register (ADS) and A/D conversion is executed. The A/D conversion can be started in the following two ways. •...
Page 322 CHAPTER 11 A/D CONVERTER (1) A/D conversion by hardware start A/D conversion is on standby if bit 6 (TRG) and bit 7 (ADCS) of the A/D converter mode register (ADM) are set to 1. When an external trigger signal is input, the A/D converter starts converting the voltage applied to the analog input pin specified by the analog input channel specification register (ADS) into a digital signal.
Page 323 CHAPTER 11 A/D CONVERTER (2) A/D conversion by software start If bit 6 (TRG) of A/D converter mode register 1 (ADM1) is set to 0 and bit 7 (ADCS) is set to 1, the A/D converter starts converting the voltage applied to the analog input pin specified by the analog input channel specification register (ADS) into a digital signal.
Page 324: Notes On Using A/D Converter
CHAPTER 11 A/D CONVERTER 11.5 Notes on Using A/D Converter (1) Current consumption in standby mode The A/D converter stops operation in the IDLE/software STOP mode (operable in the HALT mode). At this time, the current consumption of the A/D converter can be reduced by stopping the conversion (by resetting the bit 7 (ADCS) of the A/D converter mode register (ADM) to 0).
Page 325 CHAPTER 11 A/D CONVERTER (4) Countermeasures against noise To keep the resolution of 10 bits, prevent noise from being superimposed on the AV and ANI0 to ANI11 pins. The higher the output impedance of the analog input source, the heavier the influence of noise. To lower noise, connecting an external capacitor as shown in Figure 11-6 is recommended.
Page 326 CHAPTER 11 A/D CONVERTER (7) Interrupt request flag (ADIF) The interrupt request flag (ADIF) is not cleared even if the contents of the analog input channel specification register (ADS) are changed. If the analog input pin is changed during conversion, therefore, the result of the A/D conversion of the preceding analog input signal and the conversion end interrupt request flag may be set immediately before ADS is rewritten.
Page 327 CHAPTER 11 A/D CONVERTER (8) AV The AV pin is the power supply pin of the analog circuit, and also supplies power to the input circuit of ANI0 to ANI11. Even in an application where a backup power supply is used, therefore, be sure to apply the same voltage as the V pin to the AV pin as shown in Figure 11-8.
Page 328: How To Read A/D Converter Characteristics Table
CHAPTER 11 A/D CONVERTER 11.6 How to Read A/D Converter Characteristics Table Here, special terms unique to the A/D converter are explained. (1) Resolution This is the minimum analog input voltage that can be identified. That is, the percentage of the analog input voltage per bit of digital output is called 1LSB (Least Significant Bit).
Page 329 CHAPTER 11 A/D CONVERTER (3) Quantization error When analog values are converted to digital values, a ±1/2LSB error naturally occurs. In an A/D converter, an analog input voltage in a range of ±1/2LSB is converted to the same digital code, so a quantization error cannot be avoided.
Page 330 CHAPTER 11 A/D CONVERTER (5) Full-scale error This shows the difference between the actual measurement value of the analog input voltage and the theoretical value (3/2LSB) when the digital output changes from 1……110 to 1……111. Figure 11-12. Full-Scale Error Full-scale error –3 –2 –1...
Page 331 CHAPTER 11 A/D CONVERTER (7) Integral linearity error This shows the degree to which the conversion characteristics deviate from the ideal linear relationship. It expresses the maximum value of the difference between the actual measurement value and the ideal straight line when the zero-scale error and full-scale error are 0.
Page 332: Chapter 12 Dma Functions
CHAPTER 12 DMA FUNCTIONS 12.1 Functions The V850/SA1 incorporates a three channel DMA (Direct Memory Access) controller (DMAC) that controls and executes DMA transfer. The DMAC transfers data between internal RAM and on-chip peripheral I/O based on a trigger from the on-chip peripheral I/O (serial interface, timer/counter, or A/D converter).
Page 333: Configuration
CHAPTER 12 DMA FUNCTIONS 12.3 Configuration Figure 12-1. Block Diagram of DMAC DMA transfer trigger DMA transfer (INT signal) request control DMA peripheral I/O address DMA channel control register n (DIOAn) register n (DCHCn) DMA byte count DMA transfer acknowledge signal register n (DBCn) Channel controller DMA internal RAM address...
Page 334: Control Registers
CHAPTER 12 DMA FUNCTIONS 12.4 Control Registers (1) DMA peripheral I/O address registers 0 to 2 (DIOA0 to DIOA2) These registers are used to set the peripheral I/O register address for DMA channel n. These registers are can be read/written in 16-bit units. After reset: Undefined Address: DIOA0...
Page 335 CHAPTER 12 DMA FUNCTIONS The correspondence between DRAn setting value and internal RAM area is shown below. µ PD703014A, 703014AY, 703014B, 703014BY, 703015A, 703015AY, 703015B, 703015BY, 70F3015B, 70F3015BY Set the DRAn register to a value in the range of 0000H to 0FFFH (n = 0 to 2). Setting is prohibited for values between 1000H and 1FFFH.
Page 336 CHAPTER 12 DMA FUNCTIONS µ PD703017A, 703017AY, 70F3017A, 70F3017AY Set the DRAn register to a value in the range of 0000H to 0FFFH or 1000H to 1FFFH (n = 0 to 2). Figure 12-3. Correspondence Between DRAn Setting Value and Internal RAM (8 KB) (DRAn setting value) xxFFFFFFH On-chip peripheral...
Page 337 CHAPTER 12 DMA FUNCTIONS (3) DMA byte count registers 0 to 2 (DBC0 to DBC2) These are 8-bit registers that are used to set the number of transfers for DMA channel n. The remaining number of transfers is retained during the DMA transfers. A value of 1 is decremented once per transfer if the transfer is a byte (8-bit) transfer, and a value of 2 is decremented once per transfer if the transfer is a 16-bit transfer.
Page 338 CHAPTER 12 DMA FUNCTIONS (4) DMA channel control registers 0 to 2 (DCHC0 to DCHC2) These registers are used to control the DMA transfer operation mode for DMA channel n. These registers are can be read/written in 1-bit or 8-bit units. (1/2) After reset: Address:...
Page 339 CHAPTER 12 DMA FUNCTIONS (2/2) Note 1 TDIRn Transfer Direction Control Between Peripheral I/O and Internal RAM From internal RAM to peripheral I/O From peripheral I/O to internal RAM Note 1 Control of Transfer Data Size for DMA Transfer 8-bit transfer 16-bit transfer Note 2 Control of DMA Transfer Enable/Disable Status...
Page 340: Operation
CHAPTER 12 DMA FUNCTIONS 12.5 Operation The DMA controller of the V850/SA1 supports only the single transfer mode. When a DMA transfer request (INTxxx: refer to 12.4 (4) DMA channel control registers 0 to 2 (DCHC0 to DCHC2)) is generated during CPU processing, a single DMA transfer is started after the current CPU processing has finished.
Page 341: Cautions
CHAPTER 12 DMA FUNCTIONS Figure 12-5. Processing When Transfer Requests DMA0 to DMA2 Are Generated Simultaneously DMA0 DMA1 DMA2 processing processing processing processing processing processing processing Transfer requests DMA0 to DMA2 are generated simultaneously DMA operation stops only in the IDLE/software STOP mode. In the HALT mode, DMA operation continues, DMA also operates during the bus hold period and after access to external memory.
Page 342: Chapter 13 Real-Time Output Function (Rto)
CHAPTER 13 REAL-TIME OUTPUT FUNCTION (RTO) 13.1 Function The V850/SA1 incorporates a real-time output function that transfers preset data to real-time output buffer registers (RTBL, RTBH), and then transfers this data with hardware to an external device via the output latches, upon the occurrence of an external interrupt or external trigger.
Page 343: Configuration
CHAPTER 13 REAL-TIME OUTPUT FUNCTION (RTO) 13.3 Configuration Figure 13-1. Block Diagram of RTO Internal bus Real-time output port control register (RTPC) RTPOE RTPEG BYTE EXTR RTPTRG Real-time output Real-time output Output trigger buffer register, buffer register, INTTM4 controller higher 4 bits lower 4 bits (RTBH) (RTBL)
Page 344 CHAPTER 13 REAL-TIME OUTPUT FUNCTION (RTO) (1) Real-time output buffer registers (RTBL, RTBH) RTBL and RTBH are 4-bit registers that hold output data in advance. These registers are mapped to independent addresses in the special function register (SFR) area as shown in Figure 13-2.
Page 345: Control Registers
CHAPTER 13 REAL-TIME OUTPUT FUNCTION (RTO) 13.4 Control Registers RTO is controlled by using the following two registers. • Real-time output port mode register (RTPM) • Real-time output port control register (RTPC) (1) Real-time output port mode register (RTPM) This register selects real-time output port mode or port mode in 1-bit units. RTPM is set by a 1-bit or 8-bit memory manipulation instruction.
Page 346 CHAPTER 13 REAL-TIME OUTPUT FUNCTION (RTO) (2) Real-time output port control register (RTPC) This register sets the operation mode and output trigger of the real-time output port. The relationship between the operation mode and output trigger of the real-time output port is as shown in Table 13- RTPC is set by a 1-bit or 8-bit memory manipulation instruction.
Page 347: Usage
CHAPTER 13 REAL-TIME OUTPUT FUNCTION (RTO) 13.5 Usage (1) Disable the real-time output operation. Clear bit 7 (RTPOE) of the real-time output port control register (RTPC) to 0. (2) Initialization (i) Set the initial value to the output latch of port 10. (ii) Set the PM10 register to output mode.
Page 348: Operation
CHAPTER 13 REAL-TIME OUTPUT FUNCTION (RTO) 13.6 Operation If the real-time output operation is enabled by setting bit 7 (RTPOE) of the real-time output port control register (RTPC) to 1, the data of the real-time output buffer registers (RTBH and RTBL) is transferred to the output latch in Note synchronization with the generation of the selected transfer trigger (set by EXTR and BYTE ).
Page 349: Cautions
CHAPTER 13 REAL-TIME OUTPUT FUNCTION (RTO) 13.7 Cautions (1) Before performing initialization, disable the real-time output operation by clearing bit 7 (RTPOE) of the real-time output port control register (RTPC) to 0. (2) Once the real-time output operation is disabled (RTPOE = 0), be sure to set the same initial value as the output latch to the real-time output buffer registers (RTBH and RTBL) before enabling the real-time output operation (RTPOE = 0 →...
Page 350: Chapter 14 Port Function
CHAPTER 14 PORT FUNCTION 14.1 Port Configuration The V850/SA1 includes 85 I/O port pins configuring ports 0 to 12 (13 ports are input only). There are three power supplies for the I/O buffers; AV , BV , and V , which are described below.
Page 351 CHAPTER 14 PORT FUNCTION Port 0 includes the following alternate functions. Table 14-2. Alternate Functions of Port 0 Note Pin Name Alternate Function PULL Remark Port 0 Analog noise elimination INTP0 INTP1 INTP2 INTP3 INTP4/ADTRG Digital noise elimination INTP5/RTPTRG INTP6 Note Software pull-up function (1) Function of P0 pins Port 0 is an 8-bit I/O port for which I/O settings can be controlled in 1-bit units.
Page 352 CHAPTER 14 PORT FUNCTION Cautions 1. If the input pulse width is 2 to 3 clocks, whether it will be detected as a valid edge or eliminated as noise is undefined. 2. To ensure correct detection of pulses as valid edges, constant-level input is required for 3 clocks or more.
Page 353 CHAPTER 14 PORT FUNCTION (c) Rising edge specification register 0 (EGP0) EGP0 can be read/written in 1-bit or 8-bit units. After reset: Address: FFFFF0C0H EGP0 EGP07 EGP06 EGP05 EGP04 EGP03 EGP02 EGP01 EGP00 EGP0n Control of Rising Edge Detection (n = 0 to 7) Interrupt request signal did not occur at rising edge Interrupt request signal occurred at rising edge Remark...
Page 354 CHAPTER 14 PORT FUNCTION (4) Block diagram (port 0) Figure 14-1. Block Diagram of P00 to P07 P-ch PU0n Alternate function Selector P00/NMI P01/INTP0 PORT P02/INTP1 P03/INTP2 Output latch (P0n) P04/INTP3 P05/INTP4/ADTRG P06/INTP5/RTPTRG P07/INTP6 PM0n Remarks 1. PU0: Pull-up resistor option register 0 PM0: Port 0 mode register RD: Read signal of port 0 WR: Write signal of port 0...
Page 355: Port 1
CHAPTER 14 PORT FUNCTION 14.2.2 Port 1 Port 1 is a 6-bit I/O port for which I/O settings can be controlled in 1-bit units. A pull-up resistor can be connected in 1-bit units (software pull-up function). Bits 0, 1, 2, 4, and 5 are selectable as normal outputs or N-ch open-drain outputs. After reset: 00H Address: FFFFF002H Control of Output Data (in Output Mode) (n = 0 to 5)
Page 356 CHAPTER 14 PORT FUNCTION (1) Function of P1 pins Port 1 is a 6-bit I/O port for which I/O settings can be controlled in 1-bit units. I/O settings are controlled via the port 1 mode register (PM1). In output mode, the values set to each bit are output to port 1 (P1). The port 1 function register (PF1) can be used to specify whether P10 to P12, P14, and P15 are normal outputs or N-ch open-drain outputs.
Page 357 CHAPTER 14 PORT FUNCTION (b) Pull-up resistor option register 1 (PU1) PU1 can be read/written in 1-bit or 8-bit units. After reset: 00H Address: FFFFF082H PU15 PU14 PU13 PU12 PU11 PU10 PU1n Control of On-Chip Pull-Up Resistor Connection (n = 0 to 5) Do not connect Connect (c) Port 1 function register (PF1)
Page 358 CHAPTER 14 PORT FUNCTION (3) Block diagrams (port 1) Figure 14-2. Block Diagram of P10, P12, and P15 P-ch PU1n Alternate function Selector PF1n PORT Output latch (P1n) P-ch Note P10/SI0/SDA Note P12/SCK0/SCL P15/SCK1/ASCK0 N-ch PM1n Alternate function µ Note Available only in the PD703014AY, 703014BY, 703015AY, 703015BY, 703017AY, 70F3015BY, and 70F3017AY Remarks...
Page 359 CHAPTER 14 PORT FUNCTION Figure 14-3. Block Diagram of P11 and P14 P-ch PU1n Selector PF1n PORT Output latch (P1n) P-ch P11/SO0 P14/SO1/TXD0 N-ch PM1n Alternate function Remarks 1. PU1: Pull-up resistor option register 1 PF1: Port 1 function register PM1: Port 1 mode register RD: Read signal of port 1 WR: Write signal of port 1...
Page 360 CHAPTER 14 PORT FUNCTION Figure 14-4. Block Diagram of P13 P-ch PU13 Alternate function Selector PORT Output latch P13/SI1/RXD0 (P13) PM13 Remark PU1: Pull-up resistor option register 1 PM1: Port 1 mode register RD: Read signal of port 1 WR: Write signal of port 1 User’s Manual U12768EJ4V1UD...
Page 361: Port 2
CHAPTER 14 PORT FUNCTION 14.2.3 Port 2 Port 2 is an 8-bit I/O port for which I/O settings can be controlled in 1-bit units. A pull-up resistor can be connected in 1-bit units (software pull-up function). P21 and P22 are selectable as normal outputs or N-ch open-drain outputs. When P26 and P27 are used as the TI2/TI3 pins, noise is eliminated from these pins by a digital noise eliminator.
Page 362 CHAPTER 14 PORT FUNCTION (1) Function of P2 pins Port 2 is an 8-bit I/O port for which I/O settings can be controlled in 1-bit units. I/O settings are controlled via the port 2 mode register (PM2). In output mode, the values set to each bit are output to port 2 (P2). The port 2 function register (PF2) can be used to specify whether P21 and P22 are normal outputs or N-ch open-drain outputs.
Page 363 CHAPTER 14 PORT FUNCTION (b) Pull-up resistor option register 2 (PU2) PU2 can be read/written in 1-bit or 8-bit units. After reset: Address: FFFFF084H PU27 PU26 PU25 PU24 PU23 PU22 PU21 PU20 PU2n Control of On-Chip Pull-Up Resistor Connection (n = 0 to 7) Do not connect Connect (c) Port 2 function register (PF2)
Page 364 CHAPTER 14 PORT FUNCTION (3) Block diagrams (port 2) Figure 14-5. Block Diagram of P20, P23, and P25 P-ch PU2n Alternate function Selector PORT P20/SI2 Output latch P23/RXD1 (P2n) P25/ASCK1 PM2n Remarks 1. PU2: Pull-up resistor option register 2 PM2: Port 2 mode register RD: Read signal of port 2 WR: Write signal of port 2 2.
Page 365 CHAPTER 14 PORT FUNCTION Figure 14-6. Block Diagram of P21 P-ch PU21 Selector PF21 PORT Output latch P-ch (P21) P21/SO2 N-ch PM21 Alternate function Remark PU2: Pull-up resistor option register 2 PF2: Port 2 function register PM2: Port 2 mode register RD: Read signal of port 2 WR: Write signal of port 2 User’s Manual U12768EJ4V1UD...
Page 366 CHAPTER 14 PORT FUNCTION Figure 14-7. Block Diagram of P22 P-ch PU22 Alternate function Selector PF22 PORT Output latch (P22) P-ch P22/SCK2 N-ch PM22 Alternate function Remark PU2: Pull-up resistor option register 2 PF2: Port 2 function register PM2: Port 2 mode register RD: Read signal of port 2 WR: Write signal of port 2 User’s Manual U12768EJ4V1UD...
Page 367 CHAPTER 14 PORT FUNCTION Figure 14-8. Block Diagram of P24 P-ch PU24 Selector PORT Output latch (P24) P24/TXD1 PM24 Alternate function Remark PU2: Pull-up resistor option register 2 PM2: Port 2 mode register RD: Read signal of port 2 WR: Write signal of port 2 User’s Manual U12768EJ4V1UD...
Page 368 CHAPTER 14 PORT FUNCTION Figure 14-9. Block Diagram of P26 and P27 P-ch PU2n Alternate function Selector PORT Output latch P26/TI2/TO2 (P2n) P27/TI3/TO3 PM2n Alternate function Remarks 1. PU2: Pull-up resistor option register 2 PM2: Port 2 mode register RD: Read signal of port 2 WR: Write signal of port 2 2.
Page 369: Port 3
CHAPTER 14 PORT FUNCTION 14.2.4 Port 3 Port 3 is an 8-bit I/O port for which I/O settings can be controlled in 1-bit units. A pull-up resistor can be connected in 1-bit units (software pull-up function). When P36 and P37 are used as the TI4 and TI5 pins, noise is eliminated from these pins by a digital noise eliminator.
Page 370 CHAPTER 14 PORT FUNCTION (1) Function of P3 pins Port 3 is an 8-bit I/O port for which I/O settings can be controlled in 1-bit units. I/O settings are controlled via the port 3 mode register (PM3). In output mode, the values set to each bit are output to port 3 (P3). When using this port in input mode, the pin statuses can be read by reading P3.
Page 371 CHAPTER 14 PORT FUNCTION (3) Block diagrams (port 3) Figure 14-10. Block Diagram of P30 to P33 P-ch PU3n Alternate function Selector PORT P30/TI00 P31/TI01 Output latch (P3n) P32/TI10 P33/TI11 PM3n Remarks 1. PU3: Pull-up resistor option register 3 PM3: Port 3 mode register RD: Read signal of port 3 WR: Write signal of port 3 2.
Page 372 CHAPTER 14 PORT FUNCTION Figure 14-11. Block Diagram of P34 and P35 P-ch PU3n Selector PORT Output latch P34/TO0/A13 (P3n) P35/TO1/A14 PM3n Alternate function Remarks 1. PU3: Pull-up resistor option register 3 PM3: Port 3 mode register RD: Read signal of port 3 WR: Write signal of port 3 2.
Page 373 CHAPTER 14 PORT FUNCTION Figure 14-12. Block Diagram of P36 and P37 PU3n P-ch Alternate function Selector PORT Output latch P36/TI4/TO4/A15 (P3n) P37/TI5/TO5 PM3n Alternate function Remarks 1. PU3: Pull-up resistor option register 3 PM3: Port 3 mode register RD: Read signal of port 3 WR: Write signal of port 3 2.
Page 374: Ports 4 And 5
CHAPTER 14 PORT FUNCTION 14.2.5 Ports 4 and 5 Ports 4 and 5 are 8-bit I/O ports for which I/O settings can be controlled in 1-bit units. After reset: Address: FFFFF008H, FFFFF00AH (n = 4, 5) Control of Output Data (in Output Mode) (n = 4, 5, x = 0 to 7) Output 0 Output 1 Remark...
Page 375 CHAPTER 14 PORT FUNCTION (1) Functions of P4 and P5 pins Ports 4 and 5 are 8-bit I/O ports for which I/O settings can be controlled in 1-bit units. I/O settings are controlled via the port 4 mode register (PM4) and port 5 mode register (PM5). In output mode, the values set to each bit are output to ports 4 and 5 (P4 and P5).
Page 376 CHAPTER 14 PORT FUNCTION (3) Block diagram (port 4, port 5) Figure 14-13. Block Diagram of P40 to P47 and P50 to P57 Alternate function PORT Output latch (Pmn) Pmn/AD Alternate function PMmn I/O controller Remarks 1. PM4: Port 4 mode register PM5: Port 5 mode register MM: Memory expansion mode register RD: Read signals of ports 4 and 5...
Page 377: Port 6
CHAPTER 14 PORT FUNCTION 14.2.6 Port 6 Port 6 is a 6-bit I/O port for which I/O settings can be controlled in 1-bit units. After reset: Address: FFFFF00CH Control of Output Data (in Output Mode) (n = 0 to 5) Output 0 Output 1 Remark...
Page 378 CHAPTER 14 PORT FUNCTION (2) Control register (a) Port 6 mode register (PM6) PM6 can be read/written in 1-bit or 8-bit units. After reset: Address: FFFFF02CH PM65 PM64 PM63 PM62 PM61 PM60 PM6n Control of I/O Mode (n = 0 to 5) Output mode Input mode (3) Block diagram (port 6)
Page 379: Ports 7 And 8
CHAPTER 14 PORT FUNCTION 14.2.7 Ports 7 and 8 Port 7 is an 8-bit input-only port and port 8 is a 4-bit input-only port. Both ports are read-only and are accessible in 8-bit or 1-bit units. After reset: Undefined Address: FFFFF00EH Pin Level (n = 0 to 7) Read pin level of bit n After reset: Undefined...
Page 380 CHAPTER 14 PORT FUNCTION (1) Functions of P7 and P8 pins Port 7 is an 8-bit input-only port and port 8 is a 4-bit input-only port. The pin statuses can be read by reading ports 7 and 8 (P7 and P8). Data cannot be written to P7 or P8. A software pull-up function is not implemented.
Page 381: Port 9
CHAPTER 14 PORT FUNCTION 14.2.8 Port 9 Port 9 is a 7-bit I/O port for which I/O settings can be controlled in 1-bit units. After reset: Address: FFFFF012H Control of Output Data (in Output Mode) (n = 0 to 6) Output 0 Output 1 Remark...
Page 382 CHAPTER 14 PORT FUNCTION (1) Function of P9 pins Port 9 is a 7-bit I/O port for which I/O settings can be controlled in 1-bit units. I/O settings are controlled via the port 9 mode register (PM9). In output mode, the values set to each bit are output to port 9 (P9). When using this port in input mode, the pin statuses can be read by reading P9.
Page 383 CHAPTER 14 PORT FUNCTION (3) Block diagrams (port 9) Figure 14-16. Block Diagram of P90 to P95 PORT P90/LBEN/WRL Output latch P91/UBEN (P9n) P92/R/W/WRH P93/DSTB/RD Alternate P94/ASTB function P95/HLDAK PM9n I/O controller Remarks 1. PM9: Port 9 mode register MM: Memory expansion mode register RD: Read signal of port 9 WR: Write signal of port 9 2.
Page 384 CHAPTER 14 PORT FUNCTION Figure 14-17. Block Diagram of P96 Alternate function PORT Output latch P96/HLDRQ (P96) PM96 I/O controller Remark PM9: Port 9 mode register MM: Memory expansion mode register RD: Read signal of port 9 WR: Write signal of port 9 User’s Manual U12768EJ4V1UD...
Page 385: Port 10
CHAPTER 14 PORT FUNCTION 14.2.9 Port 10 Port 10 is an 8-bit I/O port for which I/O settings can be controlled in 1-bit units. A pull-up resistor can be connected in 1-bit units (software pull-up function). The pins in this port are selectable as normal outputs or N-ch open-drain outputs. After reset: Address: FFFFF014H P107...
Page 386 CHAPTER 14 PORT FUNCTION (1) Function of P10 pins Port 10 is an 8-bit I/O port for which I/O settings can be controlled in 1-bit units. I/O settings are controlled via the port 10 mode register (PM10). In output mode, the values set to each bit are output to port 10 (P10). The port 10 function register (PF10) can be used to specify whether outputs are normal outputs or N-ch open-drain outputs.
Page 387 CHAPTER 14 PORT FUNCTION (b) Pull-up resistor option register 10 (PU10) PU10 can be read/written in 1-bit or 8-bit units. After reset: Address: FFFFF094H PU10 PU107 PU106 PU105 PU104 PU103 PU102 PU101 PU100 PU10n Control of On-Chip Pull-Up Resistor Connection (n = 0 to 7) Do not connect Connect (c) Port 10 function register (PF10)
Page 388 CHAPTER 14 PORT FUNCTION (3) Block diagram (port 10) Figure 14-18. Block Diagram of P100 to P107 PU10 P-ch PU10n Selector PF10 PF10n PORT Output latch (P10n) P-ch P10n/RTPn/A N-ch PM10 PM10n Alternate function Remarks 1. PU10: Pull-up resistor option register 10 PF10: Port 10 function register PM10: Port 10 mode register RD: Read signal of port 10...
Page 389: Port 11
CHAPTER 14 PORT FUNCTION 14.2.10 Port 11 Port 11 includes P114, which is an input-only port, and P110 to P113, which comprise an I/O port for which I/O settings can be controlled in 1-bit units. A pull-up resistor can be connected to bits 0 to 3 in 1-bit units (software pull- up function).
Page 390 CHAPTER 14 PORT FUNCTION (1) Function of P11 pins Port 11 is a 5-bit (total) port that includes P114, which is an input-only port, and P110 to P113, which comprise an I/O port for which I/O settings can be controlled in 1-bit units. In output mode, the values set to each bit (bit 0 to bit 3) are output to port 11 (P11).
Page 391 CHAPTER 14 PORT FUNCTION (3) Block diagrams (port 11) Figure 14-19. Block Diagram of P110 to P113 PU11 P-ch PU11n Selector PORT Output latch (P11n) P11n/A PM11 PM11n Alternate function Remarks 1. PU11: Pull-up resistor option register 11 PM11: Port 11 mode register RD: Read signal of port 11 WR: Write signal of port 11 2.
Page 392: Port 12
CHAPTER 14 PORT FUNCTION 14.2.11 Port 12 Port 12 is a 1-bit I/O port. After reset: Address: FFFFF018H PU12 P120 P120 Control of Output Data (in Output Mode) Output 0 Output 1 Remark In input mode: When port 12 (P12) is read, the pin levels at that time are read. Writing to P12 writes the values to that register.
Page 393 CHAPTER 14 PORT FUNCTION (2) Control registers (a) Port 12 mode register (PM12) PM12 can be read/written in 1-bit or 8-bit units. After reset: Address: FFFFF038H PM12 PM120 P120 Control of Input Mode Output mode Input mode (b) Port 12 mode control register (PMC12) PMC12 can be read/written in 1-bit or 8-bit units.
Page 394 CHAPTER 14 PORT FUNCTION (3) Block diagram (port 12) Figure 14-21. Block Diagram of P120 Alternate function PORT Output latch P120/WAIT (P120) PM12 PM120 PMC12 PMC120 Remark PM12: Port 12 mode register PMC12: Port 12 mode control register RD: Read signal of port 12 WR: Write signal of port 12 User’s Manual U12768EJ4V1UD...
Page 395: Setting When Port Pin Is Used As Alternate Function
CHAPTER 14 PORT FUNCTION 14.3 Setting When Port Pin Is Used as Alternate Function When a port pin is used for an alternate function, set the port n mode register (PM0 to PM6 and PM9 to PM12) and output latch as shown below. Table 14-13.
Page 396 CHAPTER 14 PORT FUNCTION Table 14-13. Setting When Port Pin Is Used as Alternate Function (2/3) Alternate Function PMnx Bit of Pnx Bit of Other Bits Pin Name PMn Register Pn Register (Register) Function Name  Input PM20 = 1 Setting not needed for P20 ...
Page 397 CHAPTER 14 PORT FUNCTION Table 14-13. Setting When Port Pin Is Used as Alternate Function (3/3) Alternate Function PMnx Bit of Pnx Bit of Other Bits Pin Name PMn Register Pn Register (Register) Function Name P50 to P57 AD8 to AD15 Setting not needed Setting not needed Refer to 3.4.6 (1) (MM)
Page 398: Operation Of Port Function
CHAPTER 14 PORT FUNCTION 14.4 Operation of Port Function The operation of a port differs depending on whether the port is in the input or output mode, as described below. 14.4.1 Writing data to I/O port (1) In output mode A value can be written to the output latch by using a transfer instruction.
Page 399: Chapter 15 Reset Function
CHAPTER 15 RESET FUNCTION 15.1 General When a low level is input to the RESET pin, a system reset is performed and the various on-chip hardware devices are reset to their initial settings. In addition, oscillation of the main clock is stopped during the reset period, although oscillation of the subclock continues.
Page 400: Chapter 16 Flash Memory
The following can be considered as the development environment and applications using flash memory. • Software can be altered after the V850/SA1 is solder-mounted on the target system. • Small scale production of various models is made easier by differentiating software.
Page 401: Writing By Flash Programmer
Writing can be performed either on-board or off-board by the dedicated flash programmer. (1) On-board programming The contents of the flash memory are rewritten after the V850/SA1 is mounted on the target system. Mount connectors, etc., on the target system to connect the dedicated flash programmer.
Page 402 CHAPTER 16 FLASH MEMORY Figure 16-1. Wiring Example of V850/SA1 Flash Writing Adapter (FA100GC-8EU) µ PD70F3015B, µ PD70F3015BY, µ PD70F3017A, µ PD70F3017AY Connect to GND. Connect to VDD. /RESET RESERVE/HS Remarks 1. Pins not described above should be handled according to the recommended connection of unused pins (refer to 2.4 Pin I/O Circuits and Recommended Connection of Unused Pins).
Page 403 CHAPTER 16 FLASH MEMORY Table 16-1. Wiring Table of V850/SA1 Flash Writing Adapter (FA-100GC-8EU) Flash Programmer When Using CSI0 + HS When Using CSI0 When Using UART0 (PG-FP3/PG-FP4) Connection Pin Signal Name Pin Function Pin Name Pin No. Pin Name Pin No.
Page 404 CHAPTER 16 FLASH MEMORY Figure 16-2. Wiring Example of V850/SA1 Flash Writing Adapter (FA-121F1-EA6) µ PD70F3017A, µ PD70F3017AY Connect to GND. Connect to VDD. /RESET RESERVE/HS Remarks 1. Pins not described above should be handled according to the recommended connection of unused pins (refer to 2.4 Pin I/O Circuits and Recommended Connection of Unused Pins).
Page 405 CHAPTER 16 FLASH MEMORY Table 16-2. Wiring Table of V850/SA1 Flash Writing Adapter (FA-121F1-EA6) Flash Programmer When Using CSI0 + HS When Using CSI0 When Using UART0 (PG-FP3/PG-FP4) Connection Pin Signal Name Pin Function Pin Name Pin No. Pin Name Pin No.
Page 406: Programming Environment
A host machine is required for controlling the dedicated flash programmer. UART0 or CSI0 is used for the interface between the dedicated flash programmer and the V850/SA1 to perform writing, erasing, etc. A dedicated program adapter (FA Series) is required for off-board writing.
Page 407 Figure 16-5. Communication with Dedicated Flash Programmer (CSI0) Axxxx Bxxxxx Cxxxxxx STATVE PG-FP4 RESET RESET V850/SA1 Dedicated flash programmer SCK0 (3) CSI0 + HS Serial clock: Up to 1 MHz (MSB first) Figure 16-6. Communication with Dedicated Flash Programmer (CSI0 + HS) Axxxx...
Page 408 The dedicated flash programmer outputs the transfer clock, and the V850/SA1 operates as a slave. When the PG-FP3 or PG-FP4 is used as the dedicated flash programmer, it generates the signals shown in Table 16-3 to the V850/SA1. For the details, refer to PG-FP3 User’s Manual (U13502E), or PG-FP4 User’s Manual (U15260E).
Page 409: Pin Connection
V pin. The following shows an example of the connection of V pin. Figure 16-7. Connection Example of V V850/SA1 Dedicated flash programmer connection pin Pull-down resistor (R 16.5.2 Serial interface pin The following shows the pins used by each serial interface.
Page 410 Dedicated flash programmer connection pin Other device Input pin In the flash memory programming mode, if the signal the V850/SA1 outputs affects the other device, isolate the signal on the other device side. V850/SA1 Dedicated flash programmer connection pin Other device...
Page 411: Reset Pin
When a reset signal is input from the user system in the flash memory programming mode, the programming operation will not be performed correctly. Therefore, do not input signals other than the reset signals from the dedicated flash programmer. Figure 16-10. Conflict of Signals (RESET Pin) V850/SA1 Conflict of signals Dedicated flash programmer connection pin RESET...
Page 412: Programming Method
Manipulate flash memory End? 16.6.2 Flash memory programming mode When rewriting the contents of the flash memory using the dedicated flash programmer, set the V850/SA1 in the flash memory programming mode. When switching modes, set V pin before releasing reset.
Page 413: Selection Of Communication Mode
The V850/SA1 communicates with the dedicated flash programmer by means of commands. The command sent from the dedicated flash programmer to the V850/SA1 is called a “command”. The response signal sent from the V850/SA1 to the dedicated flash programmer is called a “response command”.
Page 414: Resources Used
CHAPTER 16 FLASH MEMORY The following shows the commands for flash memory control of the V850/SA1. All of these commands are issued from the dedicated flash programmer, and the V850/SA1 performs the various processing corresponding to the commands. Table 16-6. Commands for Flash Memory Control...
Page 415: Flash Memory Programming By Self-Programming
16.7 Flash Memory Programming by Self-Programming The V850/SA1 supports a self-programming function to rewrite the flash memory using a user program. By using this function, the flash memory can be rewritten by a user application. This self-programming function can also be used to upgrade the program in the field.
Page 416: Self-Programming Function
(128 KB) 00000H 00000H Note Data is deleted in area units (128 KB). 16.7.2 Self-programming function The V850/SA1 provides self-programming functions, as shown below. By combining these functions, erasing/writing flash memory becomes possible. Table 16-8. Function List Type Function Name...
Page 417: Outline Of Self-Programming Interface
CHAPTER 16 FLASH MEMORY 16.7.3 Outline of self-programming interface To execute self-programming using the self-programming interface, the environmental conditions of the hardware and software for manipulating the flash memory must be satisfied. It is assumed that the self-programming interface is used in an assembly language. (1) Entry program This program is used to call the internal processing of the device.
Page 418 CHAPTER 16 FLASH MEMORY Figure 16-16. Example of Self-Programming Circuit Configuration = 3.3 ±0.3 V V850/SA1 IC for power supply OUTPUT INPUT = 7.8 ±0.3 V) 10 kΩ ON/OFF Output port ≥ 10 kΩ The voltage applied to the V pin must satisfy the following conditions.
Page 419: Software Environment
CHAPTER 16 FLASH MEMORY 16.7.5 Software environment The following conditions must be satisfied before using the entry program to call the device internal processing. Table 16-9. Software Environmental Conditions Item Description Location of entry Execute the entry program in memory other than the flash memory area. program The device internal processing cannot be directly called by the program that is executed on the flash memory.
Page 420: Self-Programming Function Number
CHAPTER 16 FLASH MEMORY 16.7.6 Self-programming function number To identify a self-programming function, the following numbers are assigned to the respective functions. These function numbers are used as parameters when the device internal processing is called. Table 16-10. Self-Programming Function Numbers Function No.
Page 421: Calling Parameters
CHAPTER 16 FLASH MEMORY 16.7.7 Calling parameters The arguments used to call the self-programming function are shown in the table below. In addition to these arguments, parameters such as the write time and erase time are set to the RAM parameters indicated by ep (r30). Table 16-11.
Page 422: Contents Of Ram Parameters
CHAPTER 16 FLASH MEMORY 16.7.8 Contents of RAM parameters Reserve the following 48-byte area in the internal RAM or external RAM for the RAM parameters, and set the parameters to be input. Set the base addresses of these parameters to ep (r30). Table 16-12.
Page 423: Errors During Self-Programming
CHAPTER 16 FLASH MEMORY 16.7.9 Errors during self-programming The following errors related to manipulation of the flash memory may occur during self-programming. An error occurs if the return value (r10) of each function is not 0. Table 16-13. Errors During Self-Programming Error Function Description...
Page 424: Area Number
CHAPTER 16 FLASH MEMORY 16.7.11 Area number The area numbers and memory map of the V850/SA1 are shown below. Figure 16-18. Area Configuration µ PD70F3015B, 70F3015BY 0 x 1 F F F F (End address of area 0) Area 0...
Page 425: Flash Programming Mode Control Register (Flpmc)
CHAPTER 16 FLASH MEMORY 16.7.12 Flash programming mode control register (FLPMC) The flash memory mode control register (FLPMC) is a register used to enable/disable writing to flash memory and to specify the self-programming mode. This register can be read/written in 8-bit or 1-bit units (the VPP bit (bit 2) is read-only). Cautions 1.
Page 426 CHAPTER 16 FLASH MEMORY The following sequence shows the data setting of the FLPMC register. <1> Disable DMA operation. <2> Set the PSW NP bit to 1 (interrupts disabled). <3> Write any 8-bit data in the command register (PRCMD). <4> Write the set data in the FLPMC register (using the following instructions). •...
Page 427: Calling Device Internal Processing
CHAPTER 16 FLASH MEMORY 16.7.13 Calling device internal processing This section explains the procedure to call the device internal processing from the entry program. Before calling the device internal processing, make sure that all the conditions of the hardware and software environments are satisfied and that the necessary arguments and RAM parameters have been set.
Page 428 CHAPTER 16 FLASH MEMORY (4) Program example An example of a program in which the entry program is executed as a subroutine is shown below. In this example, the return address is saved to the stack and then the device internal processing is called. This program must be located in memory other than the block 0 space and flash memory area.
Page 429 (5) Internal manipulation setup parameter µ If the self-programming mode is switched to the normal operation mode, the V850/SA1 must wait for 100 before it accesses the flash memory. In the program example in (4) above, the elapse of this wait time is ensured by setting ISETUP to “52”...
Page 430: Flow Of Erasing Flash Memory
CHAPTER 16 FLASH MEMORY 16.7.14 Flow of erasing flash memory The procedure to erase the flash memory is illustrated below. The processing of each function number must be executed in accordance with the specified calling procedure. Figure 16-19. Flow of Erasing Flash Memory Erase Set RAM parameter Mask interrupts...
Page 431: Successive Writing Flow
CHAPTER 16 FLASH MEMORY 16.7.15 Successive writing flow The procedure to write data all at once to the flash memory by using the function to successively write data in word units is illustrated below. The processing of each function number must be executed in accordance with the specified calling procedure.
Page 432: Internal Verify Flow
CHAPTER 16 FLASH MEMORY 16.7.16 Internal verify flow The procedure of internal verification is illustrated below. The processing of each function number must be executed in accordance with the specified calling procedure. Figure 16-21. Internal Verify Flow Internal verify Set RAM parameter Mask interrupts Set V voltage...
Page 433: Flow Of Acquiring Flash Information
CHAPTER 16 FLASH MEMORY 16.7.17 Flow of acquiring flash information The procedure to acquire the flash information is illustrated below. The processing of each function number must be executed in accordance with the specified calling procedure. Figure 16-22. Flow of Acquiring Flash Information Acquiring flash information Set RAM parameter...
Page 434: Self-Programming Library
CHAPTER 16 FLASH MEMORY 16.7.18 Self-programming library The V850 Series Flash Memory Self Programming Library User’s Manual is available for reference when executing self-programming. In this manual, the library uses the self-programming interface of the V850 Series and can be used in C as a utility and as part of the application program.
Page 435 CHAPTER 16 FLASH MEMORY The configuration of the self-programming library is outlined below. Figure 16-24. Outline of Self-Programming Library Configuration Application program C interface Self-programming library Entry program RAM parameter Self-programming interface Device internal processing Flash memory manipulation Flash memory User’s Manual U12768EJ4V1UD...
Page 436: Chapter 17 Electrical Specifications
CHAPTER 17 ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings (T = 25°C, V = 0 V) Parameter Symbol Conditions Ratings Unit Supply voltage –0.5 to +4.6 Notes 1, 2 –0.5 to +8.5 –0.5 to +4.6 –0.5 to +4.6 –0.5 to +0.5 –0.5 to +0.5 –0.5 to +0.5 Note 6 Input voltage...
Page 437 CHAPTER 17 ELECTRICAL SPECIFICATIONS µ Notes 1. PD70F3015B, 70F3015BY, 70F3017A, and 70F3017AY only Make sure that the following conditions of the V voltage application timing are satisfied when programming flash memory. • When supply voltage rises µ must exceed V s or more after V reached the lower-limit value (2.7 V) of the operating voltage range (see “a”...
Page 438 CHAPTER 17 ELECTRICAL SPECIFICATIONS Cautions 1. Do not directly connect the output (or I/O) pins of IC products to each other, or to V and GND. Open-drain pins or open-connector pins, however, can be directly connected to each other. Direct connection of the output pins between an IC product and an external circuit is possible, if the output pins can be set to the high-impedance state and the output timing of the external circuit is designed to avoid output conflict.
Page 439 = 2.7 to 3.6 V = 3.0 to 3.6 V Cautions 1. Connect the high-speed CMOS inverter as close as possible to the X1 pin. 2. Sufficiently evaluate the matching between the V850/SA1 and the high-speed CMOS inverter. User’s Manual U12768EJ4V1UD...
Page 440 Unit Input frequency = 2.7 to 3.6 V 32.768 Cautions 1. Connect the high-speed CMOS inverter as close as possible to the XT2 pin. 2. Sufficiently evaluate the matching between the V850/SA1 and the high-speed CMOS inverter. User’s Manual U12768EJ4V1UD...
Page 441 CHAPTER 17 ELECTRICAL SPECIFICATIONS DC Characteristics (1) Operating Conditions (T = –40 to +85°C, V = AV = BV = 2.7 to 3.6 V, V = AV = BV = 0 V) (1/2) Parameter Symbol Conditions MIN. TYP. MAX. Unit Input voltage, high Pins other than below 0.7V...
Page 442 CHAPTER 17 ELECTRICAL SPECIFICATIONS (1) Operating conditions (T = –40 to +85°C, V = AV = BV = 2.7 to 3.6 V, V = AV = BV = 0 V) (2/2) Parameter Symbol Conditions MIN. TYP. MAX. Unit µ PD703014A, Supply Normal = 17 MHz...
Page 443 CHAPTER 17 ELECTRICAL SPECIFICATIONS (2) Operating Conditions (T = –40 to +85°C, V = AV = BV = 3.0 to 3.6 V, V = AV = BV = 0 V) (1/2) Parameter Symbol Conditions MIN. TYP. MAX. Unit Input voltage, high Pins other than below 0.7V Note 1...
Page 444 CHAPTER 17 ELECTRICAL SPECIFICATIONS (2) Operating conditions (T = –40 to +85°C, V = AV = BV = 3.0 to 3.6 V, V = AV = BV = 0 V) (2/2) Parameter Symbol Conditions MIN. TYP. MAX. Unit µ PD703014A, Supply Normal = 20 MHz...
Page 445 ILDR at rising edge) Note V = 2.7 V indicates the minimum operating voltage of the V850/SA1 (when f = 17 MHz). Caution Shifting to STOP mode and restoring from STOP mode must be performed at V = 2.7 V min.
Page 446 CHAPTER 17 ELECTRICAL SPECIFICATIONS AC Characteristics AC test input measurement points (1) P11, P14, P21, P24, P34, P35, P40 to P47, P50 to P57, P60 to P65, P90 to P96, P100 to P107, P110 to P113, P120, and their alternate-function pins 0.7V 0.7V Point of measurement...
Page 447 CHAPTER 17 ELECTRICAL SPECIFICATIONS Clock Timing (1) Operating Conditions (T = –40 to +85°C, V = AV = BV = 2.7 to 3.6 V, V = AV = BV = 0 V, = 50 pF) Parameter Symbol Conditions MIN. MAX. Unit X1 input cycle <1>...
Page 448 CHAPTER 17 ELECTRICAL SPECIFICATIONS Clock Timing <1> <2> <3> X1, XT1 (input) <4> <5> <6> <7> <8> CLKOUT (output) <9> <10> Timing of pins other than CLKOUT, ports 4, 5, 6, and 9 = –40 to +85°C, V = AV = BV = 2.7 to 3.6 V, V = AV...
Page 449 CHAPTER 17 ELECTRICAL SPECIFICATIONS Bus Timing (CLKOUT Asynchronous) = –40 to +85°C, V = AV = BV = 2.7 to 3.6 V, V = AV = BV = 0 V, C = 50 pF) Parameter Symbol Conditions MIN. MAX. Unit Address setup time (to ASTB↓) <13>...
Page 450 CHAPTER 17 ELECTRICAL SPECIFICATIONS Bus Timing (CLKOUT Synchronous) = –40 to +85°C, V = AV = BV = 2.7 to 3.6 V, V = AV = BV = 0 V, C = 50 pF) Parameter Symbol Conditions MIN. MAX. Unit Delay time from CLKOUT↑...
Page 451 CHAPTER 17 ELECTRICAL SPECIFICATIONS Read Cycle (CLKOUT Synchronous/Asynchronous, 1 Wait) CLKOUT (output) <41> A16 to A21 (output), A1 to A15 (output), Note <16> <45> <46> <42> Hi-Z AD0 to AD15 (I/O) Address Data <43> <43> <14> <13> <19> ASTB (output) <24>...
Page 452 CHAPTER 17 ELECTRICAL SPECIFICATIONS Write Cycle (CLKOUT Synchronous/Asynchronous, 1 Wait) CLKOUT (output) <41> A16 to A21 (output), A1 to A15 (output), Note <47> AD0 to AD15 (I/O) Address Data <43> <43> <13> <14> ASTB (output) <24> <21> <44> <44> <25> <18>...
Page 453 CHAPTER 17 ELECTRICAL SPECIFICATIONS Bus Hold CLKOUT (output) <50> <50> <51> <36> HLDRQ (input) <53> <53> <39> <40> HLDAK (output) <37> <38> <52> Hi-Z A16 to A19 (output), Note A1 to A15 (output) Data Hi-Z AD0 to AD15 (I/O) Hi-Z ASTB (output) Hi-Z DSTB (output), RD (output),...
Page 454 CHAPTER 17 ELECTRICAL SPECIFICATIONS Reset/Interrupt Timing = –40 to +85°C, V = AV = BV = 2.7 to 3.6 V, V = AV = BV = 0 V, C = 50 pF) Parameter Symbol Conditions MIN. MAX. Unit RESET high-level width <54>...
Page 455 CHAPTER 17 ELECTRICAL SPECIFICATIONS TIn Input Timing = –40 to +85°C, V = AV = BV = 2.7 to 3.6 V, V = AV = BV = 0 V, C = 50 pF) Parameter Symbol Conditions MIN. MAX. Unit Note TIn0, TIn1 high-level width <60>...
Page 456 CHAPTER 17 ELECTRICAL SPECIFICATIONS CSI Timing (1) Master mode (T = –40 to +85°C, V = AV = BV = 2.7 to 3.6 V, V = AV = BV = 0 V, C = 50 pF) Parameter Symbol Conditions MIN. MAX.
Page 457 CHAPTER 17 ELECTRICAL SPECIFICATIONS UART Timing (T = –40 to +85°C, V = AV = BV = 2.7 to 3.6 V, V = AV = BV = 0 V, C = 50 pF) Parameter Symbol Conditions MIN. MAX. Unit ASCKn cycle time <67>...
Page 458 CHAPTER 17 ELECTRICAL SPECIFICATIONS µ C Bus Mode ( PD703014AY, 703014BY, 703015AY, 703015BY, 703017AY, 70F3015BY, 70F3017AY only) = –40 to +85°C, V = AV = BV = 2.7 to 3.6 V, V = AV = BV = 0 V, C = 50 pF) Parameter Symbol...
Page 459 CHAPTER 17 ELECTRICAL SPECIFICATIONS µ C Bus Mode ( PD703014AY, 703014BY, 703015AY, 703015BY, 703017AY, 70F3015BY, 70F3017AY only) <72> <73 SCL (I/O) <74> <78> <77> <75> <76> <71> <80> <79> <71> SDA (I/O) <70> <77> <78> Stop Start Restart Stop condition condition condition condition...
Page 460 CHAPTER 17 ELECTRICAL SPECIFICATIONS Flash Memory Programming Mode µ PD70F3015B, 70F3015BY, 70F3017A, 70F3017AY only) Write/erase characteristics (T = 0 to 85°C, V = AV = BV = 3.0 to 3.6 V, V = AV = BV = 0 V) Parameter Symbol Conditions MIN.
Page 461 CHAPTER 17 ELECTRICAL SPECIFICATIONS Notes 9. The versions that guarantee 20 rewrites can be distinguished from the versions that guarantee 100 rewrites according to the product or the lot number stamped on the package (xxxx indicates the four-digit number or symbol for internal management). µ...
Page 462: Chapter 18 Package Drawings
CHAPTER 18 PACKAGE DRAWINGS 100-PIN PLASTIC LQFP (FINE PITCH) (14x14) detail of lead end NOTE ITEM MILLIMETERS Each lead centerline is located within 0.08 mm of 16.00±0.20 its true position (T.P.) at maximum material condition. 14.00±0.20 14.00±0.20 16.00±0.20 1.00 1.00 0.22 +0.05 −0.04 0.08...
Page 463 CHAPTER 18 PACKAGE DRAWINGS 121-PIN PLASTIC FBGA (12x12) N M L K J H G F E D C B A INDEX MARK φ φ ITEM MILLIMETERS 12.00±0.10 12.00±0.10 0.20 1.48±0.10 0.35±0.06 1.13 0.80 0.50 +0.05 −0.10 0.08 0.10 0.20 1.20 1.20 P121F1-80-EA6...
Page 464: Chapter 19 Recommended Soldering Conditions
CHAPTER 19 RECOMMENDED SOLDERING CONDITIONS The V850/SA1 should be soldered and mounted under the following recommended conditions. For soldering methods and conditions other than those recommended below, consult an NEC Electronics sales representative. For technical information, see the following website.
Page 465 CHAPTER 19 RECOMMENDED SOLDERING CONDITIONS Table 19-1. Surface Mounting Type Soldering Conditions (2/4) µ PD70F3017AGC-8EU: 100-pin plastic LQFP (fine pitch) (14 × 14) µ PD70F3017AYGC-8EU: 100-pin plastic LQFP (fine pitch) (14 × 14) Soldering Soldering Conditions Recommended Method Condition Symbol Infrared reflow Package peak temperature: 235°C, Time: 30 seconds max.
Page 466 CHAPTER 19 RECOMMENDED SOLDERING CONDITIONS Table 19-1. Surface Mounting Type Soldering Conditions (3/4) µ PD703015BGC-xxx-8EU-A: 100-pin plastic LQFP (fine pitch) (14 × 14) µ PD703015BYGC-xxx-8EU-A: 100-pin plastic LQFP (fine pitch) (14 × 14) µ PD703017AYGC-xxx-8EU-A: 100-pin plastic LQFP (fine pitch) (14 × 14) µ...
Page 467 CHAPTER 19 RECOMMENDED SOLDERING CONDITIONS Table 19-1. Surface Mounting Type Soldering Conditions (4/4) µ PD703014AF1-×××-EA6-A: 121-pin plastic FBGA (12 × 12) µ PD703014AYF1-×××-EA6-A: 121-pin plastic FBGA (12 × 12) µ PD703014BF1-×××-EA6-A: 121-pin plastic FBGA (12 × 12) µ PD703015AF1-×××-EA6-A: 121-pin plastic FBGA (12 × 12) µ...
Page 468: Appendix A Notes On Target System Design
APPENDIX A NOTES ON TARGET SYSTEM DESIGN The following shows a diagram of the connection conditions between the in-circuit emulator option board and conversion connector. Design your system making allowances for conditions such as the shape of parts mounted on the target system as shown below.
Page 469 APPENDIX A NOTES ON TARGET SYSTEM DESIGN Figure A-2. 121-Pin Plastic FBGA (12 × 12) Side view In-circuit emulator In-circuit emulator IE-703002-MC option board IE-703017-MC-EM1 Conversion adapter 167 mm CSICE121A1312N02 CSPACK121A1312N02 Target system Top view IE-703002-MC Target system Pin 1 position IE-703017-MC-EM1 CSPACK121A1312N02, CSICE121A1312N02...
Page 470: Appendix B Register Index
APPENDIX B REGISTER INDEX (1/5) Symbol Name Unit Page ADCR A/D conversion result register ADCRH A/D conversion result register H ADIC Interrupt control register INTC 122 to 124 A/D converter mode register Analog input channel specification register ASIM0 Asynchronous serial interface mode register 0 UART ASIM1 Asynchronous serial interface mode register 1...
Page 471 APPENDIX B REGISTER INDEX (2/5) Symbol Name Unit Page CSIS0 Serial clock select register 0 CSIS1 Serial clock select register 1 CSIS2 Serial clock select register 2 DBC0 DMA byte counter register 0 DMAC DBC1 DMA byte counter register 1 DMAC DBC2 DMA byte counter register 2...
Page 472 APPENDIX B REGISTER INDEX (3/5) Symbol Name Unit Page Port 10 Port Port 11 Port Port 12 Port Port 2 Port Port 3 Port Port 4 Port Port 5 Port Port 6 Port Port 7 Port Port 8 Port Port 9 Port Processor clock control register Port 1 function register...
Page 473 APPENDIX B REGISTER INDEX (4/5) Symbol Name Unit Page PRM1 Prescaler mode register 1 PRM11 Prescaler mode register 11 Power save control register Program status word Pull-up resistor option register 0 Port Pull-up resistor option register 1 Port PU10 Pull-up resistor option register 10 Port PU11 Pull-up resistor option register 11...
Page 474 APPENDIX B REGISTER INDEX (5/5) Symbol Name Unit Page TCL51 Timer clock select register 51 16-bit timer register 0 16-bit timer register 1 8-bit counter 2 TM23 16-bit counter 23 (when TM2 and TM3 are connected in cascade) 8-bit counter 3 8-bit counter 4 TM45 16-bit counter 45 (when TM4 and TM5 are connected in cascade)
Page 475: Appendix C List Of Instruction Sets
APPENDIX C LIST OF INSTRUCTION SETS • How to read instruction set list This column shows the instruction group. Instructions are divided into each instruction group and described. This column shows the instruction mnemonic. This column shows the instruction operand (refer to Table C-1). This column shows the instruction code (opcode) in binary format.
Page 476 APPENDIX C LIST OF INSTRUCTION SETS Table C-2. Symbols Used for Opcode Symbol Description 1-bit data of code that specifies reg1 or regID 1-bit data of code that specifies reg2 1-bit data of displacement 1-bit data of immediate data cccc 4-bit data that indicates condition code 3-bit data that specifies bit number Table C-3.
Page 477 APPENDIX C LIST OF INSTRUCTION SETS Table C-4. Symbols Used for Flag Operation Symbol Description (blank) Not affected Cleared to 0 × Set or cleared according to result Previously saved value is restored Table C-5. Condition Codes Condition Name (cond) Condition Code (cccc) Conditional Expression Description...
Page 478 APPENDIX C LIST OF INSTRUCTION SETS Instruction Set List (1/4) Flag Instruction Mnemonic Operand Opcode Operation Group CY OV S Z SAT adr ← ep + zero-extend (disp7) Load/store SLD.B disp7 [ep], rrrrr0110ddddddd GR [reg2] ← sign-extend (Load-memory reg2 (adr, Byte)) adr ←...
Page 479 APPENDIX C LIST OF INSTRUCTION SETS Instruction Set List (2/4) Flag Instruction Mnemonic Operand Opcode Operation Group CY OV S Z SAT GR [reg2] ← GR [reg2] + GR [reg1] × × × × Arithmetic reg1, reg2 rrrrr001110RRRRR operation GR [reg2] ← GR [reg2] + sign-extend ×...
Page 480 APPENDIX C LIST OF INSTRUCTION SETS Instruction Set List (3/4) Flag Instruction Operand Opcode Operation Mnemonic Group CY OV S Z SAT GR [reg2] ← GR [reg2] XOR GR [reg1] × × Logic reg1, reg2 rrrrr001001RRRRR operation GR [reg2] ← GR [reg1] XOR zero-extend ×...
Page 481 APPENDIX C LIST OF INSTRUCTION SETS Instruction Set List (4/4) Flag Instruction Mnemonic Operand Opcode Operation Group CY OV S Z SAT SR [regID] ←GR Special LDSR reg2, regID rrrrr111111RRRRR regID = EIPC, FEPC 0000000000100000 [reg2] regID = EIPSW, Note FEPSW ×...
Page 482: Appendix D Index
APPENDIX D INDEX [Number] Applications ---------------------------------------------------- 30 16-bit compare register 23 ------------------------------- 205 Arbitration ---------------------------------------------------- 271 16-bit compare register 45 ------------------------------- 205 Area -------------------------------------------------------------- 70 16-bit counter 23 ------------------------------------------- 205 Area number ------------------------------------------------- 422 16-bit counter 45 ------------------------------------------- 205 ASCK0 ---------------------------------------------------------- 45 16-bit timers ------------------------------------------------- 153 ASCK1 ---------------------------------------------------------- 46 16-bit timer mode control register n ------------------- 158...
Page 483 APPENDIX D INDEX Capture/compare register n0 --------------------------- 156 DWC ------------------------------------------------------------ 93 Capture/compare register n1 --------------------------- 157 Cascade connection (16-bit timer) mode ------------ 205 Cautions on power save function----------------------- 151 ECR ------------------------------------------------------------- 62 CG --------------------------------------------------------------- 36 Edge detection function of external interrupt request Channel control block ------------------------------------- 331 input pin ----------------------------------------------------114 CLKOUT ------------------------------------------------------- 53...
Page 484 APPENDIX D INDEX INTP0 to INTP6 ---------------------------------------------- 44 C bus -------------------------------------------------------- 228 Introduction----------------------------------------------------- 27 C bus definitions and control methods --------------- 244 ISPR ---------------------------------------------------------- 125 C bus mode ------------------------------------------------ 228 C bus mode function ------------------------------------- 243 C interrupt request --------------------------------------- 251 LBEN ------------------------------------------------------------ 50 IC -----------------------------------------------------------------54 ID flag --------------------------------------------------------- 126...
Page 485 APPENDIX D INDEX P1 -------------------------------------------------------------- 353 PM6 ------------------------------------------------------------376 P10 ------------------------------------------------------------ 383 PM9 ------------------------------------------------------------380 P10 to P15 ---------------------------------------------------- 45 PMC12 --------------------------------------------------------391 P100 to P107 ------------------------------------------------- 52 Port 0 ----------------------------------------------------------348 P11 ------------------------------------------------------------ 387 Port 0 mode register ---------------------------------------350 P110 to P114 ------------------------------------------------- 52 Port 1 ----------------------------------------------------------353 P12 ------------------------------------------------------------ 390 Port 1 function register ------------------------------------355...
Page 486 APPENDIX D INDEX Program space ------------------------------------ 68, 79, 105 RTBH --------------------------------------------------------- 342 Program status word ----------------------------------------63 RTBL ---------------------------------------------------------- 342 Programmable wait function -------------------------------93 RTO ----------------------------------------------------------- 340 Programming environment ------------------------------- 404 RTP ------------------------------------------------------------- 36 Programming method ------------------------------------- 410 RTP0 to RTP7 ------------------------------------------------ 52 PSC ------------------------------------------------------------ 142 RTPC --------------------------------------------------------- 344 PSW -------------------------------------------------------------63...
Page 487 APPENDIX D INDEX Software STOP mode ------------------------------------ 148 UART0, UART1 ---------------------------------------------286 Specific register ---------------------------------------------- 86 UBEN ----------------------------------------------------------- 50 Square wave output ---------------------------------178, 201 SRIC1 -------------------------------------------------------- 124 Standby function ------------------------------------------- 307 -------------------------------------------------------------- 54 Start condition ---------------------------------------------- 244 Voltage comparator-----------------------------------------310 Start condition detector ----------------------------------- 232 -------------------------------------------------------------- 54 STIC0, STIC1 ----------------------------------------------- 124 -------------------------------------------------------------- 54...
Page 488: Appendix E Revision History
APPENDIX E REVISION HISTORY The following table shows the revision history up to this edition. The “Applied to:” column indicates the chapters of each edition in which the revision was applied. (1/7) Edition Major Revision from Previous Edition Applied to: µ...
Page 489 APPENDIX E REVISION HISTORY (2/7) Edition Major Revision from Previous Edition Applied to: 6.1 (1) Main system clock oscillator Modification of maximum operating frequency and CHAPTER 6 edition addition of Caution 2 CLOCK GENERATION Figure 6-2 Processor Clock Control Register (PCC) Modification of bit 7, addition of bit 5 FUNCTION (MFRC) and Caution 3 6.3.1 (1) (a) Example of main clock operation →...
Page 490 APPENDIX E REVISION HISTORY (3/7) Edition Major Revision from Previous Edition Applied to: Figure 7-24 Configuration of External Event Counter Addition of PRM01 and PRM11 CHAPTER 7 registers in Note edition TIMER/COUNTER FUNCTION Figure 7-28 Control Register Settings for One-Shot Pulse Output with Software Trigger Addition of Caution 7.2.7 (2) Setting 16-bit capture/compare register, (7) <2>, (8) Conflicting operations, (9) Timer operation, (10) Capture operation, (11) Compare operation, (12) Edge...
Page 491 APPENDIX E REVISION HISTORY (4/7) Edition Major Revision from Previous Edition Applied to: Figure 9-5 Oscillation Stabilization Time Select Register (OSTS) Addition of oscillation CHAPTER 9 edition stabilization time when f = 10 MHz, f = 2 MHz WATCHDOG TIMER 10.1 Overview Deletion and addition of products in Note CHAPTER 10 SERIAL...
Page 492 µ Deletion of PD703014AGC, 703014AYGC, 703015AGC, and 703015AYGC edition Addition of Table 1-1 List of V850/SA1 Products INTRODUCTION Addition of description to the minimum instruction execution time in 1.2 Features Deletion and addition of products in 1.4 Ordering Information Deletion and addition of products in 1.5 Pin Configuration Deletion of description in 1.6.2 (2) Bus control unit (BCU)
Page 493 APPENDIX E REVISION HISTORY (6/7) Edition Major Revision from Previous Edition Applied to: Addition of description to minimum instruction execution time in 3.1 Features CHAPTER 3 CPU edition FUNCTIONS Change of description in 3.2.2 (2) Program status word (PSW) Modification of Figure 3-16 Recommended Memory Map Addition of description in 3.4.8 Peripheral I/O registers Addition and modification of description in 3.4.9 Specific registers Addition of description in 5.2.4 Noise elimination of external interrupt request input...
Page 494 CHAPTER 16 FLASH MEMORY Change of description in 16.1.1 Erasing unit µ PD70F3017A, Addition of Figure 16-1 Wiring Example of V850/SA1 Flash Writing Adapter (FA100GC- 70F3017AY) 8EU) Addition of Table 16-1 Wiring Table of V850/SA1 Flash Writing Adapter (FA100GC- 8EU)

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Renesas V850/SA1 User Manual

Chapter 1 Introduction

Chapter 2 Pin Functions

Chapter 3 Cpu Functions

Chapter 4 Bus Control Function

Chapter 5 Interrupt/Exception Processing Function

Chapter 6 Clock Generation Function

Chapter 7 Timer/Counter Function

Chapter 8 Watch Timer

Chapter 9 Watchdog Timer

Chapter 10 Serial Interface Function

Chapter 11 A/D Converter

Chapter 12 Dma Functions

Chapter 13 Real-Time Output Function (Rto)

Chapter 14 Port Function

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Summary of Contents for Renesas V850/SA1