Renesas M16C/64A Series User Manual page 507

M16C/64A Group
23.3.1.2 LSB First/MSB First Select Function
Use the UFORM bit in the UiC0 register (i = 0 to 2, 5 to 7) to select the bit order. Figure 23.7 shows the
Bit Order.
(1) UFORM bit in the UiC0 register is 0 (LSB first)
CLKi
TXDi
RXDi
(2) UFORM bit in the UiC0 register is 1 (MSB first)
CLKi
TXDi
RXDi
i = 0 to 2, 5 to 7
The above assumes the following:
• The CKPOL bit in the UiC0 register is 0 (transmit data is output at the falling edge and the
receive data is input at the rising edge of the transmit/receive clock).
• The UiLCH bit in the UiC1 register is 0 (not inverted).
Figure 23.7 Bit Order
23.3.1.3 Continuous Receive Mode
In continuous receive mode, the receive operation is enabled when the receive buffer register is read.
Thus, a dummy write to the transmit buffer register to enable the receive operation is unnecessary in
this mode. However, a dummy read of the receive buffer register is required when start receiving.
When setting the UiRRM bit in the UiC1 or UCON register (i = 0 to 2, 5 to 7) to 1 (continuous receive
mode), the TI bit in the UiC1 register is set to 0 (data present in the UiTB register) by reading the UiRB
register. When the UiRRM bit is 1, do not write dummy data to the UiTB register by a program.
When using an external clock, read the UiRB register between receiving the eighth bit of data and
starting the next transmission.
Figure 23.8 shows Operation Example in Continuous Receive Mode.
CLKi
D0 D1
RXDi
i = 0 to 2, 5 to 7
The above diagram assumes the following:
•
The CKPOL bit in the UiC0 register is 0 (receive data input at the rising edge of the transmit/receive clock).
•
The UFORM bit in the UiC0 register is 0 (LSB first).
•
The CKDIR bit in the UiMR register is 1 (external clock).
Figure 23.8 Operation Example in Continuous Receive Mode
R01UH0136EJ0210 Rev.2.10
Jul 31, 2012
D0
D1
D0 D1
D7 D6
D7 D6
When using an external clock,
read the UiRB register during this period.
D2 D3 D4 D5 D6 D7
D7 received
23. Serial Interface UARTi (i = 0 to 2, 5 to 7)
D2 D3 D4 D5
D2 D3 D4 D5
D5 D4 D3 D2
D5 D4 D3 D2
When using an external clock,
read the UiRB register during this period.
D0 D1 D2 D3 D4
Next transmission starts.
D6
D7
D6
D7
D1
D0
D1
D0
D5 D6 D7 D0
D7 received
Next transmission
starts.
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D1 D2