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M16C/64A Group
Table 22.12
Registers and Setting Values in Pattern Match Mode (Combined Operation) (1/2)
Register
PMCiCON0
PMCiCON1
PMCiCON2
PMCiCON3
PMCiSTS
i = 0, 1
-: Unimplemented bit in PMC1
Note:
1.
This table does not describe a procedure.
R01UH0136EJ0210 Rev.2.10
Jul 31, 2012
Bit
Set to 1. Refer to 22.3.3.1
EN
"Setting Procedure".
SINV
Set to 0.
FIL
Set to 0.
Select receive error holding
EHOLD
period.
Select header
HDEN
enabled/disabled.
Select special data
SDEN
enabled/disabled.
DRINT0
Select receive interrupt
generating condition.
DRINT1
TYP0
Select measuring object.
TYP1
CSS
Set to 0.
EXSDEN
Select block in which header
EXHDEN
and special pattern is detected.
Flag indicating PMCi
ENFLG
operated/stopped.
INFLG
Input signal flag
CEFLG
Not used.
CEINT
Set to 0.
PSEL0
Set to 00b.
PSEL1
CRE
Set to 0.
CFR
Set to 0.
CST
Set to 0.
PD
Set to 0.
CSRC0
Set to 00b.
CSRC1
CDIV0
Set to 00b.
CDIV1
CPFLG
Compare match flag
REFLG
Receive error flag
DRFLG
Data receiving flag
BFULFLG
Receive buffer full flag
PTHDFLG
Header pattern match flag
PTD0FLG
Data 0 pattern match flag
PTD1FLG
Data 1 pattern match flag
SDFLG
Special pattern match flag
22. Remote Control Signal Receiver
Function
PMC0
Set to 1. Refer to 22.3.3.1
"Setting Procedure".
Select input signal polarity.
Select filter enabled/disabled.
Set to 1.
Select measuring object. Set
the same value as PMC0.
Not used.
Not used.
Not used.
Set to 0.
Select input pin.
Set to 0.
Set to 0.
Set to 0.
Set to 0.
Select clock source.
Select count source divisor.
Not used
Not used
Not used
Not used
Not used
(1)
PMC1
-
-
-
-
-
-
-
-
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