Page 1 On April 1 , 2010, NEC Electronics Corporation merged with Renesas Technology Corporation, and Renesas Electronics Corporation took over all the business of both companies. Therefore, although the old company name remains in this document, it is a valid Renesas Electronics document. We appreciate your understanding.
Page 2 Renesas Electronics. Renesas Electronics shall not be in any way liable for any damages or losses incurred by you or third parties arising from the use of any Renesas Electronics product for an application categorized as “Specific”...
Page 3 μ PD78F0893(A2) The 78K0/FF2 has an on-chip debug function. Do not use this product for mass production after the on-chip debug function has been used because its reliability cannot be guaranteed, due to issues with respect to the number of times the flash memory can be rewritten. NEC Electronics does not accept complaints concerning when use this product for mass production after the on-chip debug function has been used.
Page 4 [MEMO] User’s Manual U17553EJ4V0UD...
Page 5 NOTES FOR CMOS DEVICES VOLTAGE APPLICATION WAVEFORM AT INPUT PIN Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the CMOS device stays in the area between V (MAX) and V (MIN) due to noise, etc., the device may malfunction.
Page 6 EEPROM is trademark of NEC Electronics Corporation. Windows, Windows NT and Windows XP are either registered trademarks or trademarks of Microsoft Corporation in the United States and/or other countries. PC/AT is a trademark of International Business Machines Corporation. HP9000 series 700 and HP-UX are trademarks of Hewlett-Packard Company. SPARCstation is a trademark of SPARC International, Inc.
Page 7 [MEMO] User’s Manual U17553EJ4V0UD...
Page 8 This manual is intended to give users an understanding of the functions described in the Organization below. Organization The 78K0/FF2 manual are separated into two parts: this manual and the instructions edition (common to the 78K/0 Series). 78K0/FF2 78K/0 Series User’s Manual...
Page 9 The related documents indicated in this publication may include preliminary versions. However, preliminary versions are not marked as such. Documents Related to Devices Document Name Document No. 78K0/FF2 User’s Manual This manual 78K/0 Series Instructions User’s Manual U12326E Documents Related to Development Tools (Software) (User’s Manuals) Document Name Document No.
Page 10: Table Of Contents
CONTENTS CHAPTER 1 OUTLINE ..........................17 1.1 Features............................17 1.2 Applications ..........................18 1.3 Ordering Information ........................18 1.4 Pin Configuration (Top View) ...................... 19 1.5 Fx2 Series Lineup......................... 21 1.5.1 78K0/Fx2 product lineup ........................21 1.6 Block Diagram ..........................23 1.7 Outline of Functions ........................
Page 11 3.3.1 Relative addressing..........................66 3.3.2 Immediate addressing........................67 3.3.3 Table indirect addressing ........................68 3.3.4 Register addressing ...........................68 3.4 Operand Address Addressing ....................69 3.4.1 Implied addressing ..........................69 3.4.2 Register addressing ...........................70 3.4.3 Direct addressing ..........................71 3.4.4 Short direct addressing ........................72 3.4.5 Special function register (SFR) addressing..................73 3.4.6 Register indirect addressing.......................74 3.4.7 Based addressing ..........................75 3.4.8 Based indexed addressing.........................76...
Page 12 6.2 Configuration of Clock Generator .................... 125 6.3 Registers Controlling Clock Generator..................127 6.4 System Clock Oscillator ......................136 6.4.1 X1 oscillator............................136 6.4.2 XT1 oscillator............................136 6.4.3 When subsystem clock is not used ....................139 6.4.4 Internal high-speed oscillator......................139 6.4.5 Internal low-speed oscillator ......................139 6.4.6 Prescaler ............................139 6.5 Clock Generator Operation .......................
Page 13 CHAPTER 9 8-BIT TIMERS H0 AND H1 ..................239 9.1 Functions of 8-Bit Timers H0 and H1 ..................239 9.2 Configuration of 8-Bit Timers H0 and H1................. 239 9.3 Registers Controlling 8-Bit Timers H0 and H1 ................ 243 9.4 Operation of 8-Bit Timers H0 and H1 ..................248 9.4.1 Operation as interval timer/square-wave output................248 9.4.2 Operation as PWM output mode ......................251 9.4.3 Carrier generator mode operation (8-bit timer H1 only)..............257...
Page 14 14.2 Configurations of Serial Interface UART60 and UART61............. 311 14.3 Registers Controlling Serial Interfaces UART60 and UART61 ..........315 14.4 Operations of Serial Interface UART60 and UART61............334 14.4.1 Operation stop mode........................334 14.4.2 Asynchronous serial interface (UART) mode .................335 14.4.3 Dedicated baud rate generator.......................350 CHAPTER 15 SERIAL INTERFACES CSI10 AND CSI11 ..............
Page 15 16.9.1 Message reception.........................457 16.9.2 Receive Data Read ........................458 16.9.3 Receive history list function......................459 16.9.4 Mask function ..........................461 16.9.5 Multi buffer receive block function ....................463 16.9.6 Remote frame reception.........................464 16.10 Message Transmission......................465 16.10.1 Message transmission .........................465 16.10.2 Transmit history list function......................467 16.10.3 Automatic block transmission (ABT) ....................469 16.10.4 Transmission abort process ......................470 16.10.5 Remote frame transmission ......................471...
Page 16 CHAPTER 19 RESET FUNCTION......................552 19.1 Register for Confirming Reset Source ................... 560 CHAPTER 20 MULTIPLIER/DIVIDER ....................561 20.1 Functions of Multiplier/Divider....................561 20.2 Configuration of Multiplier/Divider ..................561 20.3 Register Controlling Multiplier/Divider .................. 565 20.4 Operations of Multiplier/Divider....................566 20.4.1 Multiplication operation........................566 20.4.2 Division operation...........................568 CHAPTER 21 POWER-ON-CLEAR CIRCUIT..................
Page 17 24.7.3 Selecting communication mode .....................611 24.7.4 Communication commands......................612 24.8 Security Settings........................613 24.9 Processing Time for Each Command When PG-FP4 Is Used (Reference) ......615 24.10 Flash Memory Programming by Self-Programming............616 24.10.1 Registers used for self-programming function................623 24.11 Boot Swap Function ......................627 CHAPTER 25 ON-CHIP DEBUG FUNCTION ..................
Page 18 APPENDIX A DEVELOPMENT TOOLS....................699 A.1 Software Package ........................703 A.2 Language Processing Software ....................703 A.3 Control Software ........................704 A.4 Flash Memory Programming Tools..................705 A.4.1 When using flash memory programmer FG-FP4, FL-PR4, PG-FPL3, and FP-LITE3 ......705 A.4.2 When using on-chip debug emulator with programming function QB-MINI2........705 A.5 Debugging Tools (Hardware)....................
Page 19: Chapter 1 Outline
CHAPTER 1 OUTLINE 1.1 Features μ Minimum instruction execution time can be changed from high speed (0.1 s: @ 20 MHz operation with high- μ speed system clock) to ultra low-speed (122 s: @ 32.768 kHz operation with subsystem clock) General-purpose register: 8 bits ×...
Page 20: Applications
CHAPTER 1 OUTLINE 1.2 Applications Automotive electrical appliances (Body control, Door control, Front light control) Industrial equipment (Industrial robot, Building control) 1.3 Ordering Information • Flash memory version Part Number Package Quality Grade μ PD78F0891GC(A)-GAD-AX 80-pin plastic LQFP (14x14) Special μ...
Page 21: Pin Configuration (Top View)
CHAPTER 1 OUTLINE 1.4 Pin Configuration (Top View) • 80-pin plastic LQFP (14x14) • 80-pin plastic LQFP (Fine pitch)(12x12) 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 P120/INTP0/EXLVI P10/SCK10/T P11/SI10/R P12/SO10...
Page 22 CHAPTER 1 OUTLINE Pin Identification ANI0 to ANI15: Analog input P90 to P97: Port 9 Analog reference voltage P120 to P124: Port 12 Analog ground P130 to P132: Port 13 BUZ: Buzzer output PCL: Programmable clock output CRxD: Receive data for CAN REGC: Regulator Capacitance CTxD:...
Page 23: Fx2 Series Lineup
RAM: 3 KB RAM: 5 KB RAM: 7 KB • × × 80-pin LQFP (12 12 mm 0.5 mm pitch, 14 14 mm 0.65 mm pitch) 78K0/FF2 μPD78F0893 μPD78F0891 μPD78F0892 Single-power-supply flash Single-power-supply flash Single-power-supply flash memory: 60 KB, memory: 96 KB,...
Page 24 CHAPTER 1 OUTLINE The list of functions in the 78K0/Fx2 is shown below. Part Number 78K0/FC2 78K0/FE2 78K0/FF2 Item Number of pins 44 pins 48 pins 64 pins 80 pins Internal Flash memory 32 K/48 K/60 K 48 K/60 K/96 K/128 K...
Page 25: Block Diagram
CHAPTER 1 OUTLINE 1.6 Block Diagram TO00/TI010/P01 16-bit timer/ Port 0 P00.P01,P05, P06 event counter 00 TI000/P00 (LINSEL) RxD60/P14 (LINSEL) Port 1 P10 to P17 TO01/TI011/P06 16-bit timer/ event counter 01 TI001/P05 Port 3 P30 to P33 TO02/TI012/P32 16-bit timer/ event counter 02 Port 4 TI002/P31...
Page 26: Outline Of Functions
CHAPTER 1 OUTLINE 1.7 Outline of Functions (1/2) μ μ μ Item PD78F0891 PD78F0892 PD78F0893 Internal Flash memory 60 K 96 K 128 K memory (self-programming Note (bytes) supported) − Bank Note High-speed RAM Note Expansion RAM Memory space 64 KB High-speed system clock Crystal/ceramic oscillation (X ), external main system clock input (EXCLK)
Page 27 CHAPTER 1 OUTLINE (2/2) μ μ μ Item PD78F0891 PD78F0892 PD78F0893 Serial interface 1 ch 3-wire CSI 1 ch LIN-UART 1 ch LIN-UART/ 1 ch Note1 Multiplier/divider • 16 bit x 16 bit = 32 bit (Multiplication) • 32 bit ÷ 32 bit = 32 bit remainder of 16 bits (Division) <R>...
Page 28: Chapter 2 Pin Functions
Port pins other than P80 to P87, P90 to P97 and P121 to P124 • P121 to P124 • Non-port pins This section explains the names and functions of the pins of the 78K0/FF2. Port pins Table 2-2. Port pins (1/2)
Page 29 CHAPTER 2 PIN FUNCTIONS Table 2-2. Port pins (2/2) Pin Name Function After Reset Alternate Function − P50 to P57 Port 5. Input 8-bit I/O port. Input/output can be specified in 1-bit units. Use of an on-chip pull-up resistor can be specified by a software setting.
Page 30 CHAPTER 2 PIN FUNCTIONS Non-port pins Table 2-3. Non-port pins (1/2) Pin Name Function After Reset Alternate Function INTP0 Input External interrupt request input for which the valid edge (rising Input P120/EXLVI edge, falling edge, or both rising and falling edges) can be INTP1 specified INTP2...
Page 31 CHAPTER 2 PIN FUNCTIONS Table 2-3. Non-port pins (2/2) Pin Name Function After Reset Alternate Function TO03 Output 16-bit timer/event counter 03 output Input P132/TI013 TI50 Input External count clock input to 8-bit timer/event counter 50 Input P17/TO50 TI51 External count clock input to 8-bit timer/event counter 51 P33/TO51/INTP4 TO50 Output...
Page 32: Description Of Pin Functions
CHAPTER 2 PIN FUNCTIONS 2.2 Description of Pin Functions 2.2.1 P00, P01, P05, P06 (port 0) P00, P01, P05 and P06 function as a 4-bit I/O port. These pins also function as timer I/O and serial interface chip select input. The following operation modes can be specified in 1-bit units.
Page 33: P10 To P17 (Port 1)
CHAPTER 2 PIN FUNCTIONS 2.2.2 P10 to P17 (port 1) P10 to P17 function as an 8-bit I/O port. These pins also function as pins for external interrupt request input, serial interface data I/O, clock I/O, and timer I/O. The following operation modes can be specified in 1-bit units. Port mode P10 to P17 function as an 8-bit I/O port.
Page 34: P30 To P33 (Port 3)
CHAPTER 2 PIN FUNCTIONS 2.2.3 P30 to P33 (port 3) P30 to P33 function as a 4-bit I/O port. These pins also function as pins for external interrupt request input and timer I/O. The following operation modes can be specified in 1-bit units. Port mode P30 to P33 function as a 4-bit I/O port.
Page 35: P50 To P57 (Port 5)
CHAPTER 2 PIN FUNCTIONS 2.2.5 P50 to P57 (port 5) P50 to P57 function as a 8-bit I/O port. P50 to P57 can be set to input or output in 1-bit units using port mode register 5 (PM5). Use of an on-chip pull-up resistor can be specified by pull-up resistor option register 5 (PU5). 2.2.6 P60 to P67 (port 6) P60 to P67 function as a 8-bit I/O port.
Page 36: P80 To P87 (Port 8)
CHAPTER 2 PIN FUNCTIONS 2.2.8 P80 to P87 (port 8) P80 to P87 function as an 8-bit I/O port. These pins also function as pins for A/D converter analog input. The following operation modes can be specified in 1-bit units. Port mode P80 to P87 function as an 8-bit I/O port.
Page 37: P130 To P132 (Port 13)
CHAPTER 2 PIN FUNCTIONS (b) EXLVI This is a potential input pin for external low-voltage detection. (c) X1, X2 These are the pins for connecting a resonator for high-speed system clock. When supplying an external clock, input a signal to the X1 pin and input the inverse signal to the X2 pin. Caution Connect P121/X1 as follows when writing the flash memory with a flash programmer.
Page 38: Av Ref
CHAPTER 2 PIN FUNCTIONS 2.2.12 AV This is the A/D converter reference voltage input pin. Note When the A/D converter is not used, connect this pin directly to EV or V Note Connect port 8 and port 9 directly to EV when it is used as a digital port.
Page 39: Pin I/O Circuits And Recommended Connection Of Unused Pins
CHAPTER 2 PIN FUNCTIONS 2.3 Pin I/O Circuits and Recommended Connection of Unused Pins Table 2-4 shows the types of pin I/O circuits and the recommended connections of unused pins. Refer to Figure 2-1 for the configuration of the I/O circuit of each type. Table 2-4.
Page 40 CHAPTER 2 PIN FUNCTIONS Table 2-4. Pin I/O Circuit Types (2/2) Pin Name I/O Circuit Recommended Connection of Unused Pins Type Note 1 P80/ANI0 to P87/ANI7 11-G <Analog setting> Note 1 P90/ANI8 to P97/ANI15 Connect to AV or AV <Digital setting> Input: Independently connect to EV via a resistor.
Page 41 CHAPTER 2 PIN FUNCTIONS Figure 2-1. Pin I/O Circuit List (1/2) Type 5-H Type 2 Pullup P-ch enable Output P-ch data IN/OUT Schmitt-triggered input with hysteresis characteristics Output N-ch disable EVss Input enable Type 11-G Type 3-C Data P-ch IN/OUT P-ch Output N-ch...
Page 42 CHAPTER 2 PIN FUNCTIONS Figure 2-1. Pin I/O Circuit List (2/2) Type 37 Reset Data P-ch Output N-ch disable Input enable Reset Data P-ch Output N-ch disable Input enable User’s Manual U17553EJ4V0UD...
Page 43: Chapter 3 Cpu Architecture
CHAPTER 3 CPU ARCHITECTURE 3.1 Memory Space Products in the 78K0/FF2 can each access a 64 KB memory space. Figures 3-1 to 3-3 show the memory map. Caution Regardless of the internal memory capacity, the initial values of the internal memory size switching register (IMS) and internal expansion RAM size switching register (IXS) of the 78K0/FF2 is fixed (IMS = CFH, IXS = 0CH).
Page 44 CHAPTER 3 CPU ARCHITECTURE μ Figure 3-1. Memory Map ( PD78F0891) FFFFH Special function registers (SFR) FF20H 256 × 8 bits FF1FH FF00H FEFFH General-purpose registers Short direct 32 × 8 bits FEE0H addressing FEDFH Internal high-speed RAM E F F F H 1024 ×...
Page 45 CHAPTER 3 CPU ARCHITECTURE μ Figure 3-2. Memory Map ( PD78F0892) FFFFH Special function registers (SFR) FF20H 256 × 8 bits FF1FH FF00H FEFFH General-purpose registers Short direct 32 × 8 bits FEE0H addressing FEDFH Internal high-speed RAM 1024 × 8 bits FE20H FE1FH Note 1...
Page 46 CHAPTER 3 CPU ARCHITECTURE μ Figure 3-3. Memory Map ( PD78F0893) FFFFH Special function registers (SFR) FF20H 256 × 8 bits FF1FH FF00H FEFFH General-purpose registers Short direct 32 × 8 bits FEE0H addressing FEDFH Internal high-speed RAM 1024 × 8 bits FE20H FE1FH Note 1...
Page 47 CHAPTER 3 CPU ARCHITECTURE Correspondence between the address values and block numbers in the flash memory are shown below. Table 3-2. Correspondence Between Address Values and Block Numbers in Flash Memory (1/2) μ PD78F0891 Block Block Block Block Address Value Address Value Address Value Address Value...
Page 48 CHAPTER 3 CPU ARCHITECTURE Table 3-2. Correspondence Between Address Values and Block Numbers in Flash Memory (2/2) μ PD78F0892, 78F0893 Address Value Block Address Value Block Address Value Block Address Value Block Number Number Number Number 0000H to 03FFH 8000H to 83FFH 8000H to 83FFH 8000H to 83FFH 0400H to 07FFH...
Page 49: Internal Program Memory Space
3.1.1 Internal program memory space The internal program memory space stores the program and table data. Normally, it is addressed with the program counter (PC). 78K0/FF2 products incorporate internal ROM (flash memory), as shown below. Table 3-2. Internal ROM Capacity Part Number...
Page 50: Bank Area ( Μ Pd78F0892 And 78F0893 Only)
CHAPTER 3 CPU ARCHITECTURE (2) CALLT instruction table area The 64-byte area 0040H to 007FH can store the subroutine entry address of a 1-byte call instruction (CALLT). (3) Option byte area The option byte area is assigned to the 1-byte area of 0080H. Refer to CHAPTER 23 OPTION BYTE for details. (4) CALLF instruction entry area The area 0800H to 0FFFH can perform a direct subroutine call with a 2-byte call instruction (CALLF).
Page 51 CHAPTER 3 CPU ARCHITECTURE μ PD78F0893 B F F F H Bank Bank Bank Bank Bank Bank area 0 area 1 area 2 area 3 area 4 area 5 16384 × 16384 × 16384 × 16384 × 16384 × 16384 × 8 bits 8 bits 8 bits...
Page 52: Internal Data Memory Space
Several addressing modes are provided for addressing the memory relevant to the execution of instructions for the 78K0/FF2, based on operability and other considerations. For areas containing data memory in particular, special addressing methods designed for the functions of special function registers (SFR) and general-purpose registers are available for use.
Page 53 CHAPTER 3 CPU ARCHITECTURE μ Figure 3-5. Correspondence Between Data Memory and Addressing ( PD78F0891) FFFFH Special function registers (SFR) SFR addressing 256 × 8 bits FF20H FF1FH FF00H FEFFH General-purpose registers Register addressing 32 × 8 bits Short direct FEE0H addressing FEDFH...
Page 54 CHAPTER 3 CPU ARCHITECTURE μ Figure 3-6. Correspondence Between Data Memory and Addressing ( PD78F0892) FFFFH Special function registers (SFR) SFR addressing 256 × 8 bits FF20H FF1FH FF00H FEFFH General-purpose registers Register addressing 32 × 8 bits Short direct FEE0H addressing FEDFH...
Page 55 CHAPTER 3 CPU ARCHITECTURE μ Figure 3-7. Correspondence Between Data Memory and Addressing ( PD78F0893) FFFFH Special function registers (SFR) SFR addressing 256 × 8 bits FF20H FF1FH FF00H FEFFH General-purpose registers Register addressing 32 × 8 bits Short direct FEE0H addressing FEDFH...
Page 56: Processor Registers
CHAPTER 3 CPU ARCHITECTURE 3.2 Processor Registers 78K0/FF2 products incorporate the following processor registers. 3.2.1 Control registers The control registers control the program sequence, statuses and stack memory. The control registers consist of a program counter (PC), a program status word (PSW) and a stack pointer (SP).
Page 57 CHAPTER 3 CPU ARCHITECTURE (c) Register bank select flags (RBS0 and RBS1) These are 2-bit flags to select one of the four register banks. In these flags, the 2-bit information that indicates the register bank selected by SEL RBn instruction execution is stored.
Page 58 CHAPTER 3 CPU ARCHITECTURE Figure 3-11. Data to Be Saved to Stack Memory (a) PUSH rp instruction (when SP = FEE0H) FEE0H FEE0H FEDFH Register pair higher FEDEH Register pair lower FEDEH (b) CALL, CALLF, CALLT instructions (when SP = FEE0H) FEE0H FEE0H FEDFH...
Page 59 CHAPTER 3 CPU ARCHITECTURE Figure 3-12. Data to Be Restored from Stack Memory (a) POP rp instruction (when SP = FEDEH) FEE0H FEE0H FEDFH Register pair higher FEDEH Register pair lower FEDEH (b) RET instruction (when SP = FEDEH) FEE0H FEE0H FEDFH PC15 to PC8...
Page 60: General-Purpose Registers
CHAPTER 3 CPU ARCHITECTURE 3.2.2 General-purpose registers General-purpose registers are mapped at particular addresses (FEE0H to FEFFH) of the data memory. The general-purpose registers consists of 4 banks, each bank consisting of eight 8-bit registers (X, A, C, B, E, D, L, and H). Each register can be used as an 8-bit register, and two 8-bit registers can also be used in a pair as a 16-bit register (AX, BC, DE, and HL).
Page 61: Special Function Registers (Sfrs)
CHAPTER 3 CPU ARCHITECTURE 3.2.3 Special Function Registers (SFRs) Unlike a general-purpose register, each special function register has a special function. SFRs are allocated to the FF00H to FFFFH area. Special function registers can be manipulated like general-purpose registers, using operation, transfer and bit manipulation instructions.
Page 62 CHAPTER 3 CPU ARCHITECTURE Table 3-7. Special Function Register List (1/6) Address Special Function Register (SFR) Name Symbol Manipulatable Bit Unit After Reset 1 Bit 8 Bits 16 Bits √ √ − FF00H Port register 0 √ √ − FF01H Port register 1 −...
Page 63 CHAPTER 3 CPU ARCHITECTURE Table 3-7. Special Function Register List (2/6) Address Special Function Register (SFR) Name Symbol Manipulatable Bit Unit After Reset 1 Bit 8 Bits 16 Bits √ √ − FF2AH A/D converter mode register √ √ − FF2BH Analog input channel specification register √...
Page 64 CHAPTER 3 CPU ARCHITECTURE Table 3-7. Special Function Register List (3/6) Address Special Function Register (SFR) Name Symbol Manipulatable Bit Unit After Reset 1 Bit 8 Bits 16 Bits √ √ − FF4FH Input switch control register √ √ − FF50H Asynchronous serial interface operation mode ASIM60...
Page 65 CHAPTER 3 CPU ARCHITECTURE Table 3-7. Special Function Register List (4/6) Address Special Function Register (SFR) Name Symbol Manipulatable Bit Unit After Reset 1 Bit 8 Bits 16 Bits − − √ FF76H CAN Module Mask 2 Register H C0MASK2H Undefined FF77H −...
Page 66 CHAPTER 3 CPU ARCHITECTURE Tables 3-7. Special Function Register List (5/6) Address Special Function Register (SFR) Name Symbol Manipulatable Bit Unit After Reset 1 Bit 8 Bits 16 Bits √ √ − FFA3H Oscillation stabilization time counter status register OSTC √...
Page 67 Regardless of the internal memory capacity, the initial values of the internal memory size switching register (IMS) and internal expansion RAM size switching register (IXS) of the 78K0/FF2 is fixed (IMS = CFH, IXS = 0CH). Therefore, set the value corresponding to each as indicated below.
Page 68: Instruction Address Addressing
CHAPTER 3 CPU ARCHITECTURE 3.3 Instruction Address Addressing An instruction address is determined by program counter (PC) contents and is normally incremented (+1 for each byte) automatically according to the number of bytes of an instruction to be fetched each time another instruction is executed.
Page 69: Immediate Addressing
CHAPTER 3 CPU ARCHITECTURE 3.3.2 Immediate addressing [Function] Immediate data in the instruction word is transferred to the program counter (PC) and branched. This function is carried out when the CALL !addr16 or BR !addr16 or CALLF !addr11 instruction is executed. CALL !addr16 and BR !addr16 instructions can be branched to the entire memory space.
Page 70: Register Addressing
CHAPTER 3 CPU ARCHITECTURE 3.3.3 Table indirect addressing [Function] Table contents (branch destination address) of the particular location to be addressed by bits 1 to 5 of the immediate data of an operation code are transferred to the program counter (PC) and branched. This function is carried out when the CALLT [addr5] instruction is executed.
Page 71: Operand Address Addressing
3.4.1 Implied addressing [Function] The register that functions as an accumulator (A and AX) among the general-purpose registers is automatically (implicitly) addressed. Of the 78K0/FF2 instruction words, the following instructions employ implied addressing. Instruction Register to Be Specified by Implied Addressing MULU...
Page 72: Register Addressing
CHAPTER 3 CPU ARCHITECTURE 3.4.2 Register addressing [Function] The general-purpose register to be specified is accessed as an operand with the register bank select flags (RBS0 to RBS1) and the register specify codes (Rn and RPn) of an operation code. Register addressing is carried out when an instruction with the following operand format is executed.
Page 73: Direct Addressing
CHAPTER 3 CPU ARCHITECTURE 3.4.3 Direct addressing [Function] The memory to be manipulated is directly addressed with immediate data in an instruction word becoming an operand address. [Operand format] Identifier Description addr16 Label or 16-bit immediate data [Description example] MOV A, !0FE00H; when setting !addr16 to FE00H Operation code OP code [Illustration]...
Page 74: Short Direct Addressing
CHAPTER 3 CPU ARCHITECTURE 3.4.4 Short direct addressing [Function] The memory to be manipulated in the fixed space is directly addressed with 8-bit data in an instruction word. This addressing is applied to the 256-byte space FE20H to FF1FH. Internal RAM and special function registers (SFRs) are mapped at FE20H to FEFFH and FF00H to FF1FH, respectively.
Page 75: Special Function Register (Sfr) Addressing
CHAPTER 3 CPU ARCHITECTURE 3.4.5 Special function register (SFR) addressing [Function] A memory-mapped special function register (SFR) is addressed with 8-bit immediate data in an instruction word. This addressing is applied to the 240-byte spaces FF00H to FFCFH and FFE0H to FFFFH. However, the SFRs mapped at FF00H to FF1FH can be accessed with short direct addressing.
Page 76: Register Indirect Addressing
CHAPTER 3 CPU ARCHITECTURE 3.4.6 Register indirect addressing [Function] Register pair contents specified by a register pair specify code in an instruction word and by a register bank select flag (RBS0 and RBS1) serve as an operand address for addressing the memory. This addressing can be carried out for all the memory spaces.
Page 77: Based Addressing
CHAPTER 3 CPU ARCHITECTURE 3.4.7 Based addressing [Function] 8-bit immediate data is added as offset data to the contents of the base register, that is, the HL register pair in the register bank specified by the register bank select flag (RBS0 and RBS1), and the sum is used to address the memory.
Page 78: Based Indexed Addressing
CHAPTER 3 CPU ARCHITECTURE 3.4.8 Based indexed addressing [Function] The B or C register contents specified in an instruction word are added to the contents of the base register, that is, the HL register pair in the register bank specified by the register bank select flag (RBS0 and RBS1), and the sum is used to address the memory.
Page 79: Stack Addressing
CHAPTER 3 CPU ARCHITECTURE 3.4.9 Stack addressing [Function] The stack area is indirectly addressed with the stack pointer (SP) contents. This addressing method is automatically employed when the PUSH, POP, subroutine call and return instructions are executed or the register is saved/reset upon generation of an interrupt request. With stack addressing, only the internal high-speed RAM area can be accessed.
Page 80: Chapter 4 Memory Bank Select Function ( Μ Pd78F0892, 78F0893 Only)
CHAPTER 4 MEMORY BANK SELECT FUNCTION μ PD78F0892, 78F0893 ONLY) 4.1 Memory Bank μ PD78F0892, 78F0893 implement a ROM capacity of 96 KB or 128 KB by selecting a memory bank from a memory space of 8000H to BFFFH. μ μ...
Page 81: Difference In Representation Of Memory Space
CHAPTER 4 MEMORY BANK SELECT FUNCTION ( PD78F0892, 78F0893 ONLY) 4.2 Difference in Representation of Memory Space With the 78K0/FF2 products which support the memory bank, addresses can be viewed in the following two different ways. • Memory bank number + CPU address •...
Page 82: Memory Bank Select Register (Bank)
μ CHAPTER 4 MEMORY BANK SELECT FUNCTION ( PD78F0892, 78F0893 ONLY) Table 4-1. Memory Bank Address Representation Memory Bank Number CPU Address Flash Memory Real Address Address Representation in Note 1 Simulator and Debugger Note 2 Memory bank 0 08000H-0BFFFH 08000H-0BFFFH 08000H-0BFFFH Memory bank 1...
Page 83: Selecting Memory Bank
μ CHAPTER 4 MEMORY BANK SELECT FUNCTION ( PD78F0892, 78F0893 ONLY) 4.4 Selecting Memory Bank The memory bank selected by the memory bank select register (BANK) is reflected on the bank area and can be addressed. Therefore, to access a memory bank different from the one currently selected, that memory bank must be selected by using the BANK register.
Page 84 μ CHAPTER 4 MEMORY BANK SELECT FUNCTION ( PD78F0892, 78F0893 ONLY) • Software example (to store a value to be referenced in register A) RAMD DSEG SADDR R_BNKA: ; Secures RAM for specifying an address at the reference destination. R_BNKN: ;...
Page 85: Branching Instruction Between Memory Banks
μ CHAPTER 4 MEMORY BANK SELECT FUNCTION ( PD78F0892, 78F0893 ONLY) 4.4.2 Branching instruction between memory banks Instructions cannot branch directly from one memory bank to another. To branch an instruction from one memory bank to another, branch once to the common area (0000H to 7FFFH), change the setting of the BANK register there, and then execute the branch instruction again.
Page 86 μ CHAPTER 4 MEMORY BANK SELECT FUNCTION ( PD78F0892, 78F0893 ONLY) • Software example 1 (to branch from all areas) RAMD DSEG SADDR R_BNKA: ; Secures RAM for specifying a memory bank at the branch destination. R_BNKN: ; Secures RAM for specifying a memory bank number at the branch destination. RSAVEAX: DS ;...
Page 87: Subroutine Call Between Memory Banks
μ CHAPTER 4 MEMORY BANK SELECT FUNCTION ( PD78F0892, 78F0893 ONLY) 4.4.3 Subroutine call between memory banks Subroutines cannot be directly called between memory banks. To call a subroutine between memory banks, branch once to the common area (0000H to 7FFFH), specify the memory bank at the calling destination by using the BANK register there, execute the CALL instruction, and branch to the call destination by that instruction.
Page 88 μ CHAPTER 4 MEMORY BANK SELECT FUNCTION ( PD78F0892, 78F0893 ONLY) • Software example RAMD DSEG SADDR R_BNKA: ; Secures RAM for specifying an address at the calling destination. R_BNKN: ; Secures RAM for specifying a memory bank number at the calling destination. R_BNKRN: DS ;...
Page 89: Instruction Branch To Bank Area By Interrupt
μ CHAPTER 4 MEMORY BANK SELECT FUNCTION ( PD78F0892, 78F0893 ONLY) 4.4.4 Instruction branch to bank area by interrupt When an interrupt occurs, instructions can branch to the memory bank specified by the BANK register by using the vector table, but it is difficult to identify the BANK register when the interrupt occurs. Therefore, specify the branch destination address specified by the vector table in the common area (0000H to 7FFFH), specify the memory bank at the branch destination by using the BANK register in the common area, and execute the CALL instruction.
Page 90 μ CHAPTER 4 MEMORY BANK SELECT FUNCTION ( PD78F0892, 78F0893 ONLY) Remark Note the following points to use the memory bank select function efficiently. • Allocate a routine that is used often in the common area. • If a value that is planned to be referenced is placed in RAM, it can be referenced from all of the areas. •...
Page 91: Chapter 5 Port Functions
In addition to the function as digital I/O ports, these ports have several alternate functions. For details of the alternate functions, refer to CHAPTER 2 PIN FUNCTIONS. The 78K0/FF2 has a total of 71 I/O ports, ports 0, 1, 3 to 9, 12 and 13. The port configuration is shown below. User’s Manual U17553EJ4V0UD...
Page 92: Port Configuration
CHAPTER 5 PORT FUNCTIONS Figure 5-1. Port Types Port 0 Port 6 Port 1 Port 7 Port 3 Port 8 Port 4 Port 9 Port 5 P120 Port 12 P124 P130 Port 13 P132 5.2 Port Configuration Ports include the following hardware. Table 5-2.
Page 93: Port 0
CHAPTER 5 PORT FUNCTIONS 5.2.1 Port 0 Port 0 is a 4-bit I/O port with an output latch. Port 0 can be set to the input mode or output mode in 1-bit units using port mode register 0 (PM0). When the P00, P01, P05 and P06 pins are used as an input port, use of an on-chip pull-up resistor can be specified in 1-bit units by pull-up resistor option register 0 (PU0).
Page 94 CHAPTER 5 PORT FUNCTIONS Figure 5-3. Block Diagram of P01 and P06 PU01, PU06 P-ch Alternate function PORT Output latch P01/TI010/TO00, (P01, P06) P06/TI011/TO01 PM01, PM06 Alternate function Port register 0 PU0: Pull-up resistor option register 0 PM0: Port mode register 0 Read signal WR××: Write signal User’s Manual U17553EJ4V0UD...
Page 95: Port 1
CHAPTER 5 PORT FUNCTIONS 5.2.2 Port 1 Port 1 is an 8-bit I/O port with an output latch. Port 1 can be set to the input mode or output mode in 1-bit units using port mode register 1 (PM1). When the P10 to P17 pins are used as an input port, use of an on-chip pull-up resistor can be specified in 1-bit units by pull-up resistor option register 1 (PU1).
Page 96 CHAPTER 5 PORT FUNCTIONS Figure 5-5. Block Diagram of P11 and P14 PU11, PU14 P-ch Alternate function PORT Output latch P11/SI10/RxD61, (P11, P14) P14/RxD60 PM11, PM14 Port register 1 PU1: Pull-up resistor option register 1 PM1: Port mode register 1 Read signal WR××: Write signal User’s Manual U17553EJ4V0UD...
Page 97 CHAPTER 5 PORT FUNCTIONS Figure 5-6. Block Diagram of P12, P13 and P15 PU12, PU13, PU15 P-ch PORT Output latch (P12, P13, P15) P12/SO10, P13/TxD60, P15/TOH0 PM12, PM13, PM15 Alternate function Port register 1 PU1: Pull-up resistor option register 1 PM1: Port mode register 1 Read signal...
Page 98: Port 3
CHAPTER 5 PORT FUNCTIONS 5.2.3 Port 3 Port 3 is a 4-bit I/O port with an output latch. Port 3 can be set to the input mode or output mode in 1-bit units using port mode register 3 (PM3). When used as an input port, use of an on-chip pull-up resistor can be specified in 1-bit units by pull-up resistor option register 3 (PU3).
Page 99 CHAPTER 5 PORT FUNCTIONS Figure 5-8. Block Diagram of P32 and P33 PU32, PU33 P-ch Alternate function PORT Output latch P32/INTP3/TI012/TO02, (P32, P33) P33/INTP4/TI51/TO51 PM32, PM33 Alternate function Port register 3 PU3: Pull-up resistor option register 3 PM3: Port mode register 3 Read signal WR××: Write signal User’s Manual U17553EJ4V0UD...
Page 100: Port 4
CHAPTER 5 PORT FUNCTIONS 5.2.4 Port 4 Port 4 is a 8-bit I/O port with an output latch. Port 4 can be set to the input mode or output mode in 1-bit units using port mode register 4 (PM4). Use of an on-chip pull-up resistor can be specified in 1-bit units with pull-up resistor option register 4 (PU4).
Page 101: Port 5
CHAPTER 5 PORT FUNCTIONS 5.2.5 Port 5 Port 5 is 8-bit I/O port with an output latch. Port 5 can be set to the input mode or output mode in 1-bit units using port mode register 5 (PM5). Use of an on-chip pull-up resistor can be specified in 1-bit units using pull-up resistor option register 5 (PU5).
Page 102: Port 6
CHAPTER 5 PORT FUNCTIONS 5.2.6 Port 6 Port 6 is a 8-bit I/O port with an output latch. Port 6 can be set to the input mode or output mode in 1-bit units using port mode register 6 (PM6). P64 toP67 use of an on-chip pull-up resistor can be specified in 1-bit units using pull-up resistor option register 6 (PU6).
Page 103 CHAPTER 5 PORT FUNCTIONS Figure 5-12. Block Diagram of P64 to P67 PU64 to PU67 P-ch Selector PORT Output latch P64 to P67 (P64 to P67) PM64 to PM67 Port register 6 PU6: Pull-up resistor option register 6 PM6: Port mode register 6 Read signal WR××: Write signal User’s Manual U17553EJ4V0UD...
Page 104: Port 7
CHAPTER 5 PORT FUNCTIONS 5.2.7 Port 7 Port 7 is an 7-bit I/O port with an output latch. Port 7 can be set to the input mode or output mode in 1-bit units using port mode register 7 (PM7). When the P70 to P76 pins are used as an input port, use of an on-chip pull-up resistor can be specified in 1-bit units by pull-up resistor option register 7 (PU7).
Page 105 CHAPTER 5 PORT FUNCTIONS Figure 5-14. Block Diagram of P71 and P75 PU71 and PU75 P-ch Alternate function PORT Output latch P71/CRxD (P71 and P75) P75/SI11 PM71 and PM75 Port register 7 PU7: Pull-up resistor option register 7 PM7: Port mode register 7 Read signal WR××: Write signal User’s Manual U17553EJ4V0UD...
Page 106 CHAPTER 5 PORT FUNCTIONS <R> Figure 5-15. Block Diagram of P72 and P73 PU72 and PU73 P-ch Alternate function PORT Output latch P72/PCL/INTP6 (P72 and P73) P73/BUZ/INTP7 PM72 and PM73 Alternate function Port register 7 PU7: Pull-up resistor option register 7 PM7: Port mode register 7 Read signal...
Page 107 CHAPTER 5 PORT FUNCTIONS <R> Figure 5-16. Block Diagram of P74 PU74 P-ch PORT Output latch (P74) P74/SO11 PM74 Alternate function Port register 7 PU7: Pull-up resistor option register 7 PM7: Port mode register 7 Read signal WR××: Write signal User’s Manual U17553EJ4V0UD...
Page 108 CHAPTER 5 PORT FUNCTIONS <R> Figure 5-17. Block Diagram of P76 PU76 P-ch Alternate function PORT Output latch P76/SCK11 (P76) PM76 Alternate function Port register 7 PU7: Pull-up resistor option register 7 PM7: Port mode register 7 Read signal WR××: Write signal User’s Manual U17553EJ4V0UD...
Page 109: Port 8
CHAPTER 5 PORT FUNCTIONS 5.2.8 Port 8 Port 8 is an 8-bit I/O port with an output latch. Port 8 can be set to the input mode or output mode in 1-bit units using port mode register 8 (PM8). This port can also be used for A/D converter analog input. To use P80/ANI0 to P87/ANI7 as digital input pins, set them in the digital I/O mode by using the A/D port configuration register (ADPC) and in the input mode by using PM8.
Page 110: Port 9
CHAPTER 5 PORT FUNCTIONS 5.2.9 Port 9 Port 9 is an 8-bit I/O port with an output latch. Port 9 can be set to the input mode or output mode in 1-bit units using port mode register 9 (PM9). This port can also be used for A/D converter analog input. To use P90/ANI8 to P97/ANI15 as digital input pins, set them in the digital I/O mode by using the A/D port configuration register (ADPC) and in the input mode by using PM9.
Page 111: Port 12
CHAPTER 5 PORT FUNCTIONS 5.2.10 Port 12 Port 12 is a 5-bit I/O port with an output latch. Port 12 can be set to the input mode or output mode in 1-bit units using port mode register 12 (PM12). When used as an input port only for P120, use of an on-chip pull-up resistor can be specified by pull-up resistor option register 12 (PU12).
Page 112 CHAPTER 5 PORT FUNCTIONS Figure 5-20. Block Diagram of P120 PU12 PU120 P-ch Alternate function PORT Output latch P120/INTP0/EXLVI (P120) PM12 PM120 P12: Port register 12 PU12: Pull-up resistor option register 12 PM12: Port mode register 12 Read signal WR××: Write signal User’s Manual U17553EJ4V0UD...
Page 113 CHAPTER 5 PORT FUNCTIONS Figure 5-21. Block Diagram of P121 to P124 OSCCTL OSCSEL/ OSCSELS PORT Output latch P122/X2/EXCLK, (P122/P124) P124/XT2/EXCLKS PM12 PM122/PM124 OSCCTL OSCSEL/ OSCSELS OSCCTL EXCLK, OSCSEL/ EXCLKS, OSCSELS PORT Output latch (P121/P123) P121/X1, P123/XT1 PM12 PM121/PM123 OSCCTL OSCSEL/OSCSELS OSCCTL EXCLK/EXCLKS...
Page 114: Port 13
CHAPTER 5 PORT FUNCTIONS 5.2.11 Port 13 Port 130 is a 1-bit output-only port. Port 131 and 132 are 2-bit I/O port. P131 and P132 can be set to the input mode or output mode in 1-bit units using port mode register 13 (PM13). When used as an input port, use of an on-chip pull-up resistor can be specified in 1-bit units by pull-up resistor option register 13 (PU13).
Page 115 CHAPTER 5 PORT FUNCTIONS Figure 5-23. Block Diagram of P131 PU13 PU131 P-ch Alternate function PORT Output latch P131/TI003 (P131) PM13 PM131 P13: Port register 13 PU13: Pull-up resistor option register 13 PM13: Port mode register 13 Read signal WR××: Write signal User’s Manual U17553EJ4V0UD...
Page 116 CHAPTER 5 PORT FUNCTIONS Figure 5-24. Block Diagram of P132 PU13 PU132 P-ch Alternate function PORT Output latch P132/TI013/TO03 (P132) PM13 PM132 Alternate function P13: Port register 13 PU13: Pull-up resistor option register 13 PM13: Port mode register 13 Read signal WR××: Write signal User’s Manual U17553EJ4V0UD...
Page 117: Registers Controlling Port Function
CHAPTER 5 PORT FUNCTIONS 5.3 Registers Controlling Port Function Port functions are controlled by the following three types of registers. • Port mode registers (PM0, PM1, PM3 to PM9, PM12, PM13) • Port registers (P0, P1, P3 to P9, P12, P13) •...
Page 118 CHAPTER 5 PORT FUNCTIONS (1) Port mode registers (PM0, PM1, PM3 to PM9, PM12, PM13) These registers specify input or output mode for the port in 1-bit units. These registers can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation sets these registers to FFH except for PM13.
Page 119 CHAPTER 5 PORT FUNCTIONS Table 5-5. Settings of Port Mode Register and Output Latch When Using Alternate Function (1/2) Alternate Function PM×× P×× Pin Name Function Name × TI000 Input × TI010 Input TO00 Output × SSI11 Input × TI001 Input ×...
Page 120 CHAPTER 5 PORT FUNCTIONS Table 5-5. Settings of Port Mode Register and Output Latch When Using Alternate Function (2/2) Alternate Function PM×× P×× Pin Name Function Name × SCK11 Input Output × ANI0-ANI7 Input P80-P87 × ANI8-ANI15 Input P90-P97 × INTP0 Input P120...
Page 121 CHAPTER 5 PORT FUNCTIONS (2) Port registers (P0, P1, P3 to P9, P12, P13) These registers write the data that is output from the chip when data is output from a port. If the data is read in the input mode, the pin level is read. If it is read in the output mode, the value of the output latch is read.
Page 122 CHAPTER 5 PORT FUNCTIONS Pull-up resistor option registers (PU0, PU1, PU3 to PU7, PU12, PU13) These registers specify whether the on-chip pull-up resistors of P00, P01, P05, P06, P10 to P17, P30 to P33, P40 to P47, P50 to P57, P64 to P67, P70 to P76, P120, P131 and P132 are to be used or not. On-chip pull-up resistors can be used in 1-bit units only for the bits set to input mode of the pins to which the use of an on-chip pull-up resistor has been specified in PU0, PU1, PU3 to PU7, PU12, and PU13.
Page 123 CHAPTER 5 PORT FUNCTIONS (4) A/D port configuration register (ADPC) This register switches the P80/ANI0 to P87/ANI7 and P90/ANI8 to P97/ANI15 pins to digital I/O of port or analog input of A/D converter. ADPC can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears this register to 00H.
Page 124: Port Function Operations
CHAPTER 5 PORT FUNCTIONS 5.4 Port Function Operations Port operations differ depending on whether the input or output mode is set, as shown below. 5.4.1 Writing to I/O port (1) Output mode A value is written to the output latch by a transfer instruction, and the output latch contents are output from the pin. Once data is written to the output latch, it is retained until data is written to the output latch again.
Page 125: Cautions On 1-Bit Manipulation Instruction For Port Register N (Pn)
The targets of writing to and reading from the Pn register of a port whose PMnm bit is 1 are the output latch and pin status, respectively. A 1-bit manipulation instruction is executed in the following order in the 78K0/FF2. <1> The Pn register is read in 8-bit units.
Page 126: Chapter 6 Clock Generator
CHAPTER 6 CLOCK GENERATOR 6.1 Functions of Clock Generator The clock generator generates the clock to be supplied to the CPU and peripheral hardware. The following system clocks and clock oscillators are selectable. (1) Main system clock <1> X1 oscillator This circuit oscillates a clock of f = 4 to 20 MHz.
Page 127: Configuration Of Clock Generator
CHAPTER 6 CLOCK GENERATOR 6.2 Configuration of Clock Generator The clock generator includes the following hardware. Table 6-1. Configuration of Clock Generator Item Configuration Control registers Processor clock control register (PCC) Internal oscillator mode register (RCM) Main clock mode register (MCM) Main OSC control register (MOC) Clock operation mode select register (OSCCTL) Oscillation stabilization time counter status register (OSTC)
Page 128 Figure 6-1. Block Diagram of Clock Generator Internal bus Main OSC Main clock Clock operation mode Main clock Processor clock Oscillation stabilization control register mode register select register mode register control register time select register (OSTS) (MOC) (MCM) (OSCCTL) (MCM) (PCC) AMPH EXCLK OSCSEL...
Page 129: Registers Controlling Clock Generator
CHAPTER 6 CLOCK GENERATOR Remarks 1. X1 clock oscillation frequency Internal high-speed oscillation clock frequency : External main system clock frequency EXCLK High-speed system clock oscillation frequency Main system clock oscillation frequency Peripheral hardware clock frequency CPU clock oscillation frequency XT1 clock oscillation frequency : External subsystem clock frequency EXCLKS...
Page 130 2. f : Subsystem clock frequency The fastest instruction can be executed in 2 clocks of the CPU clock in the 78K0/FF2. Therefore, the relationship between the CPU clock (f ) and the minimum instruction execution time is as shown in Table 6-2.
Page 131 CHAPTER 6 CLOCK GENERATOR (2) Internal oscillator mode register (RCM) This register sets the operation mode of internal oscillator. RCM can be set by a 1-bit or 8-bit memory manipulation instruction. Note 1 Reset signal generation sets this register to 80H Figure 6-3.
Page 132 CHAPTER 6 CLOCK GENERATOR (3) Main clock mode register (MCM) This register selects the main system clock supplied to CPU clock and clock supplied to peripheral hardware clock. MCM can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears this register to 00H.
Page 133 CHAPTER 6 CLOCK GENERATOR (4) Main OSC control register (MOC) This register selects the operation mode of the high-speed system clock. This register is used to stop the X1 oscillator or to disable an external clock input from the EXCLK pin when the CPU operates with a clock other than the high-speed system clock.
Page 134 CHAPTER 6 CLOCK GENERATOR (5) Clock operation mode select register (OSCCTL) This register selects the operation modes of the high-speed system and subsystem clocks. OSCCTL can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears this register to 00H. Figure 6-6.
Page 135 CHAPTER 6 CLOCK GENERATOR Cautions 5. To change the value of EXCLK and OSCSEL, be sure to confirm that bit 7 (MSTOP) of the main OSC control register (MOC) is 1 (the X1 oscillator stops or the external clock from the EXCLK pin is disabled). 6.
Page 136 CHAPTER 6 CLOCK GENERATOR (6) Oscillation stabilization time counter status register (OSTC) This is the status register of the X1 clock oscillation stabilization time counter. If the internal high-speed oscillation clock or subsystem clock is used as the CPU clock, the X1 clock oscillation stabilization time can be checked.
Page 137 CHAPTER 6 CLOCK GENERATOR (7) Oscillation stabilization time select register (OSTS) This register is used to select the X1 clock oscillation stabilization wait time when the STOP mode is released. The wait time set by OSTS is valid only after the STOP mode is released with the X1 clock selected as the CPU clock.
Page 138: System Clock Oscillator
CHAPTER 6 CLOCK GENERATOR 6.4 System Clock Oscillator 6.4.1 X1 oscillator The X1 oscillator oscillates with a crystal resonator or ceramic resonator (4 to 20 MHz) connected to the X1 and X2 pins. An external clock can also be input. In this case, input the clock signal to the EXCLK pin. Figure 6-9 shows an example of the external circuit of the X1 oscillator.
Page 139 CHAPTER 6 CLOCK GENERATOR Caution When using the X1 oscillator and XT1 oscillator, wire as follows in the area enclosed by the broken lines in the Figures 6-9 and 6-10 to avoid an adverse effect from wiring capacitance. • Keep the wiring length as short as possible. •...
Page 140 CHAPTER 6 CLOCK GENERATOR Figure 6-11. Examples of Incorrect Resonator Connection (2/2) (c) Wiring near high alternating current (d) Current flowing through ground line of oscillator (potential at points A, B, and C fluctuates) High current (e) Signals are fetched Remark When using the subsystem clock, replace X1 and X2 with XT1 and XT2, respectively.
Page 141: When Subsystem Clock Is Not Used
PM123, PM124: Bits 3 and 4 of port mode register 12 (PM12) 6.4.4 Internal high-speed oscillator The internal high-speed oscillator is incorporated in the 78K0/FF2. Oscillation can be controlled by the internal oscillator mode register (RCM). After a RESET release, the internal high-speed oscillation clock starts oscillation (8 MHz (TYP.)).
Page 142: Clock Generator Operation
• Peripheral hardware clock f The CPU starts operation when the on-chip internal high-speed oscillator starts outputting after a reset release in the 78K0/FF2, thus enabling the following. (1) Enhancement of security function When the X1 clock is set as the CPU clock by the default setting, the device cannot operate if the X1 clock is damaged or badly connected and therefore does not operate after reset is released.
Page 143 CHAPTER 6 CLOCK GENERATOR Figure 6-12 Operation of the clock generating circuit when power supply voltage injection (When 1.59 V POC mode setup (option byte: LVISTART = 0)) Power supply 1.8 V voltage (V 1.59 V (TYP.) 0.5 V/ms (MIN.) Internal reset signal <1>...
Page 144 CHAPTER 6 CLOCK GENERATOR Cautions 1. When the standup of voltage until it reaches 1.8 V from the time of a power supply injection is looser than 0.5 V/ms (MAX.), input a low level into RESET pin, or set up 2.7 V/1.59 V POC mode (LVISTART = 1) from an option byte until it reaches 1.8 V from the time of a power supply injection (refer to Figure 6-13).
Page 145 CHAPTER 6 CLOCK GENERATOR Figure 6-13 Operation of the clock generating circuit when power supply voltage injection (When 2.7 V/1.59V POC mode setup (option byte: LVISTART = 1)) 2.7 V (TYP.) Power supply voltage (V Internal reset signal <1> Reset processing <3>...
Page 146: Controlling Clock
CHAPTER 6 CLOCK GENERATOR remark The clock which is not used as a CPU clock can be suspended by setup of software during microcomputer operation. Moreover, high-speed oscillation clock and a high-speed system clock can suspend a clock by execution of a STOP command (see (4) in 6.6.1 Controlling high-speed system clock, (3) in 6.6.2 Example of controlling internal high-speed oscillation clock, and (4) in 6.6.3 Example of controlling subsystem clock).
Page 147 CHAPTER 6 CLOCK GENERATOR <4> Waiting for the stabilization of the oscillation of X1 clock Check the OSTC register and wait for the necessary time. During the wait time, other software processing can be executed with the internal high-speed oscillation clock.
Page 148 CHAPTER 6 CLOCK GENERATOR <2> Setting the high-speed system clock as the main system clock (MCM register) When XSEL and MCM0 are set to 1, the high-speed system clock is supplied as the main system clock and peripheral hardware clock. XSEL MCM0 Selection of Main System Clock and Clock Supplied to Peripheral Hardware...
Page 149: Example Of Controlling Internal High-Speed Oscillation Clock
CHAPTER 6 CLOCK GENERATOR (b) To stop X1 oscillation (disabling external clock input) by setting MSTOP to 1 <1> Confirming the CPU clock status (PCC and MCM registers) Confirm with CLS and MCS that the CPU is operating on a clock other than the high-speed system clock.
Page 150 CHAPTER 6 CLOCK GENERATOR Note The setting of <1> is not necessary when the internal high-speed oscillation clock or high- speed system clock is already operating. <2> Selecting the clock supplied as the main system clock and peripheral hardware clock (MCM register) Set the main system clock and peripheral hardware clock using XSEL and MCM0.
Page 151: Example Of Controlling Subsystem Clock
CHAPTER 6 CLOCK GENERATOR (b) To stop internal high-speed oscillation clock by setting RSTOP to 1 <1> Confirming the CPU clock status (PCC and MCM registers) Confirm with CLS and MCS that the CPU is operating on a clock other than the internal high-speed oscillation clock.
Page 152 CHAPTER 6 CLOCK GENERATOR (2) Example of setting procedure when using the external subsystem clock <1> Setting XT1 and XT2 pins, selecting XT1 clock/external clock and controlling oscillation (PCC and OSCCTL registers) When XTSTART is cleared to 0 and EXCLKS and OSCSELS are set to 1, the mode is switched from port mode to external clock input mode.
Page 153: Controlling Internal Low-Speed Oscillation Clock
CHAPTER 6 CLOCK GENERATOR 6.6.4 Controlling internal low-speed oscillation clock The internal low-speed oscillation clock is a clock for the watchdog timer. It cannot be used as the CPU clock. With this clock, only the following peripheral hardware can operate. •...
Page 154: Cpu Clock Status Transition Diagram
CHAPTER 6 CLOCK GENERATOR 6.6.6 CPU clock status transition diagram Figure 6-14 shows the CPU clock status transition diagram of this product. Figure 6-14. CPU Clock Status Transition Diagram Internal low-speed oscillation: Woken up Power ON Internal high-speed oscillation: Woken up X1 oscillation/EXCLK input: Stops (I/O port mode) XT1 oscillation/EXCLKS input: Stops (I/O port mode) <...
Page 155 CHAPTER 6 CLOCK GENERATOR Table 6-4 shows transition of the CPU clock and examples of setting the SFR registers. Table 6-4. CPU Clock Transition and SFR Register Setting Examples (1/4) (1) CPU operating with high-speed system clock (C) after reset release (A) (The CPU operates with the internal high-speed oscillation clock immediately after a reset release (B).) (Setting sequence of SFR registers) Setting Flag of SFR Register...
Page 156 CHAPTER 6 CLOCK GENERATOR Table 6-4. CPU Clock Transition and SFR Register Setting Examples (2/4) (4) CPU clock changing from internal high-speed oscillation clock (B) to high-speed system clock (C) (Setting sequence of SFR registers) Setting Flag of SFR Register AMPH EXCLK OSCSEL...
Page 157 CHAPTER 6 CLOCK GENERATOR Table 6-4. CPU Clock Transition and SFR Register Setting Examples (3/4) (6) CPU clock changing from high-speed system clock (C) to internal high-speed oscillation clock (B) (Setting sequence of SFR registers) Setting Flag of SFR Register RSTOP RSTS MCM0...
Page 158 CHAPTER 6 CLOCK GENERATOR Table 6-4. CPU Clock Transition and SFR Register Setting Examples (4/4) (9) CPU clock changing from subsystem clock (D) to internal high-speed oscillation clock (B) (Setting sequence of SFR registers) Setting Flag of SFR Register RSTOP RSTS MCM0 Status Transition...
Page 159: Condition Before Changing Cpu Clock And Processing After Changing Cpu Clock
CHAPTER 6 CLOCK GENERATOR 6.6.7 Condition before changing CPU clock and processing after changing CPU clock Condition before changing the CPU clock and processing after changing the CPU clock are shown below. Table 6-5. Changing CPU Clock CPU Clock Condition Before Change Processing After Change Before Change After Change...
Page 160: Time Required For Switchover Of Cpu Clock And Main System Clock
CHAPTER 6 CLOCK GENERATOR 6.6.8 Time required for switchover of CPU clock and main system clock By setting bits 0 to 2 (PCC0 to PCC2) and bit 4 (CSS) of the processor clock control register (PCC), the CPU clock can be switched (between the main system clock and the subsystem clock) and the division ratio of the main system clock can be changed.
Page 161: Conditions Before Clock Oscillation Is Stopped
CHAPTER 6 CLOCK GENERATOR Table 6-7. Maximum Time Required for Main System Clock Switchover Set Value Before Switchover Set Value After Switchover MCM0 MCM0 1 + 2f clock 1 + 2f clock Caution When switching the internal high-speed oscillation clock to the high-speed system clock, bit 2 (XSEL) of MCM must be set to 1 in advance.
Page 162: Chapter 7 16-Bit Timer/Event Counters 00 To 03
CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 TO 03 The 78K0/FF2 incorporates 16-bit timer/event counters 00 to 03. 7.1 Functions of 16-Bit Timer/Event Counters 00 to 03 16-bit timer/event counters 00 to 03 have the following functions. • Interval timer • PPG output •...
Page 163: Configuration Of 16-Bit Timer/Event Counters 00 To 03
CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 TO 03 7.2 Configuration of 16-Bit Timer/Event Counters 00 to 03 16-bit timer/event counters 00 to 03 include the following hardware. Table 7-1. Configuration of 16-Bit Timer/Event Counters 00 to 03 Item Configuration Timer counter 16 bits (TM0n) Register 16-bit timer capture/compare register: 16 bits (CR00n, CR01n)
Page 164 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 TO 03 Figure 7-2. Block Diagram of 16-Bit Timer/Event Counter 01 Internal bus Capture/compare control register 01 (CRC01) CRC012CRC011 CRC010 INTTM001 Noise 16-bit timer capture/compare TI011/TO01/P06 elimi- register 001 (CR001) nator Match 16-bit timer counter 01 Clear (TM01) Output...
Page 165 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 TO 03 Figure 7-4. Block Diagram of 16-Bit Timer/Event Counter 03 Internal bus Capture/compare control register 03 (CRC03) CRC032CRC031 CRC030 INTTM003 16-bit timer capture/compare Noise elimi- TI013/TO03/P132 register 003 (CR003) nator Match 16-bit timer counter 03 Clear (TM03) Output...
Page 166 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 TO 03 (1) 16-bit timer counter 0n (TM0n) TM0n is a 16-bit read-only register that counts count pulses. The counter is incremented in synchronization with the rising edge of the count clock. If the count value is read during operation, then input of the count clock is temporarily stopped, and the count value at that point is read.
Page 167 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 TO 03 (2) 16-bit timer capture/compare register 00n (CR00n) CR00n is a 16-bit register that has the functions of both a capture register and a compare register. Whether it is used as a capture register or as a compare register is set by bit 0 (CRC0n0) of capture/compare control register 0n (CRC0n).
Page 168 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 TO 03 Table 7-2. CR00n Capture Trigger and Valid Edges of TI00n and TI01n Pins (1) TI00n pin valid edge selected as capture trigger (CRC0n1 = 1, CRC0n0 = 1) CR00n Capture Trigger TI00n Pin Valid Edge ES0n1 ES0n0 Falling edge...
Page 169 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 TO 03 (3) 16-bit timer capture/compare register 01n (CR01n) CR01n is a 16-bit register that has the functions of both a capture register and a compare register. Whether it is used as a capture register or a compare register is set by bit 2 (CRC0n2) of capture/compare control register 0n (CRC0n).
Page 170 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 TO 03 (4) Setting range when CR00n or CR01n is used as a compare register When CR00n or CR01n is used as a compare register, set it as shown below. Operation CR00n Register Setting Range CR01n Register Setting Range 0000H <...
Page 171 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 TO 03 Table 7-4. Capture Operation of CR00n and CR01n External Input Signal TI00n Pin Input TI01n Pin Input Capture Operation Capture operation of CRC0n1 = 1 Set values of ES0n1 and CRC0n1 bit = 0 Set values of ES1n1 and CR00n TI00n pin input...
Page 172: Registers Controlling 16-Bit Timer/Event Counters 00 To 03
CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 TO 03 7.3 Registers Controlling 16-Bit Timer/Event Counters 00 to 03 The following six registers are used to control 16-bit timer/event counters 00 to 03. • 16-bit timer mode control register 0n (TMC0n) • Capture/compare control register 0n (CRC0n) •...
Page 173 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 TO 03 Figure 7-8. Format of 16-Bit Timer Mode Control Register 00 (TMC00) Address: FFBAH After reset: 00H Symbol <0> TMC00 TMC003 TMC002 TMC001 OVF00 TMC003 TMC002 Operation enable of 16-bit timer/event counter 00 Disables 16-bit timer/event counter 00 operation.
Page 174 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 TO 03 Figure 7-9. Format of 16-Bit Timer Mode Control Register 01 (TMC01) Address: FFB6H After reset: 00H Symbol <0> TMC01 TMC013 TMC012 TMC011 OVF01 TMC013 TMC012 Operation enable of 16-bit timer/event counter 01 Disables 16-bit timer/event counter 01 operation.
Page 175 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 TO 03 Figure 7-10. Format of 16-Bit Timer Mode Control Register 02 (TMC02) Address: FF54H After reset: 00H Symbol <0> TMC02 TMC023 TMC022 TMC021 OVF02 TMC023 TMC022 Operation enable of 16-bit timer/event counter 01 Disables 16-bit timer/event counter 02 operation.
Page 176 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 TO 03 Figure 7-11. Format of 16-Bit Timer Mode Control Register 03 (TMC03) Address: FFADH After reset: 00H Symbol <0> TMC03 TMC033 TMC032 TMC031 OVF03 TMC033 TMC032 Operation enable of 16-bit timer/event counter 03 Disables 16-bit timer/event counter 03 operation.
Page 177 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 TO 03 (2) Capture/compare control register 0n (CRC0n) CRC0n is the register that controls the operation of CR00n and CR01n. Changing the value of CRC0n is prohibited during operation (when TMC0n3 and TMC0n2 = other than 00). CRC0n can be set by a 1-bit or 8-bit memory manipulation instruction.
Page 178 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 TO 03 Figure 7-13. Example of CR01n Capture Operation (When Rising Edge Is Specified) Valid edge Count clock N − 3 N − 2 N − 1 TM0n N + 1 TI00n Rising edge detection CR01n INTTM01n Remark n = 0 to 3...
Page 179 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 TO 03 Figure 7-15. Format of Capture/Compare Control Register 02 (CRC02) Address: FF5CH After reset: 00H Symbol CRC02 CRC022 CRC021 CRC020 CRC022 CR012 operating mode selection Operates as compare register Operates as capture register CRC021 CR002 capture trigger selection Captures on valid edge of TI012 pin...
Page 180 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 TO 03 Figure 7-16. Format of Capture/Compare Control Register 03 (CRC03) Address: FF52H After reset: 00H Symbol CRC03 CRC032 CRC031 CRC030 CRC032 CR013 operating mode selection Operates as compare register Operates as capture register CRC031 CR003 capture trigger selection Captures on valid edge of TI013 pin...
Page 181 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 TO 03 (3) 16-bit timer output control register 0n (TOC0n) TOC0n is an 8-bit register that controls the TO0n pin output. TOC0n can be rewritten while only OSPT0n is operating (when TMC0n3 and TMC0n2 = other than 00). Rewriting the other bits is prohibited during operation.
Page 182 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 TO 03 Figure 7-17. Format of 16-Bit Timer Output Control Register 00 (TOC00) Address: FFBDH After reset: 00H Symbol <6> <5> <3> <2> <0> TOC00 OSPT00 OSPE00 TOC004 LVS00 LVR00 TOC001 TOE00 OSPT00 One-shot pulse output trigger via software −...
Page 183 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 TO 03 Figure 7-18. Format of 16-Bit Timer Output Control Register 01 (TOC01) Address: FFB9H After reset: 00H Symbol <6> <5> <3> <2> <0> TOC01 OSPT01 OSPE01 TOC014 LVS01 LVR01 TOC011 TOE01 OSPT01 One-shot pulse output trigger via software −...
Page 184 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 TO 03 Figure 7-19. Format of 16-Bit Timer Output Control Register 02 (TOC02) Address: FFA5H After reset: 00H Symbol <6> <5> <3> <2> <0> TOC02 OSPT02 OSPE02 TOC024 LVS02 LVR02 TOC021 TOE02 OSPT02 One-shot pulse output trigger via software −...
Page 185 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 TO 03 Figure 7-20. Format of 16-Bit Timer Output Control Register 03 (TOC03) Address: FFF9H After reset: 00H Symbol <6> <5> <3> <2> <0> TOC03 OSPT03 OSPE03 TOC034 LVS03 LVR03 TOC031 TOE03 OSPT03 One-shot pulse output trigger via software −...
Page 186 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 TO 03 (4) Prescaler mode register 0n (PRM0n) PRM0n is the register that sets the TM0n count clock and TI00n and TI01n pin input valid edges. Rewriting PRM0n is prohibited during operation (when TMC0n3 and TMC0n2 = other than 00). PRM0n can be set by a 1-bit or 8-bit memory manipulation instruction.
Page 187 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 TO 03 Figure 7-21. Format of Prescaler Mode Register 00 (PRM00) Address: FFBBH After reset: 00H Symbol PRM00 ES101 ES100 ES001 ES000 PRM001 PRM000 ES101 ES100 TI010 pin valid edge selection Falling edge Rising edge Setting prohibited Both falling and rising edges ES001...
Page 188 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 TO 03 Figure 7-22. Format of Prescaler Mode Register 01 (PRM01) Address: FFB7H After reset: 00H Symbol PRM01 ES111 ES110 ES011 ES010 PRM011 PRM010 ES111 ES110 TI011 pin valid edge selection Falling edge Rising edge Setting prohibited Both falling and rising edges ES011...
Page 189 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 TO 03 Figure 7-23. Format of Prescaler Mode Register 02 (PRM02) Address: FF59H After reset: 00H Symbol PRM02 ES121 ES120 ES021 ES020 PRM021 PRM020 ES121 ES120 TI012 pin valid edge selection Falling edge Rising edge Setting prohibited Both falling and rising edges ES021...
Page 190 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 TO 03 Figure 7-24. Format of Prescaler Mode Register 03 (PRM03) Address: FF51H After reset: 00H Symbol PRM03 ES131 ES130 ES031 ES030 PRM031 PRM030 ES131 ES130 TI013 pin valid edge selection Falling edge Rising edge Setting prohibited Both falling and rising edges ES031...
Page 191 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 TO 03 (5) Port mode register 0 (PM0) This register sets port 0 input/output in 1-bit units. When using the P01/TO00/TI010 and P06/TO01/TI011 pins for timer output, set PM01 and PM06 and the output latch of P01 and P06 to 0.
Page 192 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 TO 03 (7) Port mode register 13 (PM13) This register sets port 13 input/output in 1-bit units. When using the P132/TO03/TI013 pin for timer output, set PM132 and the output latch of P132 to 0. When using the P131/TI003 and P132/TI013/TO03 pins for timer input, set PM131 and PM132 to 1.
Page 193: Operation Of 16-Bit Timer/Event Counters 00 To 03
CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 TO 03 7.4 Operation of 16-Bit Timer/Event Counters 00 to 03 7.4.1 Interval timer operation Setting 16-bit timer mode control register 0n (TMC0n) and capture/compare control register 0n (CRC0n) as shown in Figure 7-28 allows operation as an interval timer. Setting The basic operation setting procedure is as follows.
Page 194 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 TO 03 Figure 7-28. Control Register Settings for Interval Timer Operation (a) 16-bit timer mode control register 0n (TMC0n) TMC0n3 TMC0n2 TMC0n1 OVF0n TMC0n Clears and starts on match between TM0n and CR00n. (b) Capture/compare control register 0n (CRC0n) CRC0n2 CRC0n1 CRC0n0...
Page 195 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 TO 03 Figure 7-29. Interval Timer Configuration Diagram 16-bit timer capture/compare register 00n (CR00n) INTTM00n Note 1 Note 1 Note 2 16-bit timer counter 0n OVF0n Note 1 (TM0n) Noise TI000/P00 eliminator (TI001/P05) Clear TI002/P31 circuit Note 1...
Page 196: Ppg Output Operations
CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 TO 03 7.4.2 PPG output operations Setting 16-bit timer mode control register 0n (TMC0n) and capture/compare control register 0n (CRC0n) as shown in Figure 7-31 allows operation as PPG (Programmable Pulse Generator) output. Setting The basic operation setting procedure is as follows.
Page 197 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 TO 03 Figure 7-31. Control Register Settings for PPG Output Operation (a) 16-bit timer mode control register 0n (TMC0n) TMC0n3 TMC0n2 TMC0n1 OVF0n TMC0n Clears and starts on match between TM0n and CR00n. (b) Capture/compare control register 0n (CRC0n) CRC0n2 CRC0n1 CRC0n0...
Page 198 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 TO 03 Figure 7-32. Configuration Diagram of PPG Output 16-bit timer capture/compare register 00n (CR00n) Note Note Clear 16-bit timer counter 0n Note circuit (TM0n) Noise TI000/P00 eliminator (TI001/P05) TI002/P31 TO00/TI010/P01 Note (TI003/P131) (TO01/TI011/P06) TO02/TI012/P32 Note (TO03/TI013/P132)
Page 199: Pulse Width Measurement Operations
CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 TO 03 7.4.3 Pulse width measurement operations It is possible to measure the pulse width of the signals input to the TI00n pin and TI01n pin using 16-bit timer counter 0n (TM0n). There are two measurement methods: measuring with TM0n used in free-running mode, and measuring by restarting the timer in synchronization with the edge of the signal input to the TI00n pin.
Page 200 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 TO 03 (1) Pulse width measurement with free-running counter and one capture register When 16-bit timer counter 0n (TM0n) is operated in free-running mode, and the edge specified by prescaler mode register 0n (PRM0n) is input to the TI00n pin, the value of TM0n is taken into 16-bit timer capture/compare register 01n (CR01n) and an external interrupt request signal (INTTM01n) is set.
Page 201 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 TO 03 Figure 7-36. Configuration Diagram for Pulse Width Measurement with Free-Running Counter Note 16-bit timer counter 0n Note OVF0n (TM0n) Note 16-bit timer capture/compare TI00n register 01n (CR01n) INTTM01n Internal bus Note Frequencies without parentheses are for 16-bit timer/event counter 00 and 02, and those in parentheses are for 16-bit timer/event counter 01 and 03.
Page 202 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 TO 03 (2) Measurement of two pulse widths with free-running counter When 16-bit timer counter 0n (TM0n) is operated in free-running mode, it is possible to simultaneously measure the pulse widths of the two signals input to the TI00n pin and the TI01n pin. When the edge specified by bits 4 and 5 (ES0n0 and ES0n1) of prescaler mode register 0n (PRM0n) is input to the TI00n pin, the value of TM0n is taken into 16-bit timer capture/compare register 01n (CR01n) and an interrupt request signal (INTTM01n) is set.
Page 203 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 TO 03 Figure 7-39. Timing of Pulse Width Measurement Operation with Free-Running Counter (with Both Edges Specified) Count clock 0000H 0001H D0 + 1 D1 + 1 FFFFH 0000H D2 + 1 D2 + 2 TM0n count value TI00n pin input CR01n capture value...
Page 204 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 TO 03 (3) Pulse width measurement with free-running counter and two capture registers When 16-bit timer counter 0n (TM0n) is operated in free-running mode, it is possible to measure the pulse width of the signal input to the TI00n pin. When the rising or falling edge specified by bits 4 and 5 (ES0n0 and ES0n1) of prescaler mode register 0n (PRM0n) is input to the TI00n pin, the value of TM0n is taken into 16-bit timer capture/compare register 01n (CR01n) and an interrupt request signal (INTTM01n) is set.
Page 205 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 TO 03 Figure 7-41. Timing of Pulse Width Measurement Operation with Free-Running Counter and Two Capture Registers (with Rising Edge Specified) Count clock TM0n count value 0000H 0001H D0 + 1 D1 + 1 FFFFH 0000H D2 + 1...
Page 206 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 TO 03 Figure 7-42. Control Register Settings for Pulse Width Measurement by Means of Restart (with Rising Edge Specified) (a) 16-bit timer mode control register 0n (TMC0n) TMC0n3 TMC0n2 TMC0n1 OVF0n TMC0n Clears and starts at valid edge of TI00n pin. (b) Capture/compare control register 0n (CRC0n) CRC0n2 CRC0n1...
Page 207: External Event Counter Operation
CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 TO 03 7.4.4 External event counter operation Setting The basic operation setting procedure is as follows. <1> Set the CRC0n register (see Figure 7-44 for the set value). <2> Set the count clock by using the PRM0n register. <3>...
Page 208 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 TO 03 Figure 7-44. Control Register Settings in External Event Counter Mode (with Rising Edge Specified) (a) 16-bit timer mode control register 0n (TMC0n) TMC0n3 TMC0n2 TMC0n1 OVF0n TMC0n Clears and starts on match between TM0n and CR00n. (b) Capture/compare control register 0n (CRC0n) CRC0n2 CRC0n1...
Page 209 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 TO 03 Figure 7-45. Configuration Diagram of External Event Counter Internal bus 16-bit timer capture/compare register 00n (CR00n) Match INTTM00n Clear Note Valid edge of TI00n pin Noise eliminator OVF0n 16-bit timer counter 0n (TM0n) Note OVF0n is set to 1 only when CR00n is set to FFFFH.
Page 210: Square-Wave Output Operation
CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 TO 03 7.4.5 Square-wave output operation Setting The basic operation setting procedure is as follows. <1> Set the count clock by using the PRM0n register. <2> Set the CRC0n register (see Figure 7-47 for the set value). <3>...
Page 211 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 TO 03 Figure 7-47. Control Register Settings in Square-Wave Output Mode (2/2) (c) 16-bit timer output control register 0n (TOC0n) OSPT0n OSPE0n TOC0n4 LVS0n LVR0n TOC0n1 TOE0n TOC0n Enables TO0n output. Inverts output on match between TM0n and CR00n. Specifies initial value of TO0n output F/F (setting “11”...
Page 212: One-Shot Pulse Output Operation
CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 TO 03 7.4.6 One-shot pulse output operation 16-bit timer/event counter 0n can output a one-shot pulse in synchronization with a software trigger or an external trigger (TI00n pin input). Setting The basic operation setting procedure is as follows. <1>...
Page 213 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 TO 03 Figure 7-49. Control Register Settings for One-Shot Pulse Output with Software Trigger (a) 16-bit timer mode control register 0n (TMC0n) TMC0n3 TMC0n2 TMC0n1 OVF0n TMC0n Free-running mode (b) Capture/compare control register 0n (CRC0n) CRC0n2 CRC0n1 CRC0n0 CRC0n CR00n as compare register...
Page 214 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 TO 03 Figure 7-50. Timing of One-Shot Pulse Output Operation with Software Trigger Set TMC0n to 04H (TM0n count starts) Count clock TM0n count 0000H 0001H N + 1 0000H N – 1 M – 1 M + 1 M + 2 CR01n set value CR00n set value...
Page 215 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 TO 03 Figure 7-51. Control Register Settings for One-Shot Pulse Output with External Trigger (with Rising Edge Specified) (a) 16-bit timer mode control register 0n (TMC0n) TMC0n3 TMC0n2 TMC0n1 OVF0n TMC0n Clears and starts at valid edge of TI00n pin.
Page 216 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 TO 03 Figure 7-52. Timing of One-Shot Pulse Output Operation with External Trigger (with Rising Edge Specified) When TMC0n is set to 08H (TM0n count starts) Count clock TM0n count value 0000H 0001H 0000H N + 1 N + 2 M –...
Page 217: Special Use Of Tm0N
7.5 Special Use of TM0n 7.5.1 Rewriting CR01n during TM0n operation In principle, rewriting CR00n and CR01n of the 78K0/FF2 when they are used as compare registers is prohibited while TM0n is operating (TMC0n3 and TMC0n2 = other than 00).
Page 218 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 TO 03 (2) Setting LVS0n and LVR0n Set LVS0n and LVR0n using the following procedure. Figure 7-53. Example of Flow for Setting LVS0n and LVR0n Bits Setting TOC0n.OSPE0n, TOC0n4, TOC0n1 bits <1> Setting of timer output operation Setting TOC0n.TOE0n Setting...
Page 219: Cautions For 16-Bit Timer/Event Counters 00 To 03
CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 TO 03 7.6 Cautions for 16-Bit Timer/Event Counters 00 to 03 (1) Restrictions for each channel of 16-bit timer/event counter 0n Table 7-5 shows the restrictions for each channel. Table 7-5. Restrictions for Each Channel of 16-Bit Timer/Event Counter 0n Operation Restriction −...
Page 220 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 TO 03 (4) Timing of holding data by capture register (a) When the valid edge is input to the TI00n/TI01n pin and the reverse phase of the TI00n pin is detected while CR00n/CR01n is read, CR01n performs a capture operation but the read value of CR00n/CR01n is not guaranteed.
Page 221 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 TO 03 (7) Operation of OVF0n flag (a) Setting OVF0n flag (1) The OVF0n flag is set to 1 in the following case, as well as when TM0n overflows. Select the clear & start mode entered upon a match between TM0n and CR00n. ↓...
Page 222 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 TO 03 (9) Capture operation (a) When valid edge of TI00n is specified as count clock When the valid edge of TI00n is specified as the count clock, the capture register for which TI00n is specified as a trigger does not operate correctly.
Page 223: Chapter 8 8-Bit Timer/Event Counters 50 And 51
CHAPTER 8 8-BIT TIMER/EVENT COUNTERS 50 AND 51 8.1 Functions of 8-Bit Timer/Event Counters 50 and 51 8-bit timer/event counters 50 and 51 have the following functions. • Interval timer • External event counter • Square-wave output • PWM output Figures 8-1 and 8-2 show the block diagrams of 8-bit timer/event counters 50 and 51.
Page 224 CHAPTER 8 8-BIT TIMER/EVENT COUNTERS 50 AND 51 Figure 8-2. Block Diagram of 8-Bit Timer/Event Counter 51 Internal bus 8-bit timer compare Selector INTTM51 register 51 (CR51) TI51/TO51/P33/INTP4 Note 1 Match 8-bit timer TO51/TI51/ counter 51 (TM51) P33/INTP4 Clear Note 2 Output latch PM33 (P33)
Page 225: Configuration Of 8-Bit Timer/Event Counters 50 And 51
CHAPTER 8 8-BIT TIMER/EVENT COUNTERS 50 AND 51 8.2 Configuration of 8-Bit Timer/Event Counters 50 and 51 8-bit timer/event counters 50 and 51 include the following hardware. Table 8-1. Configuration of 8-Bit Timer/Event Counters 50 and 51 Item Configuration Timer register 8-bit timer counter 5n (TM5n) Register 8-bit timer compare register 5n (CR5n)
Page 226 CHAPTER 8 8-BIT TIMER/EVENT COUNTERS 50 AND 51 (2) 8-bit timer compare register 5n (CR5n) CR5n can be read and written by an 8-bit memory manipulation instruction. Except in PWM mode, the value set in CR5n is constantly compared with the 8-bit timer counter 5n (TM5n) count value, and an interrupt request (INTTM5n) is generated if they match.
Page 227: Registers Controlling 8-Bit Timer/Event Counters 50 And 51
CHAPTER 8 8-BIT TIMER/EVENT COUNTERS 50 AND 51 8.3 Registers Controlling 8-Bit Timer/Event Counters 50 and 51 The following four registers are used to control 8-bit timer/event counters 50 and 51. • Timer clock selection register 5n (TCL5n) • 8-bit timer mode control register 5n (TMC5n) •...
Page 228 CHAPTER 8 8-BIT TIMER/EVENT COUNTERS 50 AND 51 Figure 8-6. Format of Timer Clock Selection Register 51 (TCL51) Address: FF8CH After reset: 00H Symbol TCL51 TCL512 TCL511 TCL510 TCL512 TCL511 TCL510 Count clock selection = 10 = 20 TI51 pin falling edge TI51 pin rising edge 4 MHz 8 MHz...
Page 229 CHAPTER 8 8-BIT TIMER/EVENT COUNTERS 50 AND 51 (2) 8-bit timer mode control register 5n (TMC5n) TMC5n is a register that performs the following five types of settings. <1> 8-bit timer counter 5n (TM5n) count operation control <2> 8-bit timer counter 5n (TM5n) operating mode selection <3>...
Page 230 CHAPTER 8 8-BIT TIMER/EVENT COUNTERS 50 AND 51 Figure 8-8. Format of 8-Bit Timer Mode Control Register 51 (TMC51) Note Address: FF43H After reset: 00H Symbol <7> <3> <2> <0> TMC51 TCE51 TMC516 LVS51 LVR51 TMC511 TOE51 TCE51 TM51 count operation control After clearing to 0, count operation disabled (counter stopped) Count operation start TMC516...
Page 231 CHAPTER 8 8-BIT TIMER/EVENT COUNTERS 50 AND 51 (3) Port mode registers 1 and 3 (PM1, PM3) These registers set port 1 and 3 input/output in 1-bit units. When using the P17/TO50/TI50 and P33/TO51/TI51/INTP4 pins for timer output, clear PM17 and PM33 and the output latches of P17 and P33 to 0.
Page 232: Operations Of 8-Bit Timer/Event Counters 50 And 51
CHAPTER 8 8-BIT TIMER/EVENT COUNTERS 50 AND 51 8.4 Operations of 8-Bit Timer/Event Counters 50 and 51 8.4.1 Operation as interval timer 8-bit timer/event counter 5n operates as an interval timer that generates interrupt requests repeatedly at intervals of the count value preset to 8-bit timer compare register 5n (CR5n). When the count value of 8-bit timer counter 5n (TM5n) matches the value set to CR5n, counting continues with the TM5n value cleared to 0 and an interrupt request signal (INTTM5n) is generated.
Page 233 CHAPTER 8 8-BIT TIMER/EVENT COUNTERS 50 AND 51 Figure 8-11. Interval Timer Operation Timing (2/2) (b) When CR5n = 00H Count clock TM5n CR5n TCE5n INTTM5n Interval time (c) When CR5n = FFH Count clock TM5n CR5n TCE5n INTTM5n Interrupt acknowledged Interrupt acknowledged Interval time...
Page 234: Operation As External Event Counter
CHAPTER 8 8-BIT TIMER/EVENT COUNTERS 50 AND 51 8.4.2 Operation as external event counter The external event counter counts the number of external clock pulses to be input to the TI5n pin by 8-bit timer counter 5n (TM5n). TM5n is incremented each time the valid edge specified by timer clock selection register 5n (TCL5n) is input. Either the rising or falling edge can be selected.
Page 235: Square-Wave Output Operation
CHAPTER 8 8-BIT TIMER/EVENT COUNTERS 50 AND 51 8.4.3 Square-wave output operation A square wave with any selected frequency is output at intervals determined by the value preset to 8-bit timer compare register 5n (CR5n). The TO5n pin output status is inverted at intervals determined by the count value preset to CR5n by setting bit 0 (TOE5n) of 8-bit timer mode control register 5n (TMC5n) to 1.
Page 236: Pwm Output Operation
CHAPTER 8 8-BIT TIMER/EVENT COUNTERS 50 AND 51 Figure 8-13. Square-Wave Output Operation Timing Count clock N − 1 N − 1 TM5n count value Count start CR5n Note TO5n Note The initial value of TO5n output can be set by bits 2 and 3 (LVR5n, LVS5n) of 8-bit timer mode control register 5n (TMC5n).
Page 237 CHAPTER 8 8-BIT TIMER/EVENT COUNTERS 50 AND 51 (1) PWM output basic operation Setting <1> Set each register. • Clear the port output latch (P17 or P33) Note Note and port mode register (PM17 or PM33) to 0. • TCL5n: Select the count clock. •...
Page 238 CHAPTER 8 8-BIT TIMER/EVENT COUNTERS 50 AND 51 Figure 8-14. PWM Output Operation Timing (a) Basic operation (active level = H) Count clock TM5n 00H 01H FFH 00H 01H 02H N N + 1 FFH 00H 01H 02H CR5n TCE5n INTTM5n TO5n <5>...
Page 239 CHAPTER 8 8-BIT TIMER/EVENT COUNTERS 50 AND 51 (2) Operation with CR5n changed Figure 8-15. Timing of Operation with CR5n Changed (a) CR5n value is changed from N to M before clock rising edge of FFH → Value is transferred to CR5n at overflow immediately after change. Count clock TM5n N N + 1 N + 2...
Page 240: Cautions For 8-Bit Timer/Event Counters 50 And 51
CHAPTER 8 8-BIT TIMER/EVENT COUNTERS 50 AND 51 8.5 Cautions for 8-Bit Timer/Event Counters 50 and 51 (1) Timer start error An error of up to one clock may occur in the time required for a match signal to be generated after timer start. This is because 8-bit timer counters 50 and 51 (TM50, TM51) are started asynchronously to the count clock.
Page 241: Chapter 9 8-Bit Timers H0 And H1
CHAPTER 9 8-BIT TIMERS H0 AND H1 9.1 Functions of 8-Bit Timers H0 and H1 8-bit timers H0 and H1 have the following functions. • Interval timer • PWM output mode • Square-wave output • Carrier generator mode (8-bit timer H1 only) 9.2 Configuration of 8-Bit Timers H0 and H1 8-bit timers H0 and H1 include the following hardware.
Page 242 Figure 9-1. Block Diagram of 8-Bit Timer H0 Internal bus 8-bit timer H mode register 0 (TMHMD0) TMHE0 CKS02 CKS01 CKS00 TMMD01 TMMD00 TOLEV0 TOEN0 8-bit timer H 8-bit timer H compare register compare register 10 (CMP10) 00 (CMP00) Decoder TOH0/P15 Selector Output latch...
Page 243 Figure 9-2. Block Diagram of 8-Bit Timer H1 Internal bus 8-bit timer H mode 8-bit timer H carrier register 1 (TMHMD1) control register 1 (TMCYC1) TMHE1 CKS12 CKS11 CKS10 TMMD11 TMMD10 TOLEV1 TOEN1 8-bit timer H 8-bit timer H RMC1 NRZB1 NRZ1 compare compare register 1 1...
Page 244 CHAPTER 9 8-BIT TIMERS H0 AND H1 (1) 8-bit timer H compare register 0n (CMP0n) This register can be read or written by an 8-bit memory manipulation instruction. This register is used in all of the timer operation modes. This register constantly compares the value set to CMP0n with the count value of the 8-bit timer counter Hn and, when the two values match, generates an interrupt request signal (INTTMHn) and inverts the output level of TOHn.
Page 245: Registers Controlling 8-Bit Timers H0 And H1
CHAPTER 9 8-BIT TIMERS H0 AND H1 9.3 Registers Controlling 8-Bit Timers H0 and H1 The following four registers are used to control 8-bit timers H0 and H1. • 8-bit timer H mode register n (TMHMDn) • 8-bit timer H carrier control register 1 (TMCYC1) Note •...
Page 246 CHAPTER 9 8-BIT TIMERS H0 AND H1 Figure 9-5. Format of 8-Bit Timer H Mode Register 0 (TMHMD0) Address: FF69H After reset: 00H Symbol <7> <1> <0> TMHMD0 TMHE0 CKS02 CKS01 CKS00 TMMD01 TMMD00 TOLEV0 TOEN0 TMHE0 Timer operation enable Stops timer count operation (Counter is cleared to 0) Enables timer count operation (Count operation started by inputting clock) CKS02...
Page 247 CHAPTER 9 8-BIT TIMERS H0 AND H1 Cautions 1. When TMHE0 = 1, setting the other bits of TMHMD0 is prohibited. However, TMHMD0 can be refreshed (the same value is written). 2. In the PWM output mode, be sure to set 8-bit timer H compare register 10 (CMP10) when starting the timer count operation (TMHE0 = 1) after the timer count operation was stopped (TMHE0 = 0) (be sure to set again even if setting the same value to CMP10).
Page 248 CHAPTER 9 8-BIT TIMERS H0 AND H1 Cautions 1. When TMHE1 = 1, setting the other bits of TMHMD1 is prohibited. However, TMHMD1 can be refreshed (the same value is written). 2. In the PWM output mode and carrier generator mode, be sure to set 8-bit timer H compare register 11 (CMP11) when starting the timer count operation (TMHE1 = 1) after the timer count operation was stopped (TMHE1 = 0) (be sure to set again even if setting the same value to CMP11).
Page 249 CHAPTER 9 8-BIT TIMERS H0 AND H1 (3) Port mode register 1 (PM1) This register sets port 1 input/output in 1-bit units. When using the P15/TOH0 and P16/TOH1/INTP5 pins for timer output, clear PM15 and PM16 and the output latches of P15 and P16 to 0. PM1 can be set by a 1-bit or 8-bit memory manipulation instruction.
Page 250: Operation Of 8-Bit Timers H0 And H1
CHAPTER 9 8-BIT TIMERS H0 AND H1 9.4 Operation of 8-Bit Timers H0 and H1 9.4.1 Operation as interval timer/square-wave output When 8-bit timer counter Hn and compare register 0n (CMP0n) match, an interrupt request signal (INTTMHn) is generated and 8-bit timer counter Hn is cleared to 00H. Compare register 1n (CMP1n) is not used in interval timer mode.
Page 251 CHAPTER 9 8-BIT TIMERS H0 AND H1 (2) Timing chart The timing of the interval timer/square-wave output operation is shown below. Figure 9-10. Timing of Interval Timer/Square-Wave Output Operation (1/2) (a) Basic operation Count clock Count start 01H 00H 8-bit timer counter Hn Clear Clear CMP0n...
Page 252 CHAPTER 9 8-BIT TIMERS H0 AND H1 Figure 9-10. Timing of Interval Timer/Square-Wave Output Operation (2/2) (b) Operation when CMP0n = FFH Count clock Count start 8-bit timer counter Hn Clear Clear CMP0n TMHEn INTTMHn TOHn Interval time (c) Operation when CMP0n = 00H Count clock Count start 8-bit timer counter Hn...
Page 253: Operation As Pwm Output Mode
CHAPTER 9 8-BIT TIMERS H0 AND H1 9.4.2 Operation as PWM output mode In PWM output mode, a pulse with an arbitrary duty and arbitrary cycle can be output. 8-bit timer compare register 0n (CMP0n) controls the cycle of timer output (TOHn). Rewriting the CMP0n register during timer operation is prohibited.
Page 254 CHAPTER 9 8-BIT TIMERS H0 AND H1 <2> The count operation starts when TMHEn = 1. <3> The CMP0n register is the compare register that is to be compared first after counter operation is enabled. When the values of 8-bit timer counter Hn and the CMP0n register match, 8-bit timer counter Hn is cleared, an interrupt request signal (INTTMHn) is generated, and TOHn output becomes active.
Page 255 CHAPTER 9 8-BIT TIMERS H0 AND H1 (2) Timing chart The operation timing in PWM output mode is shown below. Caution Make sure that the CMP1n register setting value (M) and CMP0n register setting value (N) are within the following range. 00H ≤...
Page 256 CHAPTER 9 8-BIT TIMERS H0 AND H1 Figure 9-12. Operation Timing in PWM Output Mode (2/4) (b) Operation when CMP0n = FFH, CMP1n = 00H Count clock 8-bit timer counter Hn 00H 01H FFH 00H 01H 02H FFH 00H 01H 02H FFH 00H CMP0n CMP1n...
Page 257 CHAPTER 9 8-BIT TIMERS H0 AND H1 Figure 9-12. Operation Timing in PWM Output Mode (3/4) (d) Operation when CMP0n = 01H, CMP1n = 00H Count clock 01H 00H 01H 00H 00H 01H 00H 01H 8-bit timer counter Hn CMP0n CMP1n TMHEn INTTMHn...
Page 258 CHAPTER 9 8-BIT TIMERS H0 AND H1 Figure 9-12. Operation Timing in PWM Output Mode (4/4) (e) Operation by changing CMP1n (CMP1n = 01H → 03H, CMP0n = A5H) Count clock 8-bit timer counter Hn 00H 01H 02H A5H 00H 01H 02H 03H A5H 00H 01H 02H 03H A5H 00H CMP0n...
Page 259: Carrier Generator Mode Operation (8-Bit Timer H1 Only)
CHAPTER 9 8-BIT TIMERS H0 AND H1 9.4.3 Carrier generator mode operation (8-bit timer H1 only) The carrier clock generated by 8-bit timer H1 is output in the cycle set by 8-bit timer/event counter 51. In carrier generator mode, the output of the 8-bit timer H1 carrier pulse is controlled by 8-bit timer/event counter 51, and the carrier pulse is output from the TOH1 output.
Page 260 CHAPTER 9 8-BIT TIMERS H0 AND H1 To control the carrier pulse output during a count operation, the NRZ1 and NRZB1 bits of the TMCYC1 register have a master and slave bit configuration. The NRZ1 bit is read-only but the NRZB1 bit can be read and written. The INTTM51 signal is synchronized with the 8-bit timer H1 count clock and output as the INTTM5H1 signal.
Page 261 CHAPTER 9 8-BIT TIMERS H0 AND H1 (3) Usage Outputs an arbitrary carrier clock from the TOH1 pin. <1> Set each register. Figure 9-14. Register Setting in Carrier Generator Mode Setting 8-bit timer H mode register 1 (TMHMD1) TMHE1 CKS12 CKS11 CKS10 TMMD11...
Page 262 CHAPTER 9 8-BIT TIMERS H0 AND H1 If the setting value of the CMP01 register is N, the setting value of the CMP11 register is M, and the count clock frequency is f , the carrier clock output cycle and duty are as follows. Carrier clock output cycle = (N + M + 2)/f Duty = High-level width : Carrier clock output width = ( M + 1) : (N + M + 2) Cautions 1.
Page 263 CHAPTER 9 8-BIT TIMERS H0 AND H1 Figure 9-15. Carrier Generator Mode Operation Timing (1/3) (a) Operation when CMP01 = N, CMP11 = N 8-bit timer Hn count clock 8-bit timer counter N 00H N 00H N 00H N 00H N 00H Hn count value CMPn0...
Page 264 CHAPTER 9 8-BIT TIMERS H0 AND H1 Figure 9-15. Carrier Generator Mode Operation Timing (2/3) (b) Operation when CMP01 = N, CMP11 = M 8-bit timer Hn count clock 8-bit timer counter N 00H 01H M 00H N 00H 01H M 00H Hn count value CMPn0...
Page 265 CHAPTER 9 8-BIT TIMERS H0 AND H1 Figure 9-15. Carrier Generator Mode Operation Timing (3/3) (c) Operation when CMP11 is changed 8-bit timer H1 count clock 8-bit timer counter 00H 01H 00H 01H H1 count value CMP01 <3> <3>’ CMP11 M (L) TMHE1 INTTMH1...
Page 266: Chapter 10 Watch Timer
CHAPTER 10 WATCH TIMER 10.1 Functions of Watch Timer The watch timer has the following functions. • Watch timer • Interval timer The watch timer and the interval timer can be used simultaneously. Figure 10-1 shows the watch timer block diagram. Figure 10-1.
Page 267: Configuration Of Watch Timer
CHAPTER 10 WATCH TIMER (1) Watch timer When the high-speed system clock or subsystem clock is used, interrupt requests (INTWT) are generated at preset intervals. Table 10-1. Watch Timer Interrupt Time Interrupt Time When Operated at When Operated at When Operated at When Operated at When Operated at = 32.768 kHz...
Page 268: Register Controlling Watch Timer
CHAPTER 10 WATCH TIMER 10.3 Register Controlling Watch Timer The watch timer is controlled by the watch timer operation mode register (WTM). • Watch timer operation mode register (WTM) This register sets the watch timer count clock, enables/disables operation, prescaler interval time, and 5-bit counter operation control.
Page 269 CHAPTER 10 WATCH TIMER Caution Do not change the count clock and interval time (by setting bits 4 to 7 (WTM4 to WTM7) of WTM) during watch timer operation. Remarks 1. f Watch timer clock frequency (f or f 2. f : Peripheral hardware clock frequency 3.
Page 270: Watch Timer Operations
CHAPTER 10 WATCH TIMER 10.4 Watch Timer Operations 10.4.1 Watch timer operation The watch timer generates an interrupt request (INTWT) at a specific time interval by using the peripheral hardware clock or subsystem clock. When bit 0 (WTM0) and bit 1 (WTM1) of the watch timer operation mode register (WTM) are set to 1, the count operation starts.
Page 271: Interval Timer Operation
CHAPTER 10 WATCH TIMER 10.4.2 Interval timer operation The watch timer operates as interval timer which generates interrupt requests (INTWTI) repeatedly at an interval of the preset count value. The interval time can be selected with bits 4 to 6 (WTM4 to WTM6) of the watch timer operation mode register (WTM).
Page 272: Cautions For Watch Timer
CHAPTER 10 WATCH TIMER 10.5 Cautions for Watch Timer When operation of the watch timer and 5-bit counter is enabled by the watch timer mode control register (WTM) (by setting bits 0 (WTM0) and 1 (WTM1) of WTM to 1), the interval until the first interrupt request (INTWT) is generated after the register is set does not exactly match the specification made with bits 2 and 3 (WTM2, WTM3) of WTM.
Page 273: Chapter 11 Watchdog Timer
CHAPTER 11 WATCHDOG TIMER 11.1 Functions of Watchdog Timer The watchdog timer operates on the internal low-speed oscillation clock. The watchdog timer is used to detect an inadvertent program loop. If a program loop is detected, an internal reset signal is generated. Program loop is detected in the following cases.
Page 274: Configuration Of Watchdog Timer
CHAPTER 11 WATCHDOG TIMER 11.2 Configuration of Watchdog Timer The watchdog timer includes the following hardware. Table 11-1. Configuration of Watchdog Timer Item Configuration Control register Watchdog timer enable register (WDTE) How the counter operation is controlled, overflow time, and window open period are set by the option byte. Table 11-2.
Page 275: Register Controlling Watchdog Timer
CHAPTER 11 WATCHDOG TIMER 11.3 Register Controlling Watchdog Timer The watchdog timer is controlled by the watchdog timer enable register (WDTE). (1) Watchdog timer enable register (WDTE) Writing ACH to WDTE clears the watchdog timer counter and starts counting again. This register can be set by an 8-bit memory manipulation instruction.
Page 276: Operation Of Watchdog Timer
CHAPTER 11 WATCHDOG TIMER 11.4 Operation of Watchdog Timer 11.4.1 Controlling operation of watchdog timer 1. When the watchdog timer is used, its operation is specified by the option byte (0080H). • Enable counting operation of the watchdog timer by setting bit 4 (WDTON) of the option byte (0080H) to 1 (the counter starts operating after a reset release) (for details, see CHAPTER 23).
Page 277 CHAPTER 11 WATCHDOG TIMER Cautions 4. The operation of the watchdog timer in the HALT and STOP modes differs as follows depending on the set value of bit 0 (LSROSC) of the option byte. LSROSC = 0 (Internal Low-Speed LSROSC = 1 (Internal Low-Speed Oscillator Can Be Stopped by Software) Oscillator Cannot Be Stopped) In HALT mode...
Page 278: Setting Overflow Time Of Watchdog Timer
CHAPTER 11 WATCHDOG TIMER 11.4.2 Setting overflow time of watchdog timer Set the overflow time of the watchdog timer by using bits 3 to 1 (WDCS2 to WDCS0) of the option byte (0080H). If an overflow occurs, an internal reset signal is generated. If “ACH” is written to WDTE during the window open period before the overflow time, the present count is cleared and the watchdog timer starts counting again.
Page 279: Setting Window Open Period Of Watchdog Timer
CHAPTER 11 WATCHDOG TIMER 11.4.3 Setting window open period of watchdog timer Set the window open period of the watchdog timer by using bits 6 and 5 (WINDOW1, WINDOW0) of the option byte (0080H). The outline of the window is as follows. •...
Page 280 CHAPTER 11 WATCHDOG TIMER Remark If the overflow time is set to 2 , the window close time and open time are as follows. Setting of Window Open Period 100% Window close time 0 to 3.56 ms 0 to 2.37 ms 0 to 0.119 ms None Window open time...
Page 281: Chapter 12 Clock Output/Buzzer Output Controller
CHAPTER 12 CLOCK OUTPUT/BUZZER OUTPUT CONTROLLER 12.1 Functions of Clock Output/Buzzer Output Controller The clock output controller is intended for carrier output during remote controlled transmission and clock output for supply to peripheral LSIs. The clock selected with the clock output selection register (CKS) is output. In addition, the buzzer output is intended for square-wave output of buzzer frequency selected with CKS.
Page 282: Configuration Of Clock Output/Buzzer Output Controller
CHAPTER 12 CLOCK OUTPUT/BUZZER OUTPUT CONTROLLER 12.2 Configuration of Clock Output/Buzzer Output Controller The clock output/buzzer output controller includes the following hardware. Table 12-1. Clock Output/Buzzer Output Controller Configuration Item Configuration Control registers Clock output selection register (CKS) Port mode register 7 (PM7) Port register 7 (P7) 12.3 Register Controlling Clock Output/Buzzer Output Controller The following two registers are used to control the clock output/buzzer output controller.
Page 283 CHAPTER 12 CLOCK OUTPUT/BUZZER OUTPUT CONTROLLER Figure 12-2. Format of Clock Output Selection Register (CKS) Address: FF40H After reset: 00H Symbol <7> <4> BZOE BCS1 BCS0 CLOE CCS3 CCS2 CCS1 CCS0 BZOE BUZ output enable/disable specification Clock division circuit operation stopped. BUZ fixed to low level. Clock division circuit operation enabled.
Page 284 CHAPTER 12 CLOCK OUTPUT/BUZZER OUTPUT CONTROLLER (2) Port mode register 7 (PM7) This register sets port 7 input/output in 1-bit units. When using the P72/INTP6/PCL pin for clock output and the P73/INTP7/BUZ pin for buzzer output, set PM72, PM73 and the output latch of P72, P73 to 0. PM7 is set by a 1-bit or 8-bit memory manipulation instruction.
Page 285: Clock Output/Buzzer Output Controller Operations
CHAPTER 12 CLOCK OUTPUT/BUZZER OUTPUT CONTROLLER 12.4 Clock Output/Buzzer Output Controller Operations 12.4.1 Clock output operation The clock pulse is output as the following procedure. <1> Select the clock pulse output frequency with bits 0 to 3 (CCS0 to CCS3) of the clock output selection register (CKS) (clock pulse output in disabled status).
Page 286: Chapter 13 A/D Converter
CHAPTER 13 A/D CONVERTER 13.1 Function of A/D Converter The A/D converter converts an analog input signal into a digital value, and consists of up to sixteen channels (ANI0 to ANI15) with a resolution of 10 bits. The A/D converter has the following function. •...
Page 287: Configuration Of A/D Converter
CHAPTER 13 A/D CONVERTER 13.2 Configuration of A/D Converter The A/D converter includes the following hardware. (1) ANI0 to ANI15 pins These are the analog input pins of the 16-channel A/D converter. They input analog signals to be converted into digital signals.
Page 288 CHAPTER 13 A/D CONVERTER (7) 8-bit A/D conversion result register (ADCRH) The A/D conversion result is loaded from the successive approximation register to this register each time A/D conversion is completed, and the ADCRH register stores the higher 8 bits of the A/D conversion result. Caution When data is read from ADCR and ADCRH, a wait cycle is generated.
Page 289: Registers Used In A/D Converter
CHAPTER 13 A/D CONVERTER 13.3 Registers Used in A/D Converter The A/D converter uses the following seven registers. • A/D converter mode register (ADM) • A/D port configuration register (ADPC) • Analog input channel specification register (ADS) • Port mode register 8 (PM8) •...
Page 290 CHAPTER 13 A/D CONVERTER Table 13-1. Settings of ADCS and ADCE ADCS ADCE A/D Conversion Operation Stop status (DC power consumption path does not exist) Conversion waiting mode (comparator: 1/2AV operation, only comparator consumes power) Note Conversion mode (comparator operation stopped Conversion mode (comparator: 1/2AV operation) Note Ignore data of the first conversion because it is not guaranteed range.
Page 291 CHAPTER 13 A/D CONVERTER Table 13-2. A/D Conversion Time Selection (1) 2.7 V ≤ AV ≤ 5.5 V A/D Converter Mode Register (ADM) Conversion Time Selection Conversion Clock = 4 MHz = 10 MHz = 20 MHz μ μ 264/f 26.4 13.2 Setting prohibited...
Page 292 CHAPTER 13 A/D CONVERTER Figure 13-5. A/D Converter Sampling and A/D Conversion Timing ← ADCS 1 or ADS rewrite ADCS Sampling timing INTAD Wait Sampling time Successive Sampling time Transfer Note period clear conversion time to ADCR, clear INTAD generation Conversion time Conversion time Note For details of wait period, see CHAPTER 31 CAUTIONS FOR WAIT.
Page 293 CHAPTER 13 A/D CONVERTER (3) 8-bit A/D conversion result register (ADCRH) This register is an 8-bit register that stores the A/D conversion result. The higher 8 bits of 10-bit resolution are stored. ADCRH can be read by an 8-bit memory manipulation instruction. Reset signal generation clears this register to 00H.
Page 294 CHAPTER 13 A/D CONVERTER (4) Analog input channel specification register (ADS) This register specifies the input port of the analog voltage to be A/D converted. ADS can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears this register to 00H. Figure 13-8.
Page 295 CHAPTER 13 A/D CONVERTER (5) A/D port configuration register (ADPC) This register switches the P80/ANI0 to P87/ANI7, P90/ANI8 to P97/ANI15 pins to analog input of A/D converter or digital I/O of port. ADPC can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears this register to 00H.
Page 296 CHAPTER 13 A/D CONVERTER (6) Port mode register 8 (PM8) When using the P80/ANI0 to P87/ANI7 pins for analog input port, set PM80 to PM87 to 1. The output latches of P80 to P87 at this time may be 0 or 1. If PM80 to PM87 are set to 0, they cannot be used as analog input port pins.
Page 297: A/D Converter Operations
CHAPTER 13 A/D CONVERTER 13.4 A/D Converter Operations 13.4.1 Basic operations of A/D converter <1> Set bit 0 (ADCE) of the A/D converter mode register (ADM) to 1 to start the operation of the comparator. <2> Set channels for A/D conversion to analog input by using the A/D port configuration register (ADPC) and set to input mode by using port mode register 8, 9 (PM8, PM9).
Page 298 CHAPTER 13 A/D CONVERTER Figure 13-12. Basic Operation of A/D Converter Conversion time Sampling time A/D converter Sampling A/D conversion operation Conversion Undefined result Conversion ADCR result INTAD A/D conversion operations are performed continuously until bit 7 (ADCS) of the A/D converter mode register (ADM) is reset (0) by software.
Page 299: Input Voltage And Conversion Results
CHAPTER 13 A/D CONVERTER 13.4.2 Input voltage and conversion results The relationship between the analog input voltage input to the analog input pins (ANI0 to ANI15) and the theoretical A/D conversion result (stored in the 10-bit A/D conversion result register (ADCR)) is shown by the following expression.
Page 300: A/D Converter Operation Mode
CHAPTER 13 A/D CONVERTER 13.4.3 A/D converter operation mode The operation mode of the A/D converter is the select mode. One channel of analog input is selected from ANI0 to ANI15 by the analog input channel specification register (ADS) and A/D conversion is executed. (1) A/D conversion operation By setting bit 7 (ADCS) of the A/D converter mode register (ADM) to 1, the A/D conversion operation of the voltage, which is applied to the analog input pin specified by the analog input channel specification register...
Page 301 CHAPTER 13 A/D CONVERTER The setting methods are described below. <1> Set bit 0 (ADCE) of the A/D converter mode register (ADM) to 1. <2> Set the channel to be used in the analog input mode by using bits 4 to 0 (ADPC4 to ADPC0) of the A/D port configuration register (ADPC) and bits 7 to 0 (PM87 to PM80) of port mode register 8 (PM8), bits 7 to 0 (PM97 to PM90) of port mode register 9 (PM9).
Page 302: How To Read A/D Converter Characteristics Table
CHAPTER 13 A/D CONVERTER 13.5 How to Read A/D Converter Characteristics Table Here, special terms unique to the A/D converter are explained. (1) Resolution This is the minimum analog input voltage that can be identified. That is, the percentage of the analog input voltage per bit of digital output is called 1LSB (Least Significant Bit).
Page 303 CHAPTER 13 A/D CONVERTER (5) Full-scale error This shows the difference between the actual measurement value of the analog input voltage and the theoretical value (Full-scale − 3/2LSB) when the digital output changes from 1..110 to 1..111. (6) Integral linearity error This shows the degree to which the conversion characteristics deviate from the ideal linear relationship.
Page 304: Cautions For A/D Converter
CHAPTER 13 A/D CONVERTER 13.6 Cautions for A/D Converter (1) Operating current in STOP mode The A/D converter stops operating in the STOP mode. At this time, the operating current can be reduced by clearing bit 7 (ADCS) and bit 0 (ADCE) of the A/D converter mode register (ADM) to 0. To restart from the standby status, clear bit 6 (ADIF) of interrupt request flag register 1L (IF1L) to 0 and start operation.
Page 305 CHAPTER 13 A/D CONVERTER Figure 13-21. Analog Input Pin Connection If there is a possibility that noise equal to or higher than AV equal to or lower than AV may enter, clamp with a diode with a small V value (0.3 V or lower). Reference voltage input...
Page 306 CHAPTER 13 A/D CONVERTER (8) Interrupt request flag (ADIF) The interrupt request flag (ADIF) is not cleared even if the analog input channel specification register (ADS) is changed. Therefore, if an analog input pin is changed during A/D conversion, the A/D conversion result and ADIF for the pre-change analog input may be set just before the ADS rewrite.
Page 307 CHAPTER 13 A/D CONVERTER (11) Internal equivalent circuit The equivalent circuit of the analog input block is shown below. Figure 13-23. Internal Equivalent Circuit of ANIn Pin ANIn Table 13-4. Resistance and Capacitance Values of Equivalent Circuit (Reference Values) 4.0 V ≤ AV ≤...
Page 308: Chapter 14 Serial Interfaces Uart60 And Uart61
CHAPTER 14 SERIAL INTERFACES UART60 AND UART61 The 78K0/FF2 incorporate serial interfaces UART60 and UART61. 14.1 Functions of Serial Interfaces UART60 and UART61 Serial interfaces UART60 and UART61 have the following two modes. (1) Operation stop mode This mode is used when serial communication is not executed and can enable a reduction in the power consumption.
Page 309 CHAPTER 14 SERIAL INTERFACES UART60 AND UART61 Cautions 6. If data is continuously transmitted, the communication timing from the stop bit to the next start bit is extended two operating clocks of the macro. However, this does not affect the result of communication because the reception side initializes the timing when it has detected a start bit.
Page 310 CHAPTER 14 SERIAL INTERFACES UART60 AND UART61 Figure 14-2. LIN Reception Operation Wakeup Sync Sync Identifer Data field Data field Checksum signal frame break field field field field LIN bus 13-bit Data Data Data SBF reception reception reception reception reception reception <2>...
Page 311 CHAPTER 14 SERIAL INTERFACES UART60 AND UART61 Figure 14-3 and 14-4 show the port configuration for LIN reception operation. The wakeup signal transmitted from the LIN master is received by detecting the edge of the external interrupt (INTP0 and INTP1). The length of the sync field transmitted from the LIN master can be measured using the external event capture operation of 16-bit timer/event counter 00, 01, and the baud rate error can be calculated.
Page 312 CHAPTER 14 SERIAL INTERFACES UART60 AND UART61 Figure 14-4. Port Configuration for LIN Reception Operation (UART61) Selector P11/RxD61 RxD61 input Port mode (PM11) Output latch (P11) Selector Selector P05/TI001 TI001 input Port mode Port input (PM05) switch control (ISC2) Output latch (P05) <ISC2>...
Page 313: Configurations Of Serial Interface Uart60 And Uart61
CHAPTER 14 SERIAL INTERFACES UART60 AND UART61 14.2 Configurations of Serial Interface UART60 and UART61 Serial interfaces UART60 and UART61 include the following hardware. Table 14-1. Configurations of Serial Interface UART60 and UART61 Item Configuration Registers Receive buffer register 6n (RXB6n) Receive shift register 6n (RXS6n) Transmit buffer register 6n (TXB6n) Transmit shift register 6n (TXS6n)
Page 314 Figure 14-5. Block Diagram of Serial Interface UART60 TI010, INTP0 Filter D60/P14 INTSR60 Reception control INTSRE60 Receive shift register 60 (RXS60) Asynchronous serial Asynchronous serial Baud rate Asynchronous serial interface Receive buffer register 60 interface operation mode interface reception error generator control register 60 (ASICL60) (RXB60)
Page 315 Figure 14-6. Block Diagram of Serial Interface UART61 Filter D61/P11/SI10 INTSR61 Reception control INTSRE61 Receive shift register 61 (RXS61) Asynchronous serial Asynchronous serial Asynchronous serial interface Baud rate Receive buffer register 61 interface operation mode interface reception error control register 61 (ASICL61) generator (RXB61) register 61 (ASIM61)
Page 316 CHAPTER 14 SERIAL INTERFACES UART60 AND UART61 (1) Receive buffer register 6n (RXB6n) This 8-bit register stores parallel data converted by receive shift register 6n (RXS6n). Each time 1 byte of data has been received, new receive data is transferred to this register from RXS6n. If the data length is set to 7 bits, data is transferred as follows.
Page 317: Registers Controlling Serial Interfaces Uart60 And Uart61
CHAPTER 14 SERIAL INTERFACES UART60 AND UART61 14.3 Registers Controlling Serial Interfaces UART60 and UART61 Serial interfaces UART60 and UART61 are controlled by the following nine registers. • Asynchronous serial interface operation mode register 6n (ASIM6n) • Asynchronous serial interface reception error status register 6n (ASIS6n) •...
Page 318 CHAPTER 14 SERIAL INTERFACES UART60 AND UART61 Figure 14-7. Format of Asynchronous Serial Interface Operation Mode Register 60 (ASIM60) (1/2) Address: FF2EH After reset: 01H R/W Symbol <7> <6> <5> ASIM60 POWER60 TXE60 RXE60 PS610 PS600 CL60 SL60 ISRM60 POWER60 Enables/disables operation of internal operation clock Note 1 Disables operation of the internal operation clock (fixes the clock to low level) and asynchronously...
Page 319 CHAPTER 14 SERIAL INTERFACES UART60 AND UART61 Figure 14-7. Format of Asynchronous Serial Interface Operation Mode Register 60 (ASIM60) (2/2) PS610 PS600 Transmission operation Reception operation Does not output parity bit. Reception without parity Note Outputs 0 parity. Reception as 0 parity Outputs odd parity.
Page 320 CHAPTER 14 SERIAL INTERFACES UART60 AND UART61 Figure 14-8. Format of Asynchronous Serial Interface Operation Mode Register 61 (ASIM61) (1/2) Address: FF2FH After reset: 01H R/W Symbol <7> <6> <5> ASIM61 POWER61 TXE61 RXE61 PS611 PS601 CL61 SL61 ISRM61 POWER61 Enables/disables operation of internal operation clock Note 1 Disables operation of the internal operation clock (fixes the clock to low level) and asynchronously...
Page 321 CHAPTER 14 SERIAL INTERFACES UART60 AND UART61 Figure 14-8. Format of Asynchronous Serial Interface Operation Mode Register 61 (ASIM61) (2/2) PS611 PS601 Transmission operation Reception operation Does not output parity bit. Reception without parity Note Outputs 0 parity. Reception as 0 parity Outputs odd parity.
Page 322 CHAPTER 14 SERIAL INTERFACES UART60 AND UART61 (2) Asynchronous serial interface reception error status register 6n (ASIS6n) This register indicates an error status on completion of reception by serial interfaces UART60 and UART61. It includes three error flag bits (PE6n, FE6n, OVE6n). This register is read-only by an 8-bit memory manipulation instruction.
Page 323 CHAPTER 14 SERIAL INTERFACES UART60 AND UART61 Figure 14-10. Format of Asynchronous Serial Interface Reception Error Status Register 61 (ASIS61) Address: FF2FH After reset: 00H R Symbol ASIS61 PE61 FE61 OVE61 PE61 Status flag indicating parity error If POWER61 = 0 and RXE61 = 0, or if ASIS61 register is read If the parity of transmit data does not match the parity bit on completion of reception FE61 Status flag indicating framing error...
Page 324 CHAPTER 14 SERIAL INTERFACES UART60 AND UART61 (3) Asynchronous serial interface transmission status register 6n (ASIF6n) This register indicates the status of transmission by serial interfaces UART60 and UART61. It includes two status flag bits (TXBF6n and TXSF6n). Transmission can be continued without disruption even during an interrupt period, by writing the next data to the TXB6n register after data has been transferred from the TXB6n register to the TXS6n register.
Page 325 CHAPTER 14 SERIAL INTERFACES UART60 AND UART61 Figure 14-12. Format of Asynchronous Serial Interface Transmission Status Register 61 (ASIF61) Address: FF38H After reset: 00H R Symbol ASIF61 TXBF61 TXSF61 TXBF61 Transmit buffer data flag If POWER61 = 0 or TXE61 = 0, or if data is transferred to transmit shift register 61 (TXS61) If data is written to transmit buffer register 61 (TXB61) (if data exists in TXB61) TXSF61 Transmit shift register data flag...
Page 326 CHAPTER 14 SERIAL INTERFACES UART60 AND UART61 (4) Clock selection register 6n (CKSR6n) This register selects the base clocks of serial interface UART60 and UART61. CKSR6n can be set by an 8-bit memory manipulation instruction. Reset signal generation sets this register to 00H. Remark CKSR6n can be refreshed (the same value is written) by software during a communication operation (when bits 7 and 6 (POWER6n, TXE6n) of ASIM6n = 1 or bits 7 and 5 (POWER6n, RXE6n) of ASIM6n = 1).
Page 327 CHAPTER 14 SERIAL INTERFACES UART60 AND UART61 Figure 14-14. Format of Clock Selection Register 61 (CKSR61) Address: FF39H After reset: 00H R/W Symbol CKSR61 TPS631 TPS621 TPS611 TPS601 TPS631 TPS621 TPS611 TPS601 Base clock (f ) selection XCLK6 4 MHz 5 MHz 10 MHz 20 MHz...
Page 328 CHAPTER 14 SERIAL INTERFACES UART60 AND UART61 (5) Baud rate generator control register 6n (BRGC6n) This register sets the division value of the 8-bit counters of serial interface UART60 and UART61. BRGC6n can be set by an 8-bit memory manipulation instruction. Reset signal generation sets this register to FFH.
Page 329 CHAPTER 14 SERIAL INTERFACES UART60 AND UART61 Figure 14-16. Format of Baud Rate Generator Control Register 61 (BRGC61) Address: FF3EH After reset: FFH R/W Symbol BRGC61 MDL671 MDL661 MDL651 MDL641 MDL631 MDL621 MDL611 MDL601 MDL671 MDL661 MDL651 MDL641 MDL631 MDL621 MDL611 MDL601 Output clock selection of 8-bit counter ×...
Page 330 CHAPTER 14 SERIAL INTERFACES UART60 AND UART61 (6) Asynchronous serial interface control register 6n (ASICL6n) This register controls the serial communication operations of serial interface UART60 and UART61. ASICL6n can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation sets this register to 16H.
Page 331 CHAPTER 14 SERIAL INTERFACES UART60 AND UART61 Figure 14-17. Format of Asynchronous Serial Interface Control Register 60 (ASICL60) (2/2) SBL620 SBL610 SBL600 SBF transmission output width control SBF is output with 13-bit length. SBF is output with 14-bit length. SBF is output with 15-bit length. SBF is output with 16-bit length.
Page 332 CHAPTER 14 SERIAL INTERFACES UART60 AND UART61 Figure 14-18. Format of Asynchronous Serial Interface Control Register 61 (ASICL61) (1/2) Note Address: FF3FH After reset: 16H R/W Symbol <7> <6> ASICL61 SBRF61 SBRT61 SBTT61 SBL621 SBL611 SBL601 DIR61 TXDLV61 SBRF61 SBF reception status flag If POWER61 = 0 and RXE61 = 0 or if SBF reception has been completed correctly SBF reception in progress SBRT61...
Page 333 CHAPTER 14 SERIAL INTERFACES UART60 AND UART61 Figure 14-18. Format of Asynchronous Serial Interface Control Register 61 (ASICL61) (2/2) SBL621 SBL611 SBL601 SBF transmission output width control SBF is output with 13-bit length. SBF is output with 14-bit length. SBF is output with 15-bit length. SBF is output with 16-bit length.
Page 334 CHAPTER 14 SERIAL INTERFACES UART60 AND UART61 (7) Input switch control register (ISC) The input switch control register (ISC) is used to receive a status signal transmitted from the master during LIN (Local Interconnect Network) reception. The input source is switched by setting ISC. This register can be set by a 1-bit or 8-bit memory manipulation instruction.
Page 335 CHAPTER 14 SERIAL INTERFACES UART60 AND UART61 (8) Port mode register 1 (PM1) This register sets port 1 input/output in 1-bit units. When using the P13/TxD60 and P10/SCK10/TxD61 pins for serial interface data output, clear PM13 and PM10 to 0 and set the output latch of P13 and P10 to 1. When using the P14/RxD60 and P11/SI10/RxD61 in for serial interface data input, set PM14 and PM11 to 1.
Page 336: Operations Of Serial Interface Uart60 And Uart61
CHAPTER 14 SERIAL INTERFACES UART60 AND UART61 14.4 Operations of Serial Interface UART60 and UART61 Serial interfaces UART60 and UART61 have the following two modes. • Operation stop mode • Asynchronous serial interface (UART) mode 14.4.1 Operation stop mode In this mode, serial communication cannot be executed; therefore, the power consumption can be reduced. In addition, the pins can be used as ordinary port pins in this mode.
Page 337: Asynchronous Serial Interface (Uart) Mode
CHAPTER 14 SERIAL INTERFACES UART60 AND UART61 14.4.2 Asynchronous serial interface (UART) mode In this mode, data of 1 byte is transmitted/received following a start bit, and a full-duplex operation can be performed. A dedicated UART baud rate generator is incorporated, so that communication can be executed at a wide range of baud rates.
Page 338 CHAPTER 14 SERIAL INTERFACES UART60 AND UART61 The relationship between the register settings and pins is shown below. Table 14-2. Relationship Between Register Settings and Pins (a) UART60 POWER6n TXE6n RXE6n PM13 PM14 UART60 Pin Function Operation TxD60/P13 RxD60/P14 Note Note Note Note...
Page 339 CHAPTER 14 SERIAL INTERFACES UART60 AND UART61 (2) Communication operation (a) Format and waveform example of normal transmit/receive data Figures 14-21 and 14-22 show the format and waveform example of the normal transmit/receive data. Figure 14-21. Format of Normal UART Transmit/Receive Data 1.
Page 340 CHAPTER 14 SERIAL INTERFACES UART60 AND UART61 Figure 14-22. Example of Normal UART Transmit/Receive Data Waveform 1. Data length: 8 bits, LSB first, Parity: Even parity, Stop bit: 1 bit, Communication data: 55H 1 data frame Start Parity Stop 2. Data length: 8 bits, MSB first, Parity: Even parity, Stop bit: 1 bit, Communication data: 55H 1 data frame Start Parity...
Page 341 CHAPTER 14 SERIAL INTERFACES UART60 AND UART61 (b) Parity types and operation The parity bit is used to detect a bit error in communication data. Usually, the same type of parity bit is used on both the transmission and reception sides. With even parity and odd parity, a 1-bit (odd number) error can be detected.
Page 342 CHAPTER 14 SERIAL INTERFACES UART60 AND UART61 (c) Normal transmission When bit 7 (POWER6n) of asynchronous serial interface operation mode register 6n (ASIM6n) is set to 1 and bit 6 (TXE6n) of ASIM6n is then set to 1, transmission is enabled. Transmission can be started by writing transmit data to transmit buffer register 6n (TXB6n).
Page 343 CHAPTER 14 SERIAL INTERFACES UART60 AND UART61 (d) Continuous transmission The next transmit data can be written to transmit buffer register 6n (TXB6n) as soon as transmit shift register 6 (TXS6n) has started its shift operation. Consequently, even while the INTST6n interrupt is being serviced after transmission of one data frame, data can be continuously transmitted and an efficient communication rate can be realized.
Page 344 CHAPTER 14 SERIAL INTERFACES UART60 AND UART61 Figure 14-24 shows an example of the continuous transmission processing flow. Figure 14-24. Example of Continuous Transmission Processing Flow Set registers. Write TXB6n. Transfer executed necessary number of times? Read ASIF6n TXBF6n = 0? Write TXB6n.
Page 345 CHAPTER 14 SERIAL INTERFACES UART60 AND UART61 Figure 14-25 shows the timing of starting continuous transmission, and Figure 14-25 shows the timing of ending continuous transmission. Figure 14-25. Timing of Starting Continuous Transmission Start Data (1) Parity Stop Start Data (2) Parity Stop Start...
Page 346 CHAPTER 14 SERIAL INTERFACES UART60 AND UART61 Figure 14-26. Timing of Ending Continuous Transmission Data (n − 1) Start Start Parity Data (n) Parity Stop Stop Stop INTST6n Data (n − 1) TXB6n Data (n) Data (n − 1) TXS6n Data (n) TXBF6n TXSF6n...
Page 347 CHAPTER 14 SERIAL INTERFACES UART60 AND UART61 (e) Normal reception Reception is enabled and the R D6n pins input is sampled when bit 7 (POWER6n) of asynchronous serial interface operation mode register 6n (ASIM6n) is set to 1 and then bit 5 (RXE6n) of ASIM6n is set to 1. The 8-bit counter of the baud rate generator starts counting when the falling edge of the R D6n pins input is detected.
Page 348 CHAPTER 14 SERIAL INTERFACES UART60 AND UART61 (f) Reception error Three types of errors may occur during reception: a parity error, framing error, or overrun error. If the error flag of asynchronous serial interface reception error status register 6n (ASIS6n) is set as a result of data reception, a reception error interrupt request (INTSR6n/INTSRE6n) is generated.
Page 349 CHAPTER 14 SERIAL INTERFACES UART60 AND UART61 (g) Noise filter of receive data The RXD6n signal’s is sampled with the base clock output by the prescaler block. If two sampled values are the same, the output of the match detector changes, and the data is sampled as input data.
Page 350 CHAPTER 14 SERIAL INTERFACES UART60 AND UART61 (h) SBF transmission When the device is used in LIN communication operation, the SBF (Synchronous Break Field) transmission control function is used for transmission. For the transmission operation of LIN, see Figure 14-1 LIN Transmission Operation.
Page 351 CHAPTER 14 SERIAL INTERFACES UART60 AND UART61 SBF reception When the device is incorporated in LIN, the SBF (Synchronous Break Field) reception control function is used for reception. For the reception operation of LIN, see Figure 14-2 LIN Reception Operation. Reception is enabled when bit 7 (POWER6n) of asynchronous serial interface operation mode register 6n (ASIM6n) is set to 1 and then bit 5 (RXE6n) of ASIM6n is set to 1.
Page 352: Dedicated Baud Rate Generator
CHAPTER 14 SERIAL INTERFACES UART60 AND UART61 14.4.3 Dedicated baud rate generator The dedicated baud rate generator consists of a source clock selector and an 8-bit programmable counter, and generates a serial clock for transmission/reception of UART60 and UART61. Separate 8-bit counters are provided for transmission and reception. (1) Configuration of baud rate generator •...
Page 353 CHAPTER 14 SERIAL INTERFACES UART60 AND UART61 Figure 14-32. Configuration of Baud Rate Generator POWER6n Baud rate generator POWER6n, TXE6n (or RXE6n) Selector 8-bit counter XCLK6 Match detector Baud rate 8-bit timer/ event counter 50 output CKSR6n: TPS63n to TPS60n BRGC6n: MDL67n to MDL60n Remark POWER6n: Bit 7 of asynchronous serial interface operation mode register 6n (ASIM6n) TXE6n:...
Page 354 CHAPTER 14 SERIAL INTERFACES UART60 AND UART61 Cautions 1. Keep the baud rate error during transmission to within the permissible error range at the reception destination. 2. Make sure that the baud rate error during reception satisfies the range shown in (4) Permissible baud rate range during reception.
Page 355 CHAPTER 14 SERIAL INTERFACES UART60 AND UART61 (4) Permissible baud rate range during reception The permissible error from the baud rate at the transmission destination during reception is shown below. Caution Make sure that the baud rate error during reception is within the permissible error range, by using the calculation expression shown below.
Page 356 CHAPTER 14 SERIAL INTERFACES UART60 AND UART61 Minimum permissible data frame length: FLmin = 11 × FL − × FL = k − 2 21k + 2 Therefore, the maximum receivable baud rate at the transmission destination is as follows. −...
Page 357 CHAPTER 14 SERIAL INTERFACES UART60 AND UART61 (5) Data frame length during continuous transmission When data is continuously transmitted, the data frame length from a stop bit to the next start bit is extended by two clocks of base clock from the normal value. However, the result of communication is not affected because the timing is initialized on the reception side when the start bit is detected.
Page 358: Chapter 15 Serial Interfaces Csi10 And Csi11
CHAPTER 15 SERIAL INTERFACES CSI10 AND CSI11 The 78K0/FF2 incorporate serial interfaces CSI10 and CSI11. 15.1 Functions of Serial Interfaces CSI10 and CSI11 Serial interfaces CSI10 and CSI11 have the following two modes. • Operation stop mode • 3-wire serial I/O mode...
Page 359: Configuration Of Serial Interfaces Csi10 And Csi11
CHAPTER 15 SERIAL INTERFACES CSI10 AND CSI11 15.2 Configuration of Serial Interfaces CSI10 and CSI11 Serial interfaces CSI10 and CSI11 include the following hardware. Table 15-1. Configuration of Serial Interfaces CSI10 and CSI11 Item Configuration Controller Transmit controller Clock start/stop controller & clock phase controller Registers Transmit buffer register 1n (SOTB1n) Serial I/O shift register 1n (SIO1n)
Page 360 CHAPTER 15 SERIAL INTERFACES CSI10 AND CSI11 Figure 15-2. Block Diagram of Serial Interface CSI11 Internal bus Serial I/O shift Transmit buffer Output SI11/P75 register 11 (SIO11) register 11 (SOTB11) SO11/P74 selector Output latch Transmit data Output latch (P74) controller SSI11 PM74 Transmit controller...
Page 361: Registers Controlling Serial Interfaces Csi10 And Csi11
CHAPTER 15 SERIAL INTERFACES CSI10 AND CSI11 15.3 Registers Controlling Serial Interfaces CSI10 and CSI11 Serial interfaces CSI10 and CSI11 are controlled by the following four registers. • Serial operation mode register 1n (CSIM1n) • Serial clock selection register 1n (CSIC1n) •...
Page 362 CHAPTER 15 SERIAL INTERFACES CSI10 AND CSI11 Figure 15-4. Format of Serial Operation Mode Register 11 (CSIM11) Note 1 Address: FF88H After reset: 00H R/W Symbol <7> CSIM11 CSIE11 TRMD11 SSE11 DIR11 CSOT11 CSIE11 Operation control in 3-wire serial I/O mode Note 2 Note 3 Disables operation...
Page 363 CHAPTER 15 SERIAL INTERFACES CSI10 AND CSI11 (2) Serial clock selection register 1n (CSIC1n) This register specifies the timing of the data transmission/reception and sets the serial clock. CSIC1n can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears this register to 00H.
Page 364 CHAPTER 15 SERIAL INTERFACES CSI10 AND CSI11 Figure 15-6. Format of Serial Clock Selection Register 11 (CSIC11) Address: FF89H After reset: 00H R/W Symbol CSIC11 CKP11 DAP11 CKS112 CKS111 CKS110 CKP11 DAP11 Specification of data transmission/reception timing Type SCK11 SO11 D7 D6 D5 D4 D3 D2 D1 D0 SI11 input timing SCK11...
Page 365 CHAPTER 15 SERIAL INTERFACES CSI10 AND CSI11 (3) Port mode registers 0, 1 and 7 (PM0, PM1, PM7) These registers set port 0, 1 and 7 input/output in 1-bit units. When using P10/SCK10 and P76/SCK11 as the clock output pins of the serial interface, clear PM10 and PM76, and the output latches of P10 and P76 to 1.
Page 366: Operation Of Serial Interfaces Csi10 And Csi11
CHAPTER 15 SERIAL INTERFACES CSI10 AND CSI11 15.4 Operation of Serial Interfaces CSI10 and CSI11 Serial interfaces CSI10 and CSI11 can be used in the following two modes. • Operation stop mode • 3-wire serial I/O mode 15.4.1 Operation stop mode Serial communication is not executed in this mode.
Page 367: 3-Wire Serial I/O Mode
CHAPTER 15 SERIAL INTERFACES CSI10 AND CSI11 15.4.2 3-wire serial I/O mode The 3-wire serial I/O mode is used for connecting peripheral ICs and display controllers with a clocked serial interface. In this mode, communication is executed by using three lines: the serial clock (SCK1n), serial output (SO1n), and serial input (SI1n) lines.
Page 368 CHAPTER 15 SERIAL INTERFACES CSI10 AND CSI11 The relationship between the register settings and pins is shown below. Table 15-2. Relationship Between Register Settings and Pins (1/2) (a) Serial interface CSI10 CSIE10 TRMD10 PM11 PM12 PM10 CSI10 Pin Function Operation SI10/RxD61/ SO10/P12 SCK10/TxD61/ Note 1...
Page 369 CHAPTER 15 SERIAL INTERFACES CSI10 AND CSI11 Table 15-2. Relationship Between Register Settings and Pins (2/2) (b) Serial interface CSI11 CSIE11 TRMD11 SSE11 PM75 P75 PM74 P74 PM76 P76 PM05 P05 CSI11 Pin Function Operation SI11/ SO11/ SCK11/ SSI11/ TI001/P05 Note 1 Note 1 Note 1...
Page 370 CHAPTER 15 SERIAL INTERFACES CSI10 AND CSI11 (2) Communication operation In the 3-wire serial I/O mode, data is transmitted or received in 8-bit units. Each bit of the data is transmitted or received in synchronization with the serial clock. Data can be transmitted or received if bit 6 (TRMD1n) of serial operation mode register 1n (CSIM1n) is 1. Transmission/reception is started when a value is written to transmit buffer register 1n (SOTB1n).
Page 371 CHAPTER 15 SERIAL INTERFACES CSI10 AND CSI11 Figure 15-10. Timing in 3-Wire Serial I/O Mode (1/2) Note (1) Transmission/reception timing (Type 1; TRMD1n = 1, DIR1n = 0, CKP1n = 0, DAP1n = 0, SSE11 = 1 Note SSI11 SCK1n Read/write trigger SOTB1n 55H (communication data)
Page 372 CHAPTER 15 SERIAL INTERFACES CSI10 AND CSI11 Figure 15-10. Timing in 3-Wire Serial I/O Mode (2/2) Note (2) Transmission/reception timing (Type 2; TRMD1n = 1, DIR1n = 0, CKP1n = 0, DAP1n = 1, SSE11 = 1 Note SSI11 SCK1n Read/write trigger SOTB1n 55H (communication data)
Page 373 CHAPTER 15 SERIAL INTERFACES CSI10 AND CSI11 Figure 15-11. Timing of Clock/Data Phase (a) Type 1; CKP1n = 0, DAP1n = 0, DIR1n = 0 SCK1n SI1n capture SO1n Writing to SOTB1n or reading from SIO1n CSIIF1n CSOT1n (b) Type 2; CKP1n = 0, DAP1n = 1, DIR1n = 0 SCK1n SI1n capture SO1n...
Page 374 CHAPTER 15 SERIAL INTERFACES CSI10 AND CSI11 (3) Timing of output to SO1n pin (first bit) When communication is started, the value of transmit buffer register 1n (SOTB1n) is output from the SO1n pin. The output operation of the first bit at this time is described below. Figure 15-12.
Page 375 CHAPTER 15 SERIAL INTERFACES CSI10 AND CSI11 Figure 15-12. Output Operation of First Bit (2/2) (c) Type 2: CKP1n = 0, DAP1n = 1 SCK1n Writing to SOTB1n or reading from SIO1n SOTB1n SIO1n Output latch SO1n First bit 2nd bit 3rd bit (d) Type 4: CKP1n = 1, DAP1n = 1 SCK1n...
Page 376 CHAPTER 15 SERIAL INTERFACES CSI10 AND CSI11 (4) Output value of SO1n pin (last bit) After communication has been completed, the SO1n pin holds the output value of the last bit. Figure 15-13. Output Value of SO1n Pin (Last Bit) (1/2) (a) Type 1: CKP1n = 0, DAP1n = 0 SCK1n ( ←...
Page 377 CHAPTER 15 SERIAL INTERFACES CSI10 AND CSI11 Figure 15-13. Output Value of SO1n Pin (Last Bit) (2/2) (c) Type 2: CKP1n = 0, DAP1n = 1 SCK1n Writing to SOTB1n or ( ← Next request is issued.) reading from SIO1n SOTB1n SIO1n Output latch...
Page 378 CHAPTER 15 SERIAL INTERFACES CSI10 AND CSI11 (5) SO1n output (see (a) in Figures 15-1 and 15-2) The status of the SO1n output is as follows if bit 7 (CSIE1n) of serial operation mode register 1n (CSIM1n) is cleared to 0. Table 15-3.
Page 379: Chapter 16 Can Controller
CHAPTER 16 CAN CONTROLLER 16.1 Outline Description This product features an on-chip 1-channel CAN (Controller Area Network) controller that complies with CAN protocol as standardized in ISO 11898. 16.1.1 Features - Compliant with ISO 11898 and tested according to ISO/DIS 16845 (CAN conformance test) - Standard frame and extended frame transmission/reception enabled - Transfer rate: 1 Mbps max.
Page 380: Overview Of Functions
CHAPTER 16 CAN CONTROLLER 16.1.2 Overview of functions Table 16-1 presents an overview of the CAN controller functions. Table 16-1. Overview of Functions Function Details Protocol CAN protocol ISO 11898 (standard and extended frame transmission/reception) Maximum 1 Mbps (CAN clock input ≥ 8 MHz) Baud rate Data storage Storing messages in the CAN RAM...
Page 381: Configuration
CHAPTER 16 CAN CONTROLLER 16.1.3 Configuration The CAN controller is composed of the following four blocks. (1) NPB interface This functional block provides an NPB (NEC peripheral I/O bus) interface and means of transmitting and receiving signals between the CAN module and the host CPU. (2) MCM (Message Control Module) This functional block controls access to the CAN protocol layer and to the CAN RAM within the CAN module.
Page 382: Can Protocol
CHAPTER 16 CAN CONTROLLER 16.2 CAN Protocol CAN (Controller Area Network) is a high-speed multiplex communication protocol for real-time communication in automotive applications (class C). CAN is prescribed by ISO 11898. For details, refer to the ISO 11898 specifications. The CAN specification is generally divided into two layers: a physical layer and a data link layer. In turn, the data link layer includes logical link and medium access control.
Page 383: Frame Types
CHAPTER 16 CAN CONTROLLER 16.2.2 Frame types The following four types of frames are used in the CAN protocol. Table 16-2. Frame Types Frame Type Description Data frame Frame used to transmit data Remote frame Frame used to request a data frame Error frame Frame used to report error detection Overload frame...
Page 384 CHAPTER 16 CAN CONTROLLER (2) Remote frame A remote frame is composed of six fields. Figure 16-4. Remote Frame Remote frame <1> <2> <3> <5> <6> <7> <8> Interframe space End of frame (EOF) ACK field CRC field Control field Arbitration field Start of frame (SOF) Remarks 1.
Page 385 CHAPTER 16 CAN CONTROLLER <2> Arbitration field The arbitration field is used to set the priority, data frame/remote frame, and frame format. Figure 16-6. Arbitration Field (in Standard Format Mode) Arbitration field (Control field) Identifier (r1) ID28 · · · · · · · · · · · · · · · · · · · · ID18 (11 bits) (1 bit) (1 bit)
Page 386 CHAPTER 16 CAN CONTROLLER <3> Control field The control field sets “N” as the number of data bytes in the data field (N = 0 to 8). Figure 16-8. Control Field (Arbitration field) Control field (Data field) DLC3 DLC2 DLC1 DLC0 (IDE) Remark...
Page 387 CHAPTER 16 CAN CONTROLLER <4> Data field The data field contains the amount of data (byte units) set by the control field. Up to 8 units of data can be set. Figure 16-9. Data Field (Control field) Data field (CRC field) Data0 Data7 (8 bits)
Page 388 CHAPTER 16 CAN CONTROLLER <6> ACK field The ACK field is used to acknowledge normal reception. Figure 16-11. ACK Field (CRC field) ACK field (End of frame) ACK slot ACK delimiter (1 bit) (1 bit) Remark D: Dominant = 0 R: Recessive = 1 - If no CRC error is detected, the receiving node sets the ACK slot to the dominant level.
Page 389 CHAPTER 16 CAN CONTROLLER <8> Interframe space The interframe space is inserted after a data frame, remote frame, error frame, or overload frame to separate one frame from the next. - The bus state differs depending on the error status. (a) Error active node The interframe space consists of a 3-bit intermission field and a bus idle field.
Page 390 CHAPTER 16 CAN CONTROLLER - Operation in error status Table 16-6. Operation in Error Status Error Status Operation Error active A node in this status can transmit immediately after a 3-bit intermission. Error passive A node in this status can transmit 8 bits after the intermission. User’s Manual U17553EJ4V0UD...
Page 391: Error Frame
CHAPTER 16 CAN CONTROLLER 16.2.4 Error frame An error frame is output by a node that has detected an error. Figure 16-15. Error Frame Error frame (<4>) <1> <2> <3> (<5>) 6 bits 0 to 6 bits 8 bits Interframe space or overload frame Error delimiter Error flag2 Error flag1...
Page 392: Overload Frame
CHAPTER 16 CAN CONTROLLER 16.2.5 Overload frame An overload frame is transmitted under the following conditions. Note - When the receiving node has not completed the reception operation - If a dominant level is detected at the first two bits during intermission - If a dominant level is detected at the last bit (7th bit) of the end of frame or at the last bit (8th bit) of the error delimiter/overload delimiter Note The CAN is internally fast enough to process all received frames not generating overload frames.
Page 393: Functions
CHAPTER 16 CAN CONTROLLER 16.3 Functions 16.3.1 Determining bus priority (1) When a node starts transmission: - During bus idle, the node that output data first transmits the data. (2) When more than one node starts transmission: - The node that outputs the dominant level for the longest consecutively from the first bit of the arbitration field acquires the bus priority (if a dominant level and a recessive level are simultaneously transmitted, the dominant level is taken as the bus value).
Page 394: Error Control Function
CHAPTER 16 CAN CONTROLLER The controller is woken up from the CAN sleep mode by bus operation but it is not woken up from the CAN stop mode by bus operation (the CAN stop mode is controlled by CPU access). 16.3.6 Error control function (1) Error types Table 16-11.
Page 395 CHAPTER 16 CAN CONTROLLER (4) Error state (a) Types of error states The following three types of error states are defined by the CAN specification. - Error active - Error passive - Bus-off These types of error states are classified by the values of the TEC7 to TEC0 bits (transmission error counter bits) and the REC6 to REC0 bits (reception error counter bits) of the CAN error counter register (C0ERC) as shown in Table 16-13.
Page 396 CHAPTER 16 CAN CONTROLLER Table 16-13. Types of Error States Type Operation Value of Error Indication of Operation specific to Given Error State Counter C0INFO Register Error active Transmission 0-95 TECS1, TECS0 = 00 - Outputs an active error flag (6 consecutive dominant-level bits) on detection of the Reception 0-95...
Page 397 CHAPTER 16 CAN CONTROLLER (b) Error counter The error counter counts up when an error has occurred, and counts down upon successful transmission and reception. The error counter is updated immediately after error detection. Table 16-14. Error Counter State Transmission Error Counter Reception Error Counter (TEC7 to TEC0) (REC6 to REC0)
Page 398 CHAPTER 16 CAN CONTROLLER (5) Recovery from bus-off state When the CAN module is in the bus-off state, the CAN module permanently sets its output signals (CTxD) to recessive level. The CAN module recovers from the bus-off state in the following bus-off recovery sequence. <1>...
Page 399 CHAPTER 16 CAN CONTROLLER Figure 16-17. Recovery Operation from Bus-off State through Normal Recovery Sequence TEC > FFH »bus-off« »bus-off-recovery-sequence« »error-active« »error-passive« BOFF bit in C0INFO register <1> <2> OPMODE[2:0] in C0CTRL ≠ 00H ≠ 00H register (user writings) <3> OPMODE[2:0] in C0CTRL ≠...
Page 400: Baud Rate Control Function
CHAPTER 16 CAN CONTROLLER 16.3.7 Baud rate control function (1) Prescaler The CAN controller has a prescaler that divides the clock (f ) supplied to CAN. This prescaler generates a CAN protocol layer basic clock (f ) derived from the CAN module system clock (f ), and divided by 1 to CANMOD 256 (refer to 16.6 (12) CAN Bit Rate Prescaler Register (C0BRP)).
Page 401 CHAPTER 16 CAN CONTROLLER Reference: The CAN standard ISO 11898 specification defines the segments constituting the data bit time as shown in Figure 16-19. Figure 16-19. Reference: Configuration of Data Bit Time Defined by CAN Specification Data bit time(DBT) Sync segment Prop segment Phase segment 1 Phase segment 2...
Page 402 CHAPTER 16 CAN CONTROLLER (3) Synchronizing data bit - The receiving node establishes synchronization by a level change on the bus because it does not have a sync signal. - The transmitting node transmits data in synchronization with the bit timing of the transmitting node. (a) Hard-synchronization This synchronization is established when the receiving node detects the start of frame in the interframe space.
Page 403 CHAPTER 16 CAN CONTROLLER (b) Resynchronization Synchronization is established again if a level change is detected on the bus during reception (only if a recessive level was sampled previously). - The phase error of the edge is given by the relative position of the detected edge and sync segment. <Sign of phase error>...
Page 404: Connection With Target System
CHAPTER 16 CAN CONTROLLER 16.4 Connection with Target System The microcontroller incorporated a CAN has to be connected to the CAN bus using an external transceiver. Figure 16-22. Connection to CAN Bus CTxD CANL Microcontroller Transceiver incorporated CRxD CANH a CAN User’s Manual U17553EJ4V0UD...
Page 405: Internal Registers Of Can Controller
CHAPTER 16 CAN CONTROLLER 16.5 Internal Registers of CAN Controller 16.5.1 CAN controller configuration Table 16-15. List of CAN Controller Registers Item Register Name CAN global registers CAN global control register (C0GMCTRL) CAN global clock selection register (C0GMCS) CAN global automatic block transmission control register (C0GMABT) CAN global automatic block transmission delay register (C0GMABTD) CAN module registers CAN module mask 1 register (C0MASK1L, C0MASK1H)
Page 406: Register Access Type
CHAPTER 16 CAN CONTROLLER 16.5.2 Register access type Table 16-16. Register Access Types (1/9) Address Register Name Symbol Bit Manipulation Units Default Value √ FA00H CAN0 message data byte 01 register 00 C0MDATA0100 Undefined √ FA00H CAN0 message data byte 0 register 00 C0MDATA000 Undefined √...
Page 407 CHAPTER 16 CAN CONTROLLER Table 16-16. Register Access Types (2/9) Address Register Name Symbol Bit Manipulation Units Default Value √ FA20H CAN0 message data byte 01 register 02 C0MDATA0102 Undefined √ FA20H CAN0 message data byte 0 register 02 C0MDATA002 Undefined √...
Page 408 CHAPTER 16 CAN CONTROLLER Table 16-16. Register Access Types (3/9) Address Register Name Symbol Bit Manipulation Units Default Value √ FA40H CAN0 message data byte 01 register 04 C0MDATA0104 Undefined √ FA40H CAN0 message data byte 0 register 04 C0MDATA004 Undefined √...
Page 409 CHAPTER 16 CAN CONTROLLER Table 16-16. Register Access Types (4/9) Address Register Name Symbol Bit Manipulation Units Default Value √ FA60H CAN0 message data byte 01 register 06 C0MDATA0106 Undefined √ FA60H CAN0 message data byte 0 register 06 C0MDATA006 Undefined √...
Page 410 CHAPTER 16 CAN CONTROLLER Table 16-16. Register Access Types (5/9) Address Register Name Symbol Bit Manipulation Units Default Value √ FA80H CAN0 message data byte 01 register 08 C0MDATA0108 Undefined √ FA80H CAN0 message data byte 0 register 08 C0MDATA008 Undefined √...
Page 411 CHAPTER 16 CAN CONTROLLER Table 16-16. Register Access Types (6/9) Address Register Name Symbol Bit Manipulation Units Default Value √ FAA0H CAN0 message data byte 01 register 10 C0MDATA0110 Undefined √ FAA0H CAN0 message data byte 0 register 10 C0MDATA010 Undefined √...
Page 412 CHAPTER 16 CAN CONTROLLER Table 16-16. Register Access Types (7/9) Address Register Name Symbol Bit Manipulation Units Default Value √ FAC0H CAN0 message data byte 01 register 12 C0MDATA0112 Undefined √ FAC0H CAN0 message data byte 0 register 12 C0MDATA012 Undefined √...
Page 413 CHAPTER 16 CAN CONTROLLER Table 16-16. Register Access Types (8/9) Address Register Name Symbol Bit Manipulation Units Default Value √ FAE0H CAN0 message data byte 01 register 14 C0MDATA0114 Undefined √ FAE0H CAN0 message data byte 0 register 14 C0MDATA014 Undefined √...
Page 414 CHAPTER 16 CAN CONTROLLER Table 16-16. Register Access Types (9/9) Address Register Name Symbol Bit Manipulation Units Default Value √ FF60H CAN0 module receive history list register C0RGPT – xx02H √ FF62H CAN0 module transmit history list register C0TGPT – –...
Page 415: Register Bit Configuration
CHAPTER 16 CAN CONTROLLER 16.5.3 Register bit configuration Table 16-17. Bit Configuration of CAN Global Registers Address Symbol Bit 7/15 Bit 6/14 Bit 5/13 Bit 4/12 Bit 3/11 Bit 2/10 Bit 1/9 Bit 0/8 FF64H C0GMCTRL(W) Clear FF65H Set EFSD Set GOM FF64H C0GMCTRL(R)
Page 416 CHAPTER 16 CAN CONTROLLER Table 16-18. Bit Configuration of CAN Module Registers (1/2) Address Symbol Bit 7/15 Bit 6/14 Bit 5/13 Bit 4/12 Bit 3/11 Bit 2/10 Bit 1/9 Bit 0/8 FF60H C0RGPT(W) Clear ROVF FF61H FF60H C0RGPT(R) RHPM ROVF FF61H RGPT[7:0] FF62H...
Page 417 CHAPTER 16 CAN CONTROLLER Table 16-18. Bit Configuration of CAN Module Registers (2/2) Address Symbol Bit 7/15 Bit 6/14 Bit 5/13 Bit 4/12 Bit 3/11 Bit 2/10 Bit 1/9 Bit 0/8 FF90H C0CTRL(W) Clear Clear Clear Clear Clear Clear Clear Clear CCERC VALID...
Page 418 CHAPTER 16 CAN CONTROLLER Table 16-19. Bit Configuration of Message Buffer Registers Address Symbol Bit 7/15 Bit 6/14 Bit 5/13 Bit 4/12 Bit 3/11 Bit 2/10 Bit 1/9 Bit 0/8 FAx0H C0MDATA01m Message data (byte 0) FAx1H Message data (byte 1) FAx0H C0MDATA0m Message data (byte 0)
Page 419: Bit Set/Clear Function
CHAPTER 16 CAN CONTROLLER 16.6 Bit Set/Clear Function The CAN control registers include registers whose bits can be set or cleared via the CPU and via the CAN interface. An operation error occurs if the following registers are written directly. Do not write any values directly via bit manipulation, read/modify/write, or direct writing of target values.
Page 420 CHAPTER 16 CAN CONTROLLER Figure 16-24. 16-Bit Data during Write Operation set 7 set 6 set 5 set 4 set 3 set 2 set 1 set 0 clear 7 clear 6 clear 5 clear 4 clear 3 clear 2 clear 1 clear 0 set n clear n Status of bit n after bit set/clear operation...
Page 421: Control Registers
CHAPTER 16 CAN CONTROLLER 16.7 Control Registers Remark m = 0 to 15 (1) CAN global control register (C0GMCTRL) The C0GMCTRL register is used to control the operation of the CAN module. After reset: 0000H Address: FF64H, FF65H (a) Read C0GMCTRL MBON EFSD...
Page 422 CHAPTER 16 CAN CONTROLLER EFSD Bit Enabling Forced Shut Down Forced shut down by GOM = 0 disabled. Forced shut down by GOM = 0 enabled. Caution To request forced shutdown, the GOM bit must be cleared to 0 in a subsequent, immediately following write access after the EFSD bit has been set to 1.
Page 423 CHAPTER 16 CAN CONTROLLER (2) CAN global clock selection register (C0GMCS) The C0GMCS register is used to select the CAN module system clock. After reset: 0FH Address: FF6EH C0GMCS CCP3 CCP2 CCP1 CCP0 CCP3 CCP2 CCP1 CCP1 CAN Module System Clock (f CANMOD /16 (Default value) Remark f...
Page 424 CHAPTER 16 CAN CONTROLLER (3) CAN global automatic block transmission control register (C0GMABT) The C0GMABT register is used to control the automatic block transmission (ABT) operation. After reset: 0000H Address: FF66H, FF67H (a) Read C0GMABT ABTCLR ABTTRG (b) Write C0GMABT ABTCLR ABTTRG Clear...
Page 425 CHAPTER 16 CAN CONTROLLER (b) Write Set ABTCLR Automatic Block Transmission Engine Clear Request Bit The automatic block transmission engine is in idle state or under operation. Request to clear the automatic block transmission engine. After the automatic block transmission engine has been cleared, automatic block transmission is started from message buffer 0 by setting the ABTTRG bit to 1.
Page 426 CHAPTER 16 CAN CONTROLLER (4) CAN global automatic block transmission delay setting register (C0GMABTD) The C0GMABTD register is used to set the interval at which the data of the message buffer assigned to ABT is to be transmitted in the normal operation mode with ABT. After reset: 00H Address: FF6FH C0GMABTD...
Page 427 CHAPTER 16 CAN CONTROLLER (5) CAN module mask control register (C0MASKaL, C0MASKaH) (a = 1, 2, 3, or 4) The C0MASKaL and C0MASKaH registers are used to extend the number of receivable messages into the same message buffer by masking part of the ID comparison of a message and invalidating the ID of the masked part.
Page 428 CHAPTER 16 CAN CONTROLLER CAN Module Mask 3 Register (C0MASK3L, C0MASK3H) After reset: Undefined Address: C0MASK3L FF78H, FF79H C0MASK3H FF7AH, FF7BH C0MASK3L CMID15 CMID14 CMID13 CMID12 CMID11 CMID10 CMID9 CMID8 CMID7 CMID6 CMID5 CMID4 CMID3 CMID2 CMID1 CMID0 C0MASK3H CMID28 CMID27 CMID26 CMID25 CMID24 CMID23 CMID22 CMID21 CMID20 CMID19 CMID18 CMID17 CMID16 CAN Module Mask 4 Register (C0MASK4L, C0MASK4H) After reset: Undefined...
Page 429 CHAPTER 16 CAN CONTROLLER (6) CAN module control register (C0CTRL) The C0CTRL register is used to control the operation mode of the CAN module. After reset: 0000H Address: FF90H, FF91H (a) Read C0CTRL RSTAT TSTAT CCERC VALID PSMODE1 PSMODE0 OPMODE2 OPMODE1 OPMODE0 (b) Write C0CTRL CCERC...
Page 430 CHAPTER 16 CAN CONTROLLER TSTAT Transmission Status Bit Transmission is stopped. Transmission is in progress. Remark - The TSTAT bit is set to 1 under the following conditions (timing). - The SOF bit of a transmit frame is detected - The first bit of an error flag is detected during a transmit frame - The TSTAT bit is cleared to 0 under the following conditions (timing).
Page 431 CHAPTER 16 CAN CONTROLLER PSMODE1 PSMODE0 Power Save Mode No power save mode is selected. CAN sleep mode Setting prohibited CAN stop mode Cautions 1. Transition to and from the CAN stop mode must be made via CAN sleep mode. A request for direct transition to and from the CAN stop mode is ignored.
Page 432 CHAPTER 16 CAN CONTROLLER Clear VALID Setting of VALID Bit VALID bit is not changed. VALID bit is cleared to 0. Clear Setting of PSMODE0 Bit PSMODE0 PSMODE0 PSMODE0 bit is cleared to 0. PSMODE bit is set to 1. Other than above PSMODE0 bit is not changed.
Page 433 CHAPTER 16 CAN CONTROLLER (7) CAN module last error code register (C0LEC) The C0LEC register provides the error information of the CAN protocol. After reset: 00H Address: FF92H C0LEC LEC2 LEC1 LEC0 Remarks 1. The contents of the C0LEC register are not cleared when the CAN module changes from an operation mode to the initialization mode.
Page 434 CHAPTER 16 CAN CONTROLLER (8) CAN module information register (C0INFO) The C0INFO register indicates the status of the CAN module. After reset: 00H Address: FF93H C0INFO BOFF TECS1 TECS0 RECS1 RECS0 BOFF Bus-off State Bit Not bus-off state (transmit error counter ≤ 255) (The value of the transmit counter is less than 256.) Bus-off state (transmit error counter >...
Page 435 CHAPTER 16 CAN CONTROLLER (9) CAN module error counter register (C0ERC) The C0ERC register indicates the count value of the transmission/reception error counter. After reset: 0000H Address: FF94H, FF95H C0ERC REPS REC6 REC5 REC4 REC3 REC2 REC1 REC0 TEC7 TEC6 TEC5 TEC4 TEC3...
Page 436 CHAPTER 16 CAN CONTROLLER (10) CAN module interrupt enable register (C0IE) The C0IE register is used to enable or disable the interrupts of the CAN module. After reset: 0000H Address: FF96H, FF97H (a) Read C0IE CIE5 CIE4 CIE3 CIE2 CIE1 CIE0 (b) Write C0IE...
Page 437 CHAPTER 16 CAN CONTROLLER Set CIE2 Clear CIE2 Setting of CIE2 Bit CIE2 bit is cleared to 0. CIE2 bit is set to 1. Other than above CIE2 bit is not changed. Set CIE1 Clear CIE1 Setting of CIE1 Bit CIE1 bit is cleared to 0.
Page 438 CHAPTER 16 CAN CONTROLLER (11) CAN module interrupt status register (C0INTS) The C0INTS register indicates the interrupt status of the CAN module. After reset: 0000H Address: FF98H, FF99H (a) Read C0INTS CINTS5 CINTS4 CINTS3 CINTS2 CINTS1 CINTS0 (b) Write C0INTS Clear Clear Clear...
Page 439 CHAPTER 16 CAN CONTROLLER (12) CAN module bit rate prescaler register (C0BRP) The C0BRP register is used to select the CAN protocol layer basic clock (f ). The communication baud rate is set to the C0BTR register. After reset: FFH Address: FF9EH C0BRP TQPRS7 TQPRS6 TQPRS5 TQPRS4 TQPRS3 TQPRS2 TQPRS1 TQPRS0...
Page 440 CHAPTER 16 CAN CONTROLLER (13) CAN module bit rate register (C0BTR) The C0BTR register is used to control the data bit time of the communication baud rate. After reset: 370FH Address: FF9CH, FF9DH C0BTR SJW1 SJW0 TSEG22 TSEG21 TSEG20 TSEG13 TSEG12 TSEG11 TSEG10 Figure 16-26.
Page 441 CHAPTER 16 CAN CONTROLLER SJW1 SJW0 Length of Synchronization jump width 4TQ (default value) TSEG22 TSEG21 TSEG20 Length of time segment 2 8TQ (default value) TSEG13 TSEG12 TSEG11 TSEG10 Length of time segment 1 Setting prohibited Note Note 10TQ 11TQ 12TQ 13TQ 14TQ...
Page 442 CHAPTER 16 CAN CONTROLLER (14) CAN module last in-pointer register (C0LIPT) The C0LIPT register indicates the number of the message buffer in which a data frame or a remote frame was last stored. After reset: Undefined Address: FF9FH C0LIPT LIPT7 LIPT6 LIPT5 LIPT4...
Page 443 CHAPTER 16 CAN CONTROLLER (15) CAN module receive history list register (C0RGPT) The C0RGPT register is used to read the receive history list. After reset: xx02H Address: FF60H, FF61H (a) Read C0RGPT RGPT7 RGPT6 RGPT5 RGPT4 RGPT3 RGPT2 RGPT1 RGPT0 RHPM ROVF (b) Write...
Page 444 CHAPTER 16 CAN CONTROLLER (b) Write Clear ROVF Setting of ROVF Bit ROVF bit is not changed. ROVF bit is cleared to 0. (16) CAN module last out-pointer register (C0LOPT) The C0LOPT register indicates the number of the message buffer to which a data frame or a remote frame was transmitted last.
Page 445 CHAPTER 16 CAN CONTROLLER (17) CAN module transmit history list register (C0TGPT) The C0TGPT register is used to read the transmit history list. After reset: xx02H Address: FF62H, FF63H (a) Read C0TGPT TGPT7 TGPT6 TGPT5 TGPT4 TGPT3 TGPT2 TGPT1 TGPT0 THPM TOVF (b) Write...
Page 446 CHAPTER 16 CAN CONTROLLER (b) Write Clear TOVF Setting of TOVF Bit TOVF bit is not changed. TOVF bit is cleared to 0. (18) CAN module time stamp register (C0TS) The C0TS register is used to control the time stamp function. After reset: 0000H Address: FF8AH, FF8BH (a) Read...
Page 447 CHAPTER 16 CAN CONTROLLER TSEN TSOUT Signal Operation Setting Bit Disable TSOUT signal toggle operation. Enable TSOUT signal toggle operation. Remark The signal TSOUT is output from the CAN macro to a timer resource, depending on implementation. Refer to documentation of device implementation for details. (b) Write Set TSLOCK Clear...
Page 448 CHAPTER 16 CAN CONTROLLER (19) CAN message data byte register (C0MDATAxm)(x = 0 to 7), (C0MDATAzm) (z = 01, 23, 45, 67) The C0MDATAxm, C0MDATAzm registers are used to store the data of a transmit/receive message. The C0MDATAzm registers can access the C0MDATAxm registers in 16-bit units. After reset: Undefined Address: See Table 16-16 C0MDATAxm Register...
Page 449 CHAPTER 16 CAN CONTROLLER C0MDATAzm Register C0MDATA01m MDATA011 MDATA011 MDATA011 MDATA011 MDATA011 MDATA011 MDATA019 MDATA018 MDATA017 MDATA016 MDATA015 MDATA014 MDATA013 MDATA012 MDATA011 MDATA010 C0MDATA23m MDATA231 MDATA231 MDATA231 MDATA231 MDATA231 MDATA231 MDATA239 MDATA238 MDATA237 MDATA236 MDATA235 MDATA234 MDATA233 MDATA232 MDATA231 MDATA230 C0MDATA45m MDATA451 MDATA451 MDATA451...
Page 450 CHAPTER 16 CAN CONTROLLER (20) CAN message data length register m (C0MDLCm) The C0MDLCm register is used to set the number of bytes of the data field of a message buffer. After reset: 0000xxxxB Address: See Table 16-16 C0MDLCm MDLC3 MDLC2 MDLC1 MDLC0...
Page 451 CHAPTER 16 CAN CONTROLLER (21) CAN message configuration register (C0MCONFm) The C0MCONFm register is used to specify the type of the message buffer and to set a mask. After reset: Undefined Address: See Table 16-16 C0MCONFm Overwrite Control Bit Note The message buffer that has already received a data frame is not overwritten by a newly received data frame.
Page 452 CHAPTER 16 CAN CONTROLLER Message Buffer Assignment Bit Message buffer not used. Message buffer used. Caution Be sure to write 0 to bits 2 and 1. (22) CAN message id register m (C0MIDLm, C0MIDHm) The C0MIDLm and C0MIDHm registers are used to set an identifier (ID). After reset: Undefined Address: See Table 16-16 C0MIDLm...
Page 453 CHAPTER 16 CAN CONTROLLER (23) CAN message control register m (C0MCTRLm) The C0MCTRLm register is used to control the operation of the message buffer. After reset: 00x000000 Address: See Table 16-16. 00000000B (a) Read C0MCTRLm (b) Write C0MCTRLm Clear Clear Clear Clear Clear...
Page 454 CHAPTER 16 CAN CONTROLLER Message Buffer Data Updating Bit A data frame or remote frame is not stored in the message buffer. A data frame or remote frame is stored in the message buffer. Message Buffer Transmission Request Bit No message frame transmitting request that is pending or being transmitted is in the message buffer. The message buffer is holding transmission of a message frame pending or is transmitting a message frame.
Page 455 CHAPTER 16 CAN CONTROLLER Set TRQ Clear TRQ Setting of TRQ Bit TRQ bit is cleared to 0. TRQ bit is set to 1. Other than above TRQ bit is not changed. Set RDY Clear RDY Setting of RDY Bit RDY bit is cleared to 0.
Page 456: Can Controller Initialization
CHAPTER 16 CAN CONTROLLER 16.8 CAN Controller Initialization 16.8.1 Initialization of CAN module Before the CAN module operation is enabled, the CAN module system clock needs to be determined by setting the CCP[3:0] bits of the C0GMCS register by software. Do not change the setting of the CAN module system clock after CAN module operation is enabled.
Page 457: Transition From Initialization Mode To Operation Mode
CHAPTER 16 CAN CONTROLLER Figure 16-27. Setting Transmission Request (TRQ) to Transmit Message Buffer After Redefining Redefinition completed Execute transmission? Wait for 1 bit of CAN data. Set TRQ bit Set TRQ = 1 Clear TRQ = 0 Cautions 1. When a message is received, reception filtering is performed in accordance with the ID and mask set to each receive message buffer.
Page 458: Resetting Error Counter C0Erc Of Can Module
CHAPTER 16 CAN CONTROLLER Figure 16-28. Transition to Operation Modes OPMODE[2:0] = 00H and CAN bus is busy. [Receive-only mode] OPMODE[2:0]=03H OPMODE[2:0] = 00H OPMODE[2:0] = 00H and CAN bus is busy. and CAN bus is busy. [Normal operation OPMODE[2:0] = 03H mode with ABT] [Single-shot mode] OPMODE[2:0]=02H...
Page 459: Message Reception
CHAPTER 16 CAN CONTROLLER 16.9 Message Reception 16.9.1 Message reception In all the operation modes, the complete message buffer area is analyzed to find a suitable buffer to store a newly received message. All message buffers satisfying the following conditions are included in that evaluation (RX-search process).
Page 460: Receive Data Read
CHAPTER 16 CAN CONTROLLER 16.9.2 Receive Data Read To keep data consistency when reading CAN message buffers, perform the data reading according to Figure 16-51 to 16-53. During message reception, the CAN module sets DN of the C0MCTRLm register two times: at the beginning of the storage process of data to the message buffer, and again at the end of this storage process.
Page 461: Receive History List Function
CHAPTER 16 CAN CONTROLLER 16.9.3 Receive history list function The receive history list (RHL) function records in the receive history list the number of the receive message buffer in which each data frame or remote frame was received and stored. The RHL consists of storage elements equivalent to up to 23 messages, the last in-message pointer (LIPT) with the corresponding C0LIPT register and the receive history list get pointer (RGPT) with the corresponding C0RGPT register.
Page 462 CHAPTER 16 CAN CONTROLLER As long as the RHL contains 23 or less entries the sequence of occurrence is maintained. If more receptions occur without reading the RHL by the host processor, complete sequence of receptions can not be recovered. Figure 16-30.
Page 463: Mask Function
CHAPTER 16 CAN CONTROLLER 16.9.4 Mask function For any message buffer, which is used for reception, the assignment to one of four global reception masks (or no mask) can be selected. By using the mask function, the message ID comparison can be reduced by masked bits, herewith allowing the reception of several different IDs into one buffer.
Page 464 CHAPTER 16 CAN CONTROLLER <3> Mask setting for CAN module 1 (mask 1) (Example) (Using CAN1 address mask 1 registers L and H (C1MASKL1 and C1MASKH1)) CMID28 CMID27 CMID26 CMID25 CMID24 CMID23 CMID22 CMID21 CMID20 CMID19 CMID18 CMID17 CMID16 CMID15 CMID14 CMID13 CMID12...
Page 465: Multi Buffer Receive Block Function
CHAPTER 16 CAN CONTROLLER 16.9.5 Multi buffer receive block function The multi buffer receive block (MBRB) function is used to store a block of data in two or more message buffers sequentially with no CPU interaction, by setting the same ID to two or more message buffers with the same message buffer type.
Page 466: Remote Frame Reception
CHAPTER 16 CAN CONTROLLER 16.9.6 Remote frame reception In all the operation modes, when a remote frame is received, the message buffer that is to store the remote frame is searched from all the message buffers satisfying the following conditions. - Used as a message buffer (MA0 bit of C0MCONFm register set to 1B.) - Set as a transmit message buffer...
Page 467: Message Transmission
CHAPTER 16 CAN CONTROLLER 16.10 Message Transmission 16.10.1 Message transmission In all the operation modes, if the TRQ bit is set to 1 in a message buffer that satisfies the following conditions, the message buffer that is to transmit a message is searched. - Used as a message buffer (MA0 bit of C0MCONFm register set to 1B.) - Set as a transmit message buffer...
Page 468 CHAPTER 16 CAN CONTROLLER Priority Conditions Description 1(high) Value of first 11 bits of ID The message frame with the lowest value represented by the first 11 bits of the ID is transmitted first. If the value of an 11-bit [ID28 to ID18]: standard ID is equal to or smaller than the first 11 bits of a 29-bit extended ID, the 11-bit standard ID has a higher priority than...
Page 469: Transmit History List Function
CHAPTER 16 CAN CONTROLLER 16.10.2 Transmit history list function The transmit history list (THL) function records in the transmit history list the number of the transmit message buffer from which data or remote frames have been were sent. The THL consists of storage elements equivalent to up to seven messages, the last out-message pointer (LOPT) with the corresponding C0LOPT register, and the transmit history list get pointer (TGPT) with the corresponding C0TGPT register.
Page 470 CHAPTER 16 CAN CONTROLLER Figure 16-32. Transmit History List Transmit history list(THL) When message buffer 6 is read Transmit history list(THL) If transmission from message buffers 3 and 4 Last Message buffer 4 Last out-message is completed out-message Message buffer 3 pointer(LOPT) pointer(LOPT) Message buffer 7...
Page 471: Automatic Block Transmission (Abt)
CHAPTER 16 CAN CONTROLLER 16.10.3 Automatic block transmission (ABT) The automatic block transmission (ABT) function is used to transmit two or more data frames successively with no CPU interaction. The maximum number of transmit message buffers assigned to the ABT function is eight (message buffer numbers 0 to 7).
Page 472: Transmission Abort Process
CHAPTER 16 CAN CONTROLLER Cautions 1. Set the ABTCLR bit to 1 while the ABTTRG bit is cleared to 0 in order to resume ABT operation at buffer No.0. If the ABTCLR bit is set to 1 while the ABTTRG bit is set to 1, the subsequent operation is not guaranteed.
Page 473: Remote Frame Transmission
CHAPTER 16 CAN CONTROLLER (3) Transmission abort process for ABT transmission in normal operation mode with automatic block transmission (ABT) To abort ABT that is already started, clear the ABTTRG bit of the C0GMABT register to 0. In this case, the ABTTRG bit remains 1 if an ABT message is currently being transmitted and until the transmission is completed (successfully or not), and is cleared to 0 as soon as transmission is finished.
Page 474: Power Save Modes
CHAPTER 16 CAN CONTROLLER 16.11 Power Save Modes 16.11.1 CAN sleep mode The CAN sleep mode can be used to set the CAN controller to standby mode in order to reduce power consumption. The CAN module can enter the CAN sleep mode from all operation modes. Release of the CAN sleep mode returns the CAN module to exactly the same operation mode from which the CAN sleep mode was entered.
Page 475 CHAPTER 16 CAN CONTROLLER - Even when initialization mode and sleep mode are not requested simultaneously (i.e the first request has not been granted while the second request is made), the request for initialization has priority over the sleep mode request. The sleep mode request is cancelled when the initialization mode is requested. When a pending request for initialization mode is present, a subsequent request for Sleep mode request is cancelled right at the point in time where it was submitted.
Page 476: Can Stop Mode
CHAPTER 16 CAN CONTROLLER 16.11.2 CAN stop mode The CAN stop mode can be used to set the CAN controller to standby mode to reduce power consumption. The CAN module can enter the CAN stop mode only from the CAN sleep mode. Release of the CAN stop mode puts the CAN module in the CAN sleep mode.
Page 477: Example Of Using Power Saving Modes
CHAPTER 16 CAN CONTROLLER 16.11.3 Example of using power saving modes In some application systems, it may be necessary to place the CPU in a power saving mode to reduce the power consumption. By using the power saving mode specific to the CAN module and the power saving mode specific to the CPU in combination, the CPU can be woken up from the power saving status by the CAN bus.
Page 478: Interrupt Function
CHAPTER 16 CAN CONTROLLER 16.12 Interrupt Function The CAN module provides 6 different interrupt sources. The occurrence of these interrupt sources is stored in interrupt status registers. Four separate interrupt request signals are generated from the six interrupt sources. When an interrupt request signal that corresponds to two or more interrupt sources is generated, the interrupt sources can be identified by using an interrupt status register.
Page 479: Diagnosis Functions And Special Operational Modes
CHAPTER 16 CAN CONTROLLER 16.13 Diagnosis Functions and Special Operational Modes The CAN module provides a receive-only mode, single-shot mode, and self-test mode to support CAN bus diagnosis functions or the operation of specific CAN communication methods. 16.13.1 Receive-only mode The receive-only mode is used to monitor receive messages without causing any interference on the CAN bus and can be used for CAN bus analysis nodes.
Page 480: Single-Shot Mode
CHAPTER 16 CAN CONTROLLER Furthermore, ACK is not returned to the CAN bus in this mode upon the valid reception of a message frame. Internally, the local node recognizes that it has transmitted ACK. An overload frame cannot be transmitted to the CAN bus.
Page 481: Self-Test Mode
CHAPTER 16 CAN CONTROLLER 16.13.3 Self-test mode In the self-test mode, message frame transmission and message frame reception can be tested without connecting the CAN node to the CAN bus or without affecting the CAN bus. In the self-test mode, the CAN module is completely disconnected from the CAN bus, but transmission and reception are internally looped back.
Page 482: Receive/Transmit Operation In Each Operation Mode
CHAPTER 16 CAN CONTROLLER 16.13.4 Receive/Transmit Operation in Each Operation Mode Table 16-21 shows outline of the receive/transmit operation in each operation mode. Table 16-21. Outline of the Receive/Transmit in Each Operation Mode Operation Transmission Transmission Transmission Transmission Automatic Set of Store Data Mode of data/...
Page 483: Time Stamp Function
CHAPTER 16 CAN CONTROLLER 16.14 Time Stamp Function CAN is an asynchronous, serial protocol. All nodes connected to the CAN bus have a local, autonomous clock. As a consequence, the clocks of the nodes have no relation (i.e., the clocks are asynchronous and may have different frequencies).
Page 484 CHAPTER 16 CAN CONTROLLER Caution The time stamp function using TSLOCK bit is to stop toggle of TSOUT bit by receiving a data frame in message buffer 0. Therefore, message buffer 0 must be set as a receive message buffer. Since a receive message buffer cannot receive a remote frame, toggle of TSOUT bit cannot be stopped by reception of a remote frame.
Page 485: Baud Rate Settings
CHAPTER 16 CAN CONTROLLER 16.15 Baud Rate Settings 16.15.1 Baud rate settings Make sure that the settings are within the range of limit values for ensuring correct operation of the CAN controller, as follows. (a) 5TQ ≤ SPT (sampling point) ≤ 17 TQ SPT = TSEG1 + 1 (b) 8 TQ ≤...
Page 486 CHAPTER 16 CAN CONTROLLER Table 16-22. Settable Bit Rate Combinations (1/3) Valid Bit Rate Setting C0BTR Register Setting Sampling Point Value (Unit %) DBT Length SYNC PROP PHASE PHASE TSEG1[3:0] TSEG2[2:0] SEGMENT SEGMENT SEGMENT1 SEGMENT2 1111 68.0 1110 66.7 1111 70.8 1101 65.2...
Page 487 CHAPTER 16 CAN CONTROLLER Table 16-22. Settable Bit Rate Combinations (2/3) Valid Bit Rate Setting C0BTR Register Setting Sampling Point Value (Unit %) DBT Length SYNC PROP PHASE PHASE TSEG1[3:0] TSEG2[2:0] SEGMENT SEGMENT SEGMENT1 SEGMENT2 1000 58.8 1001 64.7 1010 70.6 1011 76.5...
Page 488 CHAPTER 16 CAN CONTROLLER Table 16-22. Settable Bit Rate Combinations (3/3) Valid Bit Rate Setting C0BTR Register Setting Sampling Point Value (Unit %) DBT Length SYNC PROP PHASE PHASE TSEG1[3:0] TSEG2[2:0] SEGMENT SEGMENT SEGMENT1 SEGMENT2 0101 63.6 0110 72.7 0111 81.8 1000 90.9...
Page 489: Representative Examples Of Baud Rate Settings
CHAPTER 16 CAN CONTROLLER 16.15.2 Representative examples of baud rate settings Tables 16-23 and 16-24 show representative examples of baud rate setting. Table 16-23. Representative Examples of Baud Rate Settings (f = 8 MHz) (1/2) CANMOD Set Baud Division C0BRP Valid Bit Rate Setting (Unit: kbps) C0BTR Register Samplin...
Page 490 CHAPTER 16 CAN CONTROLLER Table 16-23. Representative Examples of Baud Rate Settings (f = 8 MHz) (2/2) CANMOD Set Baud Division C0BRP Valid Bit Rate Setting (Unit: kbps) C0BTR Register Samplin Rate Value Ratio of Register Setting Value g point (Unit: kbps) C0BRP Set Value...
Page 491 CHAPTER 16 CAN CONTROLLER Table 16-24. Representative Examples of Baud Rate Settings (f = 16 MHz) (1/2) CANMOD Set Baud Division C0BRP Valid Bit Rate Setting (Unit: kbps) C0BTR Register Samplin Rate Value Ratio of Register Setting Value g point (Unit: kbps) C0BRP Set Value...
Page 492 CHAPTER 16 CAN CONTROLLER Table 16-24. Representative Examples of Baud Rate Settings (f = 16 MHz) (2/2) CANMOD Set Baud Division C0BRP Valid Bit Rate Setting (Unit: kbps) C0BTR Register Samplin Rate Value Ratio of Register Setting Value g point (Unit: kbps) C0BRP Set Value...
Page 493: Operation Of Can Controller
CHAPTER 16 CAN CONTROLLER 16.16 Operation of CAN Controller Remark m = 0 to 15 Figure 16-37. Initialization START CnGMCS register CnGMCTRL register (Set GOM = 1) CnBRP register, CnBTR register CnIE register CnMASK register Initialize message buffers CnCTRL register (set OPMODE) Remark OPMODE: Normal operation mode, normal operation mode with ABT, receive-only mode, single- shot mode, self-test mode...
Page 494 CHAPTER 16 CAN CONTROLLER Figure 16-38. Re-initialization START Clear OPMODE INIT mode? C0BRP register, C0BTR register C0IE register C0MASK register Initialize message buffers C0ERC and C0INFO register clear? Set CCERC bit Set C0CTRL register (Set OPMODE) Caution After setting the CAN module to the initialization mode, avoid setting the module to another operation mode immediately after.
Page 495 CHAPTER 16 CAN CONTROLLER Figure 16-39. Message Buffer Initialization START START RDY = 1? Clear RDY bit RDY = 0? C0MCONFm register C0MIDHm register, C0MIDLm register Transmit message buffer? C0MDLCm register Clear C0MDATAm register C0MCTRLm register Set RDY bit Cautions 1. Before a message buffer is initialized, the RDY bit must be cleared. 2.
Page 496 CHAPTER 16 CAN CONTROLLER Figure 16-40 shows the processing for a receive message buffer (MT [2:0] bits of C0MCONFm register = 001B to 101B). Figure 16-40. Message Buffer Redefinition START Clear VALID bit RDY = 1? Clear RDY bit RDY = 0? RSTAT = 0 or Note1 VALID = 1?
Page 497 CHAPTER 16 CAN CONTROLLER Figure 16-41 shows the processing for a transmit message buffer during transmission (MT [2:0] bits of C0MCONFm register = 000B). Figure 16-41. Message Buffer Redefinition during Transmission START Transmit abort process Clear RDY bit RDY = 0? Data frame Remote frame Data frame or remote frame?
Page 498 CHAPTER 16 CAN CONTROLLER Figure 16-42 shows the processing for a transmit message buffer (MT [2:0] bits of C0MCONFm register = 000B). Figure 16-42. Message Transmit Processing START TRQ = 0? Clear RDY bit RDY = 0? Data frame Remote frame Data frame or remote frame? Set C0MDATAxm register Set C0MDLCm register...
Page 499 CHAPTER 16 CAN CONTROLLER Figure 16-43 shows the processing for a transmit message buffer (MT [2:0] bits of C0MCONFm register = 000B). Figure 16-43. ABT Message Transmit Processing START ABTTRG = 0? Clear RDY bit RDY = 0? Set C0MDATAxm register Set C0MDLCm register Clear RTR bit of C0MCONFm register...
Page 500 CHAPTER 16 CAN CONTROLLER Figure 16-44. Transmission via Interrupt (Using C0LOPT register) START Transmit completion interrupt processing Read C0LOPT register Clear RDY bit RDY = 0? Data frame Remote frame Data frame or remote frame? Set C0MDATAxm register Set C0MDLCm register Set C0MDLCm register, Set RTR bit of C0MCONFm Clear RTR bit of C0MCONFm...
Page 501 CHAPTER 16 CAN CONTROLLER Figure 16-45. Transmit via Interrupt (Using C0TGPT register) START Transmit completion interrupt processing Read C0TGPT register TOVF = 1? Clear TOVF bit Clear RDY bit RDY = 0? Data frame Remote frame Data frame or remote frame? Set C0MDATAxm register Set C0MDLCm register Set C0MDLCm register...
Page 502 CHAPTER 16 CAN CONTROLLER Figure 16-46. Transmission via Software Polling START CINTS0 = 1? Clear CINTS0 bit Read C0TGPT register TOVF = 1? Clear TOVF bit Clear RDY bit RDY = 0? Data frame Remote frame Data frame or remote frame? Set C0MDATAxm register Set C0MDLCm register Set C0MDLCm register...
Page 503 CHAPTER 16 CAN CONTROLLER Figure 16-47. Transmission Abort Processing (Except Normal Operation Mode with ABT) START Clear TRQ bit Note Wait for 11 CAN data bits TSTAT = 0? Read C0LOPT register Message buffer to be aborted matches C0LOPT register? Transmit abort request was successful Transmission successful...
Page 504 CHAPTER 16 CAN CONTROLLER Figure 16-48. Transmission Abort Processing Except for ABT Transmission (Normal Operation Mode with ABT) START Clear ABTTRG bit ABTTRG = 0? Clear TRQ bit Note Wait for 11 CAN data bits TSTAT = 0? Read C0LOPT register Message buffer to be aborted matches C0LOPT register?
Page 505 CHAPTER 16 CAN CONTROLLER Figure 16-49 shows the processing not to skip resumption of transmitting a message that was stopped when transmission of an ABT message buffer was aborted. Figure 16-49. ABT Transmission Abort Processing (Normal Operation Mode with ABT) START TSTAT = 0? Clear ABTTRG bit...
Page 506 CHAPTER 16 CAN CONTROLLER Figure 16-50 shows the processing to skip resumption of transmitting a message that was stopped when transmission of an ABT message buffer was aborted. Figure 16-50. ABT Transmission Request Abort Processing (Normal Operation Mode with ABT) START Clear TRQ bit of message buffer undergoing transmission...
Page 507 CHAPTER 16 CAN CONTROLLER Figure 16-51. Reception via Interrupt (Using C0LIPT Register) START Generation of receive completion interrupt Read C0LIPT register Clear DN bit Read C0MDATAxm , C0MDLCm, C0MIDLm, and C0MIDHm registers DN = 0 Note MUC = 0 Note Check the MUC and DN bits using one read access. Remark Also check the MBON flag at the beginning and at the end of the interrupt routine, in order to check the access to the message buffers as well as reception history list registers, in case a pending sleep mode had been executed.
Page 508 CHAPTER 16 CAN CONTROLLER Figure 16-52. Reception via Interrupt (Using C0RGPT Register) START Generation of receive completion interrupt Read C0RGPT register ROVF = 1? Clear ROVF bit RHPM = 1? Clear DN bit Read C0MDATAxm , C0MDLCm, C0MIDLm, C0MIDHm registers DN = 0 Note MUC = 0...
Page 509 CHAPTER 16 CAN CONTROLLER Figure 16-53. Reception via Software Polling START CINTS1 = 1? Clear CINTS1 bit Read C0RGPT register ROVF = 1? Clear ROVF bit RHPM = 1? Clear DN bit Read C0MDATAxm , C0MDLCm, C0MIDLm, C0MIDHm registers DN = 0 Note MUC = 0 Correct data is read...
Page 510 CHAPTER 16 CAN CONTROLLER Figure 16-54. Setting CAN Sleep Mode/Stop Mode START (when PSMODE[1:0] = 00B) Set PSMODE0 bit PSMODE0 = 1? CAN sleep mode CAN sleep mode Set PSMODE1 bit PSMODE1 = 1? Request CAN sleep mode again? CAN stop mode CAN stop mode Clear OPMODE INIT mode?
Page 511 CHAPTER 16 CAN CONTROLLER Figure 16-55. Clear CAN Sleep/Stop Mode START CAN stop mode Clear PSMODE1 bit Released by CRxD at CAN sleep mode CPU NOT standby state Released by USER (VPCLK is still supplied) Released by CRxD at CPU standby state (VPCLK is stopped) After CRxD is dominant After CRxD is dominant...
Page 512 CHAPTER 16 CAN CONTROLLER Figure 16-56. Bus-Off Recovery (Expect Normal Operation Mode with ABT) START BOFF = 1? Note Clear all TRQ bits Set C0CTRL register (Clear OPMODE) Access to registers other than C0CTRL and C0GMCTRL registers Forced recovery from bus off? Set C0CTRL register Set CCERC bit (Set OPMODE)
Page 513 CHAPTER 16 CAN CONTROLLER Figure 16-57. Bus-Off Recovery (Normal Operation Mode with ABT) START BOFF = 1? Clear ABTTRG bit Note Clear all TRQ bits Set C0CTRL register (Clear OPMODE) Access to registers other than C0CTRL and C0GMCTRL registers Forced recovery from bus off? Set C0CTRL register Set CCERC bit (Set OPMODE)
Page 514 CHAPTER 16 CAN CONTROLLER Figure 16-58. Normal Shutdown Process START INIT mode Clear GOM bit GOM = 0? Shutdown successful GOM = 0, EFSD = 0 User’s Manual U17553EJ4V0UD...
Page 515 CHAPTER 16 CAN CONTROLLER Figure 16-59. Forced Shutdown Process START Set EFSD bit Must be a subseguent write Clear GOM bit GOM = 0? Shutdown successful GOM = 0, EFSD = 0 Caution Do not read- or write-access any registers by software between setting the EFSD bit and clearing the GOM bit.
Page 516 CHAPTER 16 CAN CONTROLLER Figure 16-60. Error Handling START Error interrupt CINTS2 = 1? Check CAN module state (read C0INFO register) Clear CINTS2 bit CINTS3 = 1? Check CAN protocol error state (read C0LEC register) Clear CINTS3 bit CINTS4 = 1? Clear CINTS4 bit User’s Manual U17553EJ4V0UD...
Page 517 CHAPTER 16 CAN CONTROLLER Figure 16-61. Setting CPU Standby (from CAN Sleep Mode) START Set PSMODE0 bit PSMODE0 = 1? CAN sleep mode Set CPU standby mode Caution Before the CPU is set in the CPU standby mode, please check the CAN sleep mode or not. However, after check of the CAN sleep mode, until the CPU is set in the CPU standby mode, the CAN sleep mode may be cancelled by wakeup from CAN bus.
Page 518 CHAPTER 16 CAN CONTROLLER Figure 16-62. Setting CPU Standby (from CAN Stop Mode) START Set PSMODE0 bit PSMODE0 = 1? Note Clear CINTS5 bit CAN sleep mode Set PSMODE1 bit PSMODE1 = 1? CAN stop mode Set CPU standby mode Note During wakeup interrupts Caution The CAN stop mode can only be released by writing 01B to the PSMODE[1:0] bit of the C0CTRL register and not by a change in the CAN bus state.
Page 519: Chapter 17 Interrupt Functions
CHAPTER 17 INTERRUPT FUNCTIONS 17.1 Interrupt Function Types The following two types of interrupt functions are used. (1) Maskable interrupts These interrupts undergo mask control. Maskable interrupts can be divided into a high interrupt priority group and a low interrupt priority group by setting the priority specification flag registers (PR0L, PR0H, PR1L, PR1H). Multiple interrupt servicing can be applied to low-priority interrupts when high-priority interrupts are generated.
Page 520 CHAPTER 17 INTERRUPT FUNCTIONS Table 17-1. Interrupt Source List (1/2) Interrupt Default Interrupt Source Internal/ Vector Basic Note 1 Type Priority External Table Configuration Name Trigger Note 2 Address Type Note 3 Maskable INTLVI Low-voltage detection Internal 0004H INTP0 Pin input edge detection External 0006H INTP1...
Page 521 CHAPTER 17 INTERRUPT FUNCTIONS Table 17-1. Interrupt Source List (2/2) Interrupt Default Interrupt Source Internal/ Vector Basic Note 1 Type Priority External Table Configuration Name Trigger Note 2 Address Type Maskable INTTMH1 Match between TMH1 and CMP01 Internal 0026H (when compare register is specified) INTTMH0 Match between TMH0 and CMP00 0028H...
Page 522 CHAPTER 17 INTERRUPT FUNCTIONS Figure 17-1. Basic Configuration of Interrupt Function (A) Internal maskable interrupt Internal bus Vector table Priority controller Interrupt address generator request Standby release signal (B) External maskable interrupt (INTP0 to INTP7) Internal bus External interrupt edge enable register (EGP, EGN) Vector table...
Page 523: Registers Controlling Interrupt Functions
CHAPTER 17 INTERRUPT FUNCTIONS 17.3 Registers Controlling Interrupt Functions The following 6 types of registers are used to control the interrupt functions. • Interrupt request flag register (IF0L, IF0H, IF1L, IF1H) • Interrupt mask flag register (MK0L, MK0H, MK1L, MK1H) •...
Page 524 CHAPTER 17 INTERRUPT FUNCTIONS Table 17-2. Flags Corresponding to Interrupt Request Sources Interrupt Interrupt Request Flag Interrupt Mask Flag Priority Specification Flag Request Register Register Register INTLVI LVIIF IF0L LVIMK MK0L LVIPR PR0L INTP0 PIF0 PMK0 PPR0 INTP1 PIF1 PMK1 PPR1 INTP2 PIF2...
Page 525 CHAPTER 17 INTERRUPT FUNCTIONS (1) Interrupt request flag registers (IF0L, IF0H, IF1L, IF1H) The interrupt request flags are set to 1 when the corresponding interrupt request is generated or an instruction is executed. They are cleared to 0 when an instruction is executed upon acknowledgment of an interrupt request or upon reset signal generation.
Page 526 CHAPTER 17 INTERRUPT FUNCTIONS Cautions 3. When manipulating a flag of the interrupt request flag register, use a 1-bit memory manipulation instruction (CLR1). When describing in C language, use a bit manipulation instruction such as “IF0L.0 = 0;” or “_asm(“clr1 IF0L, 0”);” because the compiled assembler must be a 1-bit memory manipulation instruction (CLR1).
Page 527 CHAPTER 17 INTERRUPT FUNCTIONS (2) Interrupt mask flag registers (MK0L, MK0H, MK1L, MK1H) The interrupt mask flags are used to enable/disable the corresponding maskable interrupt servicing. MK0L, MK0H, MK1L, and MK1H are set by a 1-bit or 8-bit memory manipulation instruction. When MK0L and MK0H, and MK1L and MK1H are combined to form 16-bit registers MK0 and MK1, they are set with a 16-bit memory manipulation instruction.
Page 528 CHAPTER 17 INTERRUPT FUNCTIONS (3) Priority specification flag registers (PR0L, PR0H, PR1L, PR1H) The priority specification flag registers are used to set the corresponding maskable interrupt priority order. PR0L, PR0H, PR1L, and PR1H are set by a 1-bit or 8-bit memory manipulation instruction. If PR0L and PR0H, and PR1L and PR1H are combined to form 16-bit registers PR0 and PR1, they are set with a 16-bit memory manipulation instruction.
Page 529 CHAPTER 17 INTERRUPT FUNCTIONS (4) External interrupt rising edge enable register (EGP), external interrupt falling edge enable register (EGN) These registers specify the valid edge for INTP0 to INTP7. EGP and EGN are set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears these registers to 00H.
Page 530 CHAPTER 17 INTERRUPT FUNCTIONS (5) Program status word (PSW) The program status word is a register used to hold the instruction execution result and the current status for an interrupt request. The IE flag that sets maskable interrupt enable/disable and the ISP flag that controls multiple interrupt servicing are mapped to the PSW.
Page 531: Interrupt Servicing Operations
CHAPTER 17 INTERRUPT FUNCTIONS 17.4 Interrupt Servicing Operations 17.4.1 Maskable interrupt acknowledgement A maskable interrupt becomes acknowledgeable when the interrupt request flag is set to 1 and the mask (MK) flag corresponding to that interrupt request is cleared to 0. A vectored interrupt request is acknowledged if interrupts are in the interrupt enabled state (when the IE flag is set to 1).
Page 532 CHAPTER 17 INTERRUPT FUNCTIONS Figure 17-7. Interrupt Request Acknowledgement Processing Algorithm Start ××IF = 1? Yes (interrupt request generation) ××MK = 0? Interrupt request held pending Yes (High priority) ××PR = 0? No (Low priority) Any high-priority Any high-priority interrupt request among those interrupt request among simultaneously generated with ××PR = 0?
Page 533: Software Interrupt Request Acknowledgement
CHAPTER 17 INTERRUPT FUNCTIONS Figure 17-8. Interrupt Request Acknowledgement Timing (Minimum Time) 6 clocks PSW and PC saved, Interrupt servicing CPU processing Instruction Instruction jump to interrupt program servicing ××IF (××PR = 1) 8 clocks ××IF (××PR = 0) 7 clocks Remark 1 clock: 1/f : CPU clock) Figure 17-9.
Page 534: Multiple Interrupt Servicing
CHAPTER 17 INTERRUPT FUNCTIONS 17.4.3 Multiple interrupt servicing Multiple interrupt servicing occurs when another interrupt request is acknowledged during execution of an interrupt. Multiple interrupt servicing does not occur unless the interrupt request acknowledgement enabled state is selected (IE = 1). When an interrupt request is acknowledged, interrupt request acknowledgement becomes disabled (IE = 0). Therefore, to enable multiple interrupt servicing, it is necessary to set (1) the IE flag with the EI instruction during interrupt servicing to enable interrupt acknowledgement.
Page 535 CHAPTER 17 INTERRUPT FUNCTIONS Figure 17-10. Examples of Multiple Interrupt Servicing (1/2) Example 1. Multiple interrupt servicing occurs twice Main processing INTxx servicing INTyy servicing INTzz servicing IE = 0 IE = 0 IE = 0 INTxx INTyy INTzz (PR = 1) (PR = 0) (PR = 0) RETI...
Page 536 CHAPTER 17 INTERRUPT FUNCTIONS Figure 17-10. Examples of Multiple Interrupt Servicing (2/2) Example 3. Multiple interrupt servicing does not occur because interrupts are not enabled Main processing INTxx servicing INTyy servicing IE = 0 INTyy (PR = 0) INTxx (PR = 0) RETI IE = 1 IE = 0...
Page 537: Interrupt Request Hold
CHAPTER 17 INTERRUPT FUNCTIONS 17.4.4 Interrupt request hold There are instructions where, even if an interrupt request is issued for them while another instruction is being executed, request acknowledgement is held pending until the end of execution of the next instruction. These instructions (interrupt request hold instructions) are listed below.
Page 538: Chapter 18 Standby Function
CHAPTER 18 STANDBY FUNCTION 18.1 Standby Function and Configuration 18.1.1 Standby function The standby function is designed to reduce the operating current of the system. The following two modes are available. (1) HALT mode HALT instruction execution sets the HALT mode. In the HALT mode, the CPU operation clock is stopped. If the high-speed system clock oscillator, internal high-speed oscillator, internal low-speed oscillator, or subsystem clock oscillator is operating before the HALT mode is set, oscillation of each clock continues.
Page 539 CHAPTER 18 STANDBY FUNCTION (1) Oscillation stabilization time counter status register (OSTC) This is the register that indicates the count status of the X1 clock oscillation stabilization time counter. When X1 clock oscillation starts with the internal high-speed oscillation clock or subsystem clock used as the CPU clock, the X1 clock oscillation stabilization time can be checked.
Page 540 CHAPTER 18 STANDBY FUNCTION (2) Oscillation stabilization time select register (OSTS) This register is used to select the X1 clock oscillation stabilization time when the STOP mode is released. When the X1 clock is selected as the CPU clock, the operation waits for the time set using OSTS after the STOP mode is released.
Page 541: Standby Function Operation
CHAPTER 18 STANDBY FUNCTION 18.2 Standby Function Operation 18.2.1 HALT mode (1) HALT mode The HALT mode is set by executing the HALT instruction. HALT mode can be set regardless of whether the CPU clock before the setting was the high-speed system clock, internal high-speed oscillation Clock, or subsystem clock.
Page 542 CHAPTER 18 STANDBY FUNCTION Table 18-1. Operating Statuses in HALT Mode (1/2) HALT Mode Setting When HALT Instruction Is Executed While CPU Is Operating on Main System Clock When CPU Is Operating on When CPU Is Operating on When CPU Is Operating on Internal High-Speed X1 Clock (f External Main System Clock...
Page 543 CHAPTER 18 STANDBY FUNCTION Table 18-1. Operating Statuses in HALT Mode (2/2) HALT Mode Setting When HALT Instruction Is Executed While CPU Is Operating on Subsystem Clock When CPU Is Operating on XT1 Clock (f When CPU Is Operating on External Subsystem Clock (f Item EXCLKS...
Page 544 CHAPTER 18 STANDBY FUNCTION Remark f Internal high-speed oscillation clock X1 clock External main system clock EXCLK XT1 clock : External subsystem clock EXCLKS Internal low-speed oscillation clock User’s Manual U17553EJ4V0UD...
Page 545 CHAPTER 18 STANDBY FUNCTION (2) HALT mode release The HALT mode can be released by the following two sources. (a) Release by unmasked interrupt request When an unmasked interrupt request is generated, the HALT mode is released. If interrupt acknowledgement is enabled, vectored interrupt servicing is carried out. If interrupt acknowledgement is disabled, the next address instruction is executed.
Page 546 CHAPTER 18 STANDBY FUNCTION (b) Release by reset signal generation When the reset signal is generated, HALT mode is released, and then, as in the case with a normal reset operation, the program is executed after branching to the reset vector address. Figure 18-4.
Page 547: Stop Mode
CHAPTER 18 STANDBY FUNCTION Table 18-2. Operation in Response to Interrupt Request in HALT Mode Release Source MK×× PR×× Operation × Maskable interrupt Next address request instruction execution × Interrupt servicing execution Next address instruction execution × Interrupt servicing execution ×...
Page 548 CHAPTER 18 STANDBY FUNCTION Table 18-3. Operating Statuses in STOP Mode STOP Mode Setting When STOP Instruction Is Executed While CPU Is Operating on Main System Clock When CPU Is Operating on When CPU Is Operating on When CPU Is Operating on Internal High-Speed X1 Clock (f External Main System Clock...
Page 549 CHAPTER 18 STANDBY FUNCTION Remark f Internal high-speed oscillation clock X1 clock External main system clock EXCLK XT1 clock : External subsystem clock EXCLKS Internal low-speed oscillation clock Cautions 1. To use the peripheral hardware that stops operation in the STOP mode, and the peripheral hardware for which the clock that stops oscillating in the STOP mode after the STOP mode is released, restart the peripheral hardware.
Page 550 CHAPTER 18 STANDBY FUNCTION (2) STOP mode release Figure 18-5. Operation Timing When STOP Mode Is Released (When Unmasked Interrupt Request Is Generated) STOP mode release STOP mode High-speed system clock (X1 oscillation) High-speed system clock (external clock input) Internal high-speed oscillation clock Wait for oscillation accuracy μ...
Page 551 CHAPTER 18 STANDBY FUNCTION (a) Release by unmasked interrupt request When an unmasked interrupt request is generated, the STOP mode is released. After the oscillation stabilization time has elapsed, if interrupt acknowledgment is enabled, vectored interrupt servicing is carried out. If interrupt acknowledgment is disabled, the next address instruction is executed. Figure 18-6.
Page 552 CHAPTER 18 STANDBY FUNCTION Figure 18-6. STOP Mode Release by Interrupt Request Generation (2/2) (2) When high-speed system clock (external clock input) is used as CPU clock (2/2) • When AMPH = 0 Interrupt request STOP instruction Standby release signal Normal operation Normal operation (high-speed...
Page 553 CHAPTER 18 STANDBY FUNCTION (b) Release by reset signal generation When the reset signal is generated, STOP mode is released, and then, as in the case with a normal reset operation, the program is executed after branching to the reset vector address. Figure 18-7.
Page 554: Chapter 19 Reset Function
CHAPTER 19 RESET FUNCTION The following four operations are available to generate a reset signal. (1) External reset input via RESET pin (2) Internal reset by watchdog timer program loop detection (3) Internal reset by comparison of supply voltage and detection voltage of power-on-clear (POC) circuit (4) Internal reset by comparison of supply voltage and detection voltage of low-power-supply detector (LVI) External and internal resets have no functional differences.
Page 555 Figure 19-1. Block Diagram of Reset Function Internal bus Reset control flag register (RESF) WDTRF LVIRF Watchdog timer reset signal Clear Clear Reset signal to LVIM/LVIS register RESET Power-on-clear circuit reset signal Reset signal Low-voltage detector reset signal Caution An LVI circuit internal reset does not reset the LVI circuit. Remarks 1.
Page 556 CHAPTER 19 RESET FUNCTION Figure 19-2. Timing of Reset by RESET Input Wait for oscillation accuracy stabilization μ (86 to 361 s) Internal high-speed oscillation clock Starting X1 oscillation is specified by software. High-speed system clock (when X1 oscillation is selected) Reset processing Normal operation...
Page 557 CHAPTER 19 RESET FUNCTION Figure 19-4. Timing of Reset in STOP Mode by RESET Input Wait for oscillation accuracy stabilization STOP instruction execution μ (86 to 361 s) Internal high-speed oscillation clock Starting X1 oscillation is specified by software. High-speed system clock (when X1 oscillation is selected) Reset processing...
Page 558 CHAPTER 19 RESET FUNCTION Table 19-1. Operation Statuses During Reset Period Item During Reset Period System clock Clock supply to the CPU is stopped. Main system clock Operation stopped Operation stopped (pin is I/O port mode) Clock input invalid (pin is I/O port mode) EXCLK Subsystem clock Operation stopped (pin is I/O port mode)
Page 559 The initial values of the internal memory size switching register (IMS) and internal expansion RAM size switching register (IXS) after a reset release are constant (IMS = CFH, IXS = 0CH) in all the 78K0/FF2 products, regardless of the internal memory capacity. Therefore, after a reset is released, be sure to set the following values for each product.
Page 560 CHAPTER 19 RESET FUNCTION Table 19-2. Hardware Statuses After Reset Acknowledgment (2/3) Hardware Status After Reset Note 1 Acknowledgment 8-bit timer/event counters Timer counters 50, 51 (TM50, TM51) 50, 51 Compare registers 50, 51 (CR50, CR51) Timer clock selection registers 50, 51 (TCL50, TCL51) Mode control registers 50, 51 (TMC50, TMC51) 8-bit timers H0, H1 Compare registers 00, 10, 01, 11 (CMP00, CMP10, CMP01, CMP11)
Page 561 CHAPTER 19 RESET FUNCTION Table 19-2. Hardware Statuses After Reset Acknowledgment (3/3) Hardware Status After Reset Note 1 Acknowledgment Multiplier/divider Remainder data register 0 (SDR0) 0000H Multiplication/division data register A0 (MDA0H, MDA0L) 0000H Multiplication/division data register B0 (MDB0) 0000H Multiplier/divider control register 0 (DMUC0) Note2 Reset function Reset control flag register (RESF)
Page 562: Register For Confirming Reset Source
CHAPTER 19 RESET FUNCTION 19.1 Register for Confirming Reset Source Many internal reset generation sources exist in the 78K0/FF2. The reset control flag register (RESF) is used to store which source has generated the reset request. RESF can be read by an 8-bit memory manipulation instruction.
Page 563: Chapter 20 Multiplier/Divider
CHAPTER 20 MULTIPLIER/DIVIDER 20.1 Functions of Multiplier/Divider The multiplier/divider has the following functions. • 16 bits × 16 bits = 32 bits (multiplication) • 32 bits ÷ 16 bits = 32 bits, 16-bit remainder (division) 20.2 Configuration of Multiplier/Divider The multiplier/divider includes the following hardware. Table 20-1.
Page 564 Figure 20-1. Block Diagram of Multiplier/Divider Internal bus Multiplier/divider control register 0 (DMUC0) Multiplication/division data register B0 Remainder data register 0 Multiplication/division data register A0 DMUSEL0 DMUE (MDB0 (MDB0H + MDB0L) (SDR0 (SDR0H + SDR0L) (MDA0H (MDA0HH + MDA0HL) + MDA0L (MDA0LH + MDA0LL) ) Start MDA000 INTDMU...
Page 565 CHAPTER 20 MULTIPLIER/DIVIDER (1) Remainder data register 0 (SDR0) SDR0 is a 16-bit register that stores a remainder. This register stores 0 in the multiplication mode and the remainder of an operation result in the division mode. SDR0 can be read by an 8-bit or 16-bit memory manipulation instruction. Reset signal generation clears SDR0 to 0000H.
Page 566 CHAPTER 20 MULTIPLIER/DIVIDER The functions of MDA0 when an operation is executed are shown in the table below. Table 20-2. Functions of MDA0 During Operation Execution DMUSEL0 Operation Mode Setting Operation Result Division mode Dividend Division result (quotient) Multiplication mode Higher 16 bits: 0, Lower 16 Multiplication result bits: Multiplier A...
Page 567: Register Controlling Multiplier/Divider
CHAPTER 20 MULTIPLIER/DIVIDER 20.3 Register Controlling Multiplier/Divider The multiplier/divider is controlled by multiplier/divider control register 0 (DMUC0). (1) Multiplier/divider control register 0 (DMUC0) DMUC0 is an 8-bit register that controls the operation of the multiplier/divider. DMUC0 can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears DMUC0 to 00H.
Page 568: Operations Of Multiplier/Divider
CHAPTER 20 MULTIPLIER/DIVIDER 20.4 Operations of Multiplier/Divider 20.4.1 Multiplication operation • Initial setting 1. Set operation data to multiplication/division data register A0L (MDA0L) and multiplication/division data register B0 (MDB0). 2. Set bits 0 (DMUSEL0) and 7 (DMUE) of multiplier/divider control register 0 (DMUC0) to 1. Operation will start. •...
Page 569 Figure 20-6. Timing Chart of Multiplication Operation (00DAH × 0093H) Operation clock DMUE DMUSEL0 Internal clock Counter XXXX 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 SDR0 0000 0049 0024 005B 0077 003B 0067...
Page 570: Division Operation
CHAPTER 20 MULTIPLIER/DIVIDER 20.4.2 Division operation • Initial setting 1. Set operation data to multiplication/division data register A0 (MDA0L and MDA0H) and multiplication/division data register B0 (MDB0). 2. Set bits 0 (DMUSEL0) and 7 (DMUE) of multiplier/divider control register 0 (DMUC0) to 0 and 1, respectively. Operation will start.
Page 571 Figure 20-7. Timing Chart of Division Operation (DCBA2586H ÷ 0018H) Operation clock DMUE DMUSEL0 “0” Internal clock 1B 1C 1D 1E Counter XXXX 0000 0001 0003 0006 000D 0003 0007 000E 0004 000B 0016 0014 0010 0008 0011 000B 0016 SDR0 B974 72E8...
Page 572: Chapter 21 Power-On-Clear Circuit
Caution If an internal reset signal is generated in the POC circuit, the reset control flag register (RESF) is cleared to 00H. Remark The 78K0/FF2 incorporates multiple hardware functions that generate an internal reset signal. A flag that indicates the reset cause is located in the reset control flag register (RESF) for when an internal reset signal is generated by the watchdog timer (WDT) or low-voltage-detector (LVI).
Page 573: Configuration Of Power-On-Clear Circuit
CHAPTER 21 POWER-ON-CLEAR CIRCUIT 21.2 Configuration of Power-on-Clear Circuit The block diagram of the power-on-clear circuit is shown in Figure 21-1. Figure 21-1. Block Diagram of Power-on-Clear Circuit Internal reset signal − Reference voltage source 21.3 Operation of Power-on-Clear Circuit (1) In 1.59 V POC mode (option byte: LVISTART = 0) •...
Page 574 CHAPTER 21 POWER-ON-CLEAR CIRCUIT Figure 21-2. Timing of Generation of Internal Reset Signal by Power-on-Clear Circuit and Low-Voltage Detector (1/2) (1) In 1.59 V POC mode (option byte: LVISTART = 0) Set LVI to be Set LVI to be Set LVI to be used for reset used for interrupt used for reset...
Page 575 CHAPTER 21 POWER-ON-CLEAR CIRCUIT Figure 21-2. Timing of Generation of Internal Reset Signal by Power-on-Clear Circuit and Low-Voltage Detector (2/2) (2) In 2.7 V / 1.59V POC mode (option byte: LVISTART = 1) Set LVI to be Set LVI to be Set LVI to be used for reset used for interrupt...
Page 576: Cautions For Power-On-Clear Circuit
CHAPTER 21 POWER-ON-CLEAR CIRCUIT 21.4 Cautions for Power-on-Clear Circuit In a system where the supply voltage (V ) fluctuates for a certain period in the vicinity of the POC detection voltage (V ), the system may be repeatedly reset and released from the reset status. In this case, the time from release of reset to the start of the operation of the microcontroller can be arbitrarily set by taking the following action.
Page 577 CHAPTER 21 POWER-ON-CLEAR CIRCUIT Figure 21-3. Example of Software Processing After Release of Reset (2/2) • Checking reset cause Check reset cause WDTRF of RESF register = 1? Reset processing by watchdog timer LVIRF of RESF register = 1? Reset processing by low-voltage detector Power-on-clear/external reset generated...
Page 578: Chapter 22 Low-Voltage Detector
CHAPTER 22 LOW-VOLTAGE DETECTOR 22.1 Functions of Low-Voltage Detector The low-voltage detector (LVI) has the following functions. • The LVI circuit compares the supply voltage (V ) with the detection voltage (V ) or the input voltage from an external input pin (EXLVI) with the detection voltage (V = 1.21 V (TYP.): fixed), and generates an internal EXLVI reset or internal interrupt signal.
Page 579: Configuration Of Low-Voltage Detector
CHAPTER 22 LOW-VOLTAGE DETECTOR 22.2 Configuration of Low-Voltage Detector The block diagram of the low-voltage detector is shown in Figure 22-1. Figure 22-1. Block Diagram of Low-Voltage Detector N-ch Internal reset signal EXLVI/P120/ INTP0 − INTLVI Reference voltage source Low-voltage detection level Low-voltage detection register selection register (LVIS) (LVIM)
Page 580 CHAPTER 22 LOW-VOLTAGE DETECTOR (1) Low-voltage detection register (LVIM) This register sets low-voltage detection and the operation mode. This register can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears LVIM to 00H. Figure 22-2. Format of Low-Voltage Detection Register (LVIM) Note 1 Address: FFBEH After reset: 00H...
Page 581 CHAPTER 22 LOW-VOLTAGE DETECTOR Cautions 1. To stop LVI, follow either of the procedures below. • When using 8-bit memory manipulation instruction: Write 00H to LVIM. • When using 1-bit memory manipulation instruction: Clear LVION to 0. 2. Input voltage from external input pin (EXLVI) must be EXLVI < V (2) Low-voltage detection level selection register (LVIS) This register selects the low-voltage detection level.
Page 582: Operation Of Low-Voltage Detector
CHAPTER 22 LOW-VOLTAGE DETECTOR (3) Port mode register 12 (PM12) When using the P120/EXLVI/INTP0 pin for external low-voltage detection potential input, set PM120 to 1. At this time, the output latch of P120 may be 0 or 1. PM12 can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation sets PM12 to FFH.
Page 583: When Used As Reset
CHAPTER 22 LOW-VOLTAGE DETECTOR 22.4.1 When used as reset (1) When detecting level of supply voltage (V • When starting operation <1> Mask the LVI interrupt (LVIMK = 1). <2> Clear bit 2 (LVISEL) of the low-voltage detection register (LVIM) to 0 (detects level of supply voltage )) (default value).
Page 584 CHAPTER 22 LOW-VOLTAGE DETECTOR Figure 22-5. Timing of Low-Voltage Detector Internal Reset Signal Generation (Detects Level of Supply Voltage (V )) (1/2) (1) In 1.59 V POC mode setup (option byte: LVISTART = 0) Supply voltage (V = 1.59 V (TYP.) Time LVIMK flag Note1...
Page 585 CHAPTER 22 LOW-VOLTAGE DETECTOR Figure 22-5. Timing of Low-Voltage Detector Internal Reset Signal Generation (Detects Level of Supply Voltage (V )) (2/2) (2) In 2.7/1.59 V POC mode setup (option byte: LVISTART = 1) Supply voltage (V 2.7 V (TYP.) = 1.59 V (TYP.) Time LVIMK flag...
Page 586 CHAPTER 22 LOW-VOLTAGE DETECTOR (2) When detecting level of input voltage from external input pin (EXLVI) • When starting operation <1> Mask the LVI interrupt (LVIMK = 1). <2> Set bit 2 (LVISEL) of the low-voltage detection register (LVIM) to 1 (detects level of input voltage from external input pin (EXLVI)).
Page 587 CHAPTER 22 LOW-VOLTAGE DETECTOR Figure 22-6. Timing of Low-Voltage Detector Internal Reset Signal Generation (Detects Level of Input Voltage from External Input Pin (EXLVI)) Input voltage from external input pin (EXLVI) LVI detection voltage EXLVI Time LVIMK flag Note 1 (set by software) <1>...
Page 588: When Used As Interrupt
CHAPTER 22 LOW-VOLTAGE DETECTOR 22.4.2 When used as interrupt (1) When detecting level of supply voltage (V • When starting operation <1> Mask the LVI interrupt (LVIMK = 1). <2> Clear bit 2 (LVISEL) of the low-voltage detection register (LVIM) to 0 (detects level of supply voltage )) (default value).
Page 589 CHAPTER 22 LOW-VOLTAGE DETECTOR Figure 22-7. Timing of Low-Voltage Detector Interrupt Signal Generation (Detects Level of Supply Voltage (V )) (1/2) (1) In 1.59 V POC mode setup (option byte: LVISTART = 0) Supply voltage (V = 1.59 V (TYP.) Time LVIMK flag (set by software)
Page 590 CHAPTER 22 LOW-VOLTAGE DETECTOR Figure 22-7. Timing of Low-Voltage Detector Interrupt Signal Generation (Detects Level of Supply Voltage (V )) (2/2) (2) In 2.7/1.59 V POC mode setup (option byte: LVISTART = 1) Supply voltage (V 2.7 V(TYP.) = 1.59 V (TYP.) Time LVIMK flag (set by software)
Page 591 CHAPTER 22 LOW-VOLTAGE DETECTOR (2) When detecting level of input voltage from external input pin (EXLVI) • When starting operation <1> Mask the LVI interrupt (LVIMK = 1). <2> Set bit 2 (LVISEL) of the low-voltage detection register (LVIM) to 1 (detects level of input voltage from external input pin (EXLVI)).
Page 592 CHAPTER 22 LOW-VOLTAGE DETECTOR Figure 22-8. Timing of Low-Voltage Detector Interrupt Signal Generation (Detects Level of Input Voltage from External Input Pin (EXLVI)) Input voltage from external input pin (EXLVI) EXLVI Time LVIMK flag (set by software) <1> Note 1 <7>...
Page 593: Cautions For Low-Voltage Detector
CHAPTER 22 LOW-VOLTAGE DETECTOR 22.5 Cautions for Low-Voltage Detector In a system where the supply voltage (V ) fluctuates for a certain period in the vicinity of the LVI detection voltage ), the operation is as follows depending on how the low-voltage detector is used. (1) When used as reset The system may be repeatedly reset and released from the reset status.
Page 594 CHAPTER 22 LOW-VOLTAGE DETECTOR Figure 22-9. Example of Software Processing After Reset Release (1/2) • If supply voltage fluctuation is 50 ms or less in vicinity of LVI detection voltage Reset Note Check the reset source Initialization Initialize the port. processing <1>...
Page 595 CHAPTER 22 LOW-VOLTAGE DETECTOR Figure 22-9. Example of Software Processing After Reset Release (2/2) • Checking reset cause Check reset cause WDTRF of RESF register = 1? Reset processing by watchdog timer LVIRF of RESF register = 1? Power-on-clear/external reset generated Reset processing by low-voltage detector User’s Manual U17553EJ4V0UD...
Page 596: Chapter 23 Option Byte
23.1 Functions of Option Bytes The flash memory at 0080H to 0084H of the 78K0/FF2 is an option byte area. When power is turned on or when the device is restarted from the reset status, the device automatically references the option bytes and sets specified functions.
Page 597 CHAPTER 23 OPTION BYTE (3) 0084H/1084H On-chip debug operation control • Disabling on-chip debug operation • Enabling on-chip debug operation and erasing data of the flash memory in case authentication of the on- chip debug security ID fails • Enabling on-chip debug operation and not erasing data of the flash memory even in case authentication of the on-chip debug security ID fails Caution To use the on-chip debug function, set 02H or 03H to 0084H.
Page 598: Format Of Option Byte
CHAPTER 23 OPTION BYTE 23.2 Format of Option Byte The format of the option byte is shown below. Figure 23-1. Format of Option Byte (1/2) Note Address: 0080H/1080H WINDOW1 WINDOW0 WDTON WDCS2 WDCS1 WDCS0 LSROSC WINDOW1 WINDOW0 Watchdog timer window open period 100% WDTON Operation control of watchdog timer counter/illegal access detection...
Page 599 CHAPTER 23 OPTION BYTE Figure 23-1. Format of Option Byte (2/2) Notes 1, 2 Address: 0081H/1081H LVISTART LVISTART POC mode selection 1.59 V POC mode (default) 2.7 V/1.59 V POC mode Notes 1. LVISTART can only be written by using a dedicated flash memory programmer. It cannot be set during self-programming or boot swap operation during self-programming (at this time, 1.59 V POC mode (default) is set).
Page 600 CHAPTER 23 OPTION BYTE Here is an example of description of the software for setting the option bytes. CSEG AT 0080H OPTION: DB ; Enables watchdog timer operation (illegal access detection operation), ; Window open period of watchdog timer: 50%, ;...
Page 601: Chapter 24 Flash Memory
CHAPTER 24 FLASH MEMORY The 78K0/FF2 incorporates the flash memory to which a program can be written, erased, and overwritten while mounted on the board. 24.1 Internal Memory Size Switching Register The internal memory capacity can be selected using the internal memory size switching register (IMS).
Page 602: Internal Expansion Ram Size Switching Register
Caution To set memory size, set IMS and then IXS. Set memory size so that the internal ROM area and internal expansion RAM area do not overlap. Table 24-2. Internal Expansion RAM Size Switching Register Settings Flash Memory Versions (78K0/FF2) IXS Setting μ...
Page 603: Writing With Flash Memory Programmer
Data can be written to the flash memory on-board or off-board, by using a dedicated flash memory programmer. (1) On-board programming The contents of the flash memory can be rewritten after the 78K0/FF2 has been mounted on the target system. The connectors that connect the dedicated flash memory programmer must be mounted on the target system.
Page 604 CHAPTER 24 FLASH MEMORY Examples of the recommended connection when using the adapter for flash memory writing are shown below. Figure 24-3. Example of Wiring Adapter for Flash Memory Writing in 3-Wire Serial I/O (CSI10) Mode (2.3 to 5.5 V) 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 VDD2...
Page 605 CHAPTER 24 FLASH MEMORY Figure 24-4. Example of Wiring Adapter for Flash Memory Writing in UART (UART60) Mode (2.3 to 5.5 V) 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 Note 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 VDD2...
Page 606: Programming Environment
CHAPTER 24 FLASH MEMORY 24.4 Programming Environment The environment required for writing a program to the flash memory of the 78K0/FF2 is illustrated below. Figure 24-5. Environment for Writing Program to Flash Memory FLMD0 RS-232C Axxxx Bxxxxx Cxxxxxx STATVE PG-FP4...
Page 607 When using the clock output from the PG-FPL3 or FP-LITE3, connect CLK to X1/P121 (pin 15), and connect its inverted signal to X2/EXCLK/P122 (pin 14). The dedicated flash memory programmer generates the following signals for the 78K0/FF2. For details, refer to the user’s manual for the PG-FP4, FL-PR4, PG-FPL3, or FP-LITE3.
Page 608: Connection Of Pins On Board
In the normal operation mode, 0 V is input to the FLMD0 pin. In the flash memory programming mode, the V write voltage is supplied to the FLMD0 pin. An FLMD0 pin connection example is shown below. Figure 24-8. FLMD0 Pin Connection Example 78K0/FF2 Dedicated flash memory programmer connection pin FLMD0 10 k Ω...
Page 609 Dedicated flash memory programmer connection pin Other device Input pin If the signal output by the 78K0/FF2 in the flash memory programming mode affects the other device, isolate the signal of the other device. 78K0/FF2 Dedicated flash memory programmer connection pin...
Page 610: Reset Pin
If the reset signal is input from the user system while the flash memory programming mode is set, the flash memory will not be correctly programmed. Do not input any signal other than the reset signal of the dedicated flash memory programmer. Figure 24-11. Signal Collision (RESET Pin) 78K0/FF2 Dedicated flash memory Signal collision programmer connection signal...
Page 611: Power Supply
CHAPTER 24 FLASH MEMORY 24.6.7 Power supply To use the supply voltage output of the flash memory programmer, connect the V pin to V of the flash memory programmer, and the V pin to GND of the flash memory programmer. To use the on-board supply voltage, connect in compliance with the normal operation mode.
Page 612: Programming Method
End? 24.7.2 Flash memory programming mode To rewrite the contents of the flash memory by using the dedicated flash memory programmer, set the 78K0/FF2 in the flash memory programming mode. To set the mode, set the FLMD0 pin to V and clear the reset signal.
Page 613: Selecting Communication Mode
24.7.3 Selecting communication mode In the 78K0/FF2, a communication mode is selected by inputting pulses (up to 8 pulses) to the FLMD0 pin after the dedicated flash memory programming mode is entered. These FLMD0 pulses are generated by the flash memory programmer.
Page 614: Communication Commands
The 78K0/FF2 communicates with the dedicated flash memory programmer by using commands. The signals sent from the flash memory programmer to the 78K0/FF2 are called commands, and the signals sent from the 78K0/FF2 to the dedicated flash memory programmer are called response.
Page 615: Security Settings
CHAPTER 24 FLASH MEMORY 24.8 Security Settings The 78K0/FF2 supports a security function that prohibits rewriting the user program written to the internal flash memory, so that the program cannot be changed by an unauthorized person. The operations shown below can be performed using the security set command. The security setting is valid when the programming mode is set next.
Page 616 CHAPTER 24 FLASH MEMORY Table 24-10. Relationship Between Enabling Security Function and Command (1) During on-board/off-board programming Valid Security Executed Command Batch Erase (Chip Erase) Block Erase Write Note Prohibition of batch erase (chip erase) Cannot be erased in batch Blocks cannot be Can be performed erased.
Page 617: Processing Time For Each Command When Pg-Fp4 Is Used (Reference)
CHAPTER 24 FLASH MEMORY 24.9 Processing Time for Each Command When PG-FP4 Is Used (Reference) The following table shows the processing time for each command (reference) when the PG-FP4 is used as a dedicated flash memory programmer. <R> Table 24-12. Processing Time for Each Command When PG-FP4 Is Used (Reference) •...
Page 618: Flash Memory Programming By Self-Programming
24.10 Flash Memory Programming by Self-Programming The 78K0/FF2 supports a self-programming function that can be used to rewrite the flash memory via a user program. Because this function allows a user application to rewrite the flash memory by using the 78K0/FF2 self- programming library, it can be used to upgrade the program in the field.
Page 619 CHAPTER 24 FLASH MEMORY Cautions 6. Allocate the entry program for self-programming in the common area of 0000H to 7FFFH. μ Figure 24-15. Operation Mode and Memory Map for Self-Programming ( PD78F0893) F F F F H F F F F H F F 0 0 H F F 0 0 H F E F F H...
Page 620 CHAPTER 24 FLASH MEMORY The following figure illustrates a flow of rewriting the flash memory by using a self programming sample library. Figure 24-16. Flow of Self-Programming (Rewriting Flash Memory) Start of self programming FLMD0 pin Low level → High level FlashStart Setting operating environment FlashEnv...
Page 621 CHAPTER 24 FLASH MEMORY The following table shows the processing time and interrupt response time for the self programming sample library. Table 24-14. Processing Time and Interrupt Response Time for Self Programming Sample Library (1/4) (1) When internal high-speed oscillation clock is used and entry RAM is located outside short direct addressing range μ...
Page 622 CHAPTER 24 FLASH MEMORY Table 24-14. Processing Time and Interrupt Response Time for Self Programming Sample Library (2/4) (2) When internal high-speed oscillation clock is used and entry RAM is located in short direct addressing range (FE20H) μ μ Library Name Processing Time ( Interrupt Response Time ( Normal Model of C Compiler...
Page 623 CHAPTER 24 FLASH MEMORY Table 24-14. Processing Time and Interrupt Response Time for Self Programming Sample Library (3/4) (3) When high-speed system clock (X1 oscillation or external clock input) is used and entry RAM is located outside short direct addressing range μ...
Page 624 CHAPTER 24 FLASH MEMORY Table 24-14. Processing Time and Interrupt Response Time for Self Programming Sample Library (4/4) (4) When high-speed system clock (X1 oscillation or external clock input) is used and entry RAM is located in short direct addressing range (FE20H) μ...
Page 625: Registers Used For Self-Programming Function
CHAPTER 24 FLASH MEMORY 24.10.1 Registers used for self-programming function The following three registers are used for the self-programming function. • Flash-programming mode control register (FLPMC) • Flash protect command register (PFCMD) • Flash status register (PFS) (1) Flash-programming mode control register (FLPMC) This register is used to enable or disable writing or erasing of the flash memory and to set the operation mode during self-programming.
Page 626 CHAPTER 24 FLASH MEMORY Figure 24-17. Format of Flash-Programming Mode Control Register (FLPMC) Note 1 Note 2 Address: FFC4H After reset: 0×H Symbol FLPMC FWEDIS FWEPR FLSPM1 FLSPM0 FWEDIS Control of flash memory writing/erasing Note 3 Writing/erasing enabled Writing/erasing disabled FWEPR Status of FLMD0 pin Low level...
Page 627 CHAPTER 24 FLASH MEMORY (2) Flash protect command register (PFCMD) If the application system stops inadvertently due to malfunction caused by noise or program hang-up, an operation to write the flash programming mode control register (FLPMC) may have a serious effect on the system. PFCMD is used to protect FLPMC from being written, so that the application system does not stop inadvertently.
Page 628 CHAPTER 24 FLASH MEMORY The operating conditions of the FPRERR flag are as follows. <Setting conditions> • If PFCMD is written when the store instruction operation recently performed on a peripheral register is not to write a specific value (A5H) to PFCMD •...
Page 629: Boot Swap Function
1 in advance. When the program has been correctly written to boot cluster 1, swap this boot cluster 1 and boot cluster 0 by using the set information function of the firmware of the 78K0/FF2, so that boot cluster 1 is used as a boot area.
Page 630 CHAPTER 24 FLASH MEMORY Figure 24-21. Example of Executing Boot Swapping Block number Erasing block 4 Erasing block 5 Erasing block 6 Erasing block 7 Program Program Program Program Boot Program Program Program cluster 1 Program Program Program 1 0 0 0 H Boot program Boot program Boot program...
Page 631: Chapter 25 On-Chip Debug Function
CHAPTER 25 ON-CHIP DEBUG FUNCTION 25.1 Outline of Functions The 78K0/FF2 uses the V , FLMD0, RESET, X1 (or P31), X2 (or P32), and V pins to communicate with the host machine via an on-chip debug emulator (QB-78K0MINI). Whether X1 and P31, or X2 and P32 are used can be selected.
Page 632: Connection With Minicube
CHAPTER 25 ON-CHIP DEBUG FUNCTION 25.2 Connection with MINICUBE In order to connect QB-78K0MINI, it is necessary to mount the connector for emulator connection, and the circuit for connection on a target system. The connector for OCD (a two-row 2.54 pitch type connector, with reverse-insertion blocker) is described below. •...
Page 633: Connection Circuit Examples
CHAPTER 25 ON-CHIP DEBUG FUNCTION 25.3 Connection Circuit Examples The following are examples of circuits required when connecting the QB-78K0MINI to the target system. Figure 25-2. Connection Circuit Example (When QB-78K0MINI Is Not Used) Target device QB-78K0MINI target connector Shorted by jumper FLMD0 FLMD0 Note...
Page 634 CHAPTER 25 ON-CHIP DEBUG FUNCTION Figure 25-4. Connection Circuit Example (When Using QB-78K0MINI: Ports 31 and 32 Are Used) Target device QB-78K0MINI target connector FLMD0 FLMD0 Note Target reset RESET IN RESET RESET OUT Note Note Make pull-down resistor 470 Ω or more (10 kΩ: recommended). Connect the FLMD0 pin as follows when performing self programming by means of on-chip debugging.
Page 635: On-Chip Debug Security Id
CHAPTER 25 ON-CHIP DEBUG FUNCTION 25.4 On-Chip Debug Security ID The 78K0/FF2 has an on-chip debug operation control flag in the flash memory at 0084H (see CHAPTER 23 OPTION BYTE) and an on-chip debug security ID setting area at 0085H to 008EH.
Page 636: Chapter 26 Instruction Set
CHAPTER 26 INSTRUCTION SET This chapter lists each instruction set of 78K0/FF2 in table form. For details of each operation and operation code, refer to the separate document 78K/0 Series Instructions User’s Manual (U12326E). 26.1 Conventions Used in Operation List 26.1.1 Operand identifiers and specification methods...
Page 637: Description Of Operation Column
CHAPTER 26 INSTRUCTION SET 26.1.2 Description of operation column A register; 8-bit accumulator X register B register C register D register E register H register L register AX register pair; 16-bit accumulator BC register pair DE register pair HL register pair Program counter Stack pointer PSW:...
Page 638: Operation List
CHAPTER 26 INSTRUCTION SET 26.2 Operation List Clocks Flag Instruction Mnemonic Operands Bytes Operation Group Z AC CY Note 1 Note 2 r ← byte − 8-bit data r, #byte transfer (saddr) ← byte saddr, #byte − sfr ← byte sfr, #byte −...
Page 639 CHAPTER 26 INSTRUCTION SET Clocks Flag Instruction Mnemonic Operands Bytes Operation Group Z AC CY Note 1 Note 2 − rp ← word 16-bit data MOVW rp, #word transfer (saddrp) ← word saddrp, #word − sfrp ← word sfrp, #word AX ←...
Page 640 CHAPTER 26 INSTRUCTION SET Clocks Flag Instruction Mnemonic Operands Bytes Operation Group Z AC CY Note 1 Note 2 − A, CY ← A − byte × × × 8-bit A, #byte operation (saddr), CY ← (saddr) − byte × ×...
Page 641 CHAPTER 26 INSTRUCTION SET Clocks Flag Instruction Mnemonic Operands Bytes Operation Group Z AC CY Note 1 Note 2 − A ← A ∨ byte × 8-bit A, #byte operation (saddr) ← (saddr) ∨ byte × saddr, #byte − A ← A ∨ r ×...
Page 642 CHAPTER 26 INSTRUCTION SET Clocks Flag Instruction Mnemonic Operands Bytes Operation Group Z AC CY Note 1 Note 2 − AX, CY ← AX + word × × × 16-bit ADDW AX, #word operation − AX, CY ← AX − word ×...
Page 643 CHAPTER 26 INSTRUCTION SET Clocks Flag Instruction Mnemonic Operands Bytes Operation Group Z AC CY Note 1 Note 2 CY ← CY ∧ saddr.bit) × AND1 CY, saddr.bit manipulate − CY ← CY ∧ sfr.bit × CY, sfr.bit − CY ← CY ∧ A.bit ×...
Page 644 CHAPTER 26 INSTRUCTION SET Clocks Flag Instruction Mnemonic Operands Bytes Operation Group Z AC CY Note 1 Note 2 − (SP − 1) ← (PC + 3) , (SP − 2) ← (PC + 3) Call/return CALL !addr16 PC ← addr16, SP ← SP − 2 −...
Page 645 CHAPTER 26 INSTRUCTION SET Clocks Flag Instruction Mnemonic Operands Bytes Operation Group Z AC CY Note 1 Note 2 PC ← PC + 3 + jdisp8 if(saddr.bit) = 1 Conditional saddr.bit, $addr16 branch − PC ← PC + 4 + jdisp8 if sfr.bit = 1 sfr.bit, $addr16 −...
Page 646: Instructions Listed By Addressing Type
CHAPTER 26 INSTRUCTION SET 26.3 Instructions Listed by Addressing Type (1) 8-bit instructions MOV, XCH, ADD, ADDC, SUB, SUBC, AND, OR, XOR, CMP, MULU, DIVUW, INC, DEC, ROR, ROL, RORC, ROLC, ROR4, ROL4, PUSH, POP, DBNZ Note Second Operand [HL + byte] #byte saddr !addr16...
Page 647 CHAPTER 26 INSTRUCTION SET (2) 16-bit instructions MOVW, XCHW, ADDW, SUBW, CMPW, PUSH, POP, INCW, DECW Note Second Operand #word sfrp saddrp !addr16 None First Operand ADDW MOVW MOVW MOVW MOVW MOVW SUBW XCHW CMPW Note MOVW MOVW INCW DECW PUSH Sfrp MOVW...
Page 648 CHAPTER 26 INSTRUCTION SET (4) Call instructions/branch instructions CALL, CALLF, CALLT, BR, BC, BNC, BZ, BNZ, BT, BF, BTCLR, DBNZ Second Operand !addr16 !addr11 [addr5] $addr16 First Operand Basic instruction CALL CALLF CALLT Compound instruction BTCLR DBNZ (5) Other instructions ADJBA, ADJBS, BRK, RET, RETI, RETB, SEL, NOP, EI, DI, HALT, STOP User’s Manual U17553EJ4V0UD...
Page 649: Chapter 27 Electrical Specifications ((A) Grade Products)
CHAPTER 27 ELECTRICAL SPECIFICATIONS ((A) GRADE PRODUCTS) 27.1 Absolute Maximum Ratings Absolute Maximum Ratings (T = 25°C) (1/2) Parameter Symbol Conditions Ratings Unit −0.5 to +6.5 Supply voltage −0.5 to +6.5 −0.5 to +0.3 −0.5 to +0.3 −0.5 to V Note +0.3 −0.5 to +0.3...
Page 650 CHAPTER 27 ELECTRICAL SPECIFICATIONS ((A) GRADE PRODUCTS) Absolute Maximum Ratings (T = 25°C) (2/2) Parameter Symbol Conditions Ratings Unit Output current, low Per pin P00, P01, P05, P06, P10 to P17, P30 to P33, P40 to P47, P50 to P57, P60 to P67, P70 to P76, P120, P130 to P132 Total of P05, P06, P10 to P17,...
Page 651: Oscillator Characteristics
CHAPTER 27 ELECTRICAL SPECIFICATIONS ((A) GRADE PRODUCTS) 27.2 Oscillator Characteristics (1) Main System Clock (Crystal/Ceramic) Oscillator Characteristics = −40 to +85°C, 1.8 V ≤ V ≤ 5.5 V, V = EV = EV = AV = 0 V) Resonator Recommended Circuit Parameter Conditions MIN.
Page 652 CHAPTER 27 ELECTRICAL SPECIFICATIONS ((A) GRADE PRODUCTS) (2) On-chip Internal Oscillator Characteristics = −40 to +85°C, 1.8 V ≤ V ≤ 5.5 V, V = EV = EV = AV = 0 V) Resonator Parameter Conditions MIN. TYP. MAX. Unit 2.7 V ≤...
Page 653: Dc Characteristics
CHAPTER 27 ELECTRICAL SPECIFICATIONS ((A) GRADE PRODUCTS) 27.3 DC Characteristics DC Characteristics (1/7) = −40 to +85°C, 4.0 V ≤ V ≤ 5.5 V, V = EV = EV = AV = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit −3.0 Note 1...
Page 654 CHAPTER 27 ELECTRICAL SPECIFICATIONS ((A) GRADE PRODUCTS) DC Characteristics (2/7) = −40 to +85°C, 2.7 V ≤ V = EV < 4.0 V, V = EV = AV = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit −2.5 Note 1 Output current, high Per pin for P00, P01, P05, P06, P10 to P17, P30 to P33, P40 to P47, P50 to P57, P64 to P67,...
Page 655 CHAPTER 27 ELECTRICAL SPECIFICATIONS ((A) GRADE PRODUCTS) DC Characteristics (3/7) = −40 to +85°C, 1.8 V ≤ V = EV < 2.7 V, V = EV = AV = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit −1.0 Note 1 Output current, high Per pin for P00, P01, P05, P06, P10 to P17, P30 to P33, P40 to P47, P50 to P57, P64 to P67,...
Page 656 CHAPTER 27 ELECTRICAL SPECIFICATIONS ((A) GRADE PRODUCTS) DC Characteristics (4/7) = −40 to +85°C, 1.8 V ≤ V ≤ 5.5 V, V = EV = EV = AV = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit Input voltage, high P12, P13, P15, P40 to P47, P50 to P57, P64 to P67, 0.7V P70, P74, P121-P124...
Page 657 CHAPTER 27 ELECTRICAL SPECIFICATIONS ((A) GRADE PRODUCTS) DC Characteristics (5/7) = −40 to +85°C, 1.8 V ≤ V ≤ 5.5 V, V = EV = EV = AV = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit μ P00, P01, P05, P06, P10 to P17, Input leakage current, LIH1 P30 to P33, P40 to P47, P50 to P57,...
Page 658 CHAPTER 27 ELECTRICAL SPECIFICATIONS ((A) GRADE PRODUCTS) DC Characteristics (6/7) = −40 to +85°C, 1.8 V ≤ V ≤ 5.5 V, 2.3 V ≤ AV ≤ V = EV = EV = AV = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit Note 1 Supply current Operating...
Page 659 LVI operating current Notes 1. Current flowing only to the A/D converter (AVREF-pin). The current value of the 78K0/FF2 is the sum of or I and I when the A/D converter operates in an operation mode or the HALT mode.
Page 660: Ac Characteristics
CHAPTER 27 ELECTRICAL SPECIFICATIONS ((A) GRADE PRODUCTS) 27.4 AC Characteristics (1) Basic operation = −40 to +85°C, 1.8 V ≤ V ≤ 5.5 V, V = EV = EV = AV = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit μ...
Page 661 CHAPTER 27 ELECTRICAL SPECIFICATIONS ((A) GRADE PRODUCTS) vs. V (Main System Clock Operation) 20.0 10.0 Guaranteed operation range Supply voltage V User’s Manual U17553EJ4V0UD...
Page 662 CHAPTER 27 ELECTRICAL SPECIFICATIONS ((A) GRADE PRODUCTS) AC Timing Test Points (Excluding X1, XT1) 0.8V 0.8V Test points 0.2V 0.2V External clock input timing EXTL EXTH 0.8V EXCLK 0.2V EXTS EXTSL EXTSH 0.8V EXCLKS 0.2V TI Timing TIL0 TIH0 TI000, TI001, TI002, TI003, TI010, TI011, TI012, TI013 TIL5 TIH5...
Page 663 CHAPTER 27 ELECTRICAL SPECIFICATIONS ((A) GRADE PRODUCTS) RESET Input Timing RESET (2) Serial interface = −40 to +85°C, 1.8 V ≤ V ≤ 5.5 V, V = EV = EV = AV = 0 V) (a) UART mode (UART6n, dedicated baud rate generator output) Parameter Symbol Conditions...
Page 664 CHAPTER 27 ELECTRICAL SPECIFICATIONS ((A) GRADE PRODUCTS) Serial Transfer Timing 3-wire serial I/O mode: KCYm SCK1n SIKm KSIm SI1n Input data KSOm SO1n Output data Remark m = 1, 2 n = 0, 1 User’s Manual U17553EJ4V0UD...
Page 665 ) = Internal Transfer Delay (t ) + Internal Receive Delay (t NODE output input Note CAN Internal clock (f ): CAN baud rate clock CTxD pin 78K0/FF2 Internal Transfer Delay macro Internal Receive Delay CRxD pin Image figure of internal delay User’s Manual U17553EJ4V0UD...
Page 666 CHAPTER 27 ELECTRICAL SPECIFICATIONS ((A) GRADE PRODUCTS) (4) A/D Converter Characteristics = −40 to +85°C, 2.3 V ≤ V ≤ 5.5 V, 2.3 V ≤ AV ≤ V = EV = EV = AV = 0 V) Parameter Symbol Conditions MIN.
Page 667 CHAPTER 27 ELECTRICAL SPECIFICATIONS ((A) GRADE PRODUCTS) (5) POC Circuit Characteristics = −40 to +85°C, V = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit Detection voltage 1.44 1.59 1.74 POC0 : 0 V → V Power supply rise time V/ms POC0 μ...
Page 668 CHAPTER 27 ELECTRICAL SPECIFICATIONS ((A) GRADE PRODUCTS) (6) LVI Circuit Characteristics = −40 to +85°C, V ≤ V ≤ 5.5 V, AV ≤ V = EV = EV = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit Detection Supply voltage level 4.14 4.24 4.34...
Page 669 CHAPTER 27 ELECTRICAL SPECIFICATIONS ((A) GRADE PRODUCTS) (7) Power Supply Starting Time = −40 to +85°C, V = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit Note1 LVI starting option invalid Starting maximum time to V min (1.8 V) PUP1 When pin RESET intact : 0 V→1.8 V)
Page 670: Data Retention Characteristics
CHAPTER 27 ELECTRICAL SPECIFICATIONS ((A) GRADE PRODUCTS) 27.5 Data Retention Characteristics = −40 to +85°C) Data Memory STOP Mode Low Supply Voltage Data Retention Characteristics (T Parameter Symbol Conditions MIN. TYP. MAX. Unit Note Data retention supply voltage 1.44 DDDR Note The value depends on the POC detection voltage.
Page 671: Flash Eeprom Programming Characteristics
CHAPTER 27 ELECTRICAL SPECIFICATIONS ((A) GRADE PRODUCTS) 27.6 Flash EEPROM Programming Characteristics (1) Basic characteristics = −40 to +85°C, 2.7 V ≤ V ≤ 5.5 V, V = EV = EV = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit supply current = 10 MHz (TYP.), 20 MHz (MAX.)
Page 672: Chapter 28 Electrical Specifications ((A2) Grade Products)
CHAPTER 28 ELECTRICAL SPECIFICATIONS ((A2) GRADE PRODUCTS) 28.1 Absolute Maximum Ratings Absolute Maximum Ratings (T = 25°C) (1/2) Parameter Symbol Conditions Ratings Unit −0.5 to +6.5 Supply voltage −0.5 to +6.5 −0.5 to +0.3 −0.5 to +0.3 −0.5 to V Note +0.3 −0.5 to +0.3...
Page 673 CHAPTER 28 ELECTRICAL SPECIFICATIONS ((A2) GRADE PRODUCTS) Absolute Maximum Ratings (T = 25°C) (2/2) Parameter Symbol Conditions Ratings Unit Output current, low Per pin P00, P01, P05, P06, P10 to P17, P30 to P33, P40 to P47, P50 to P57, P60 to P67, P70 to P76, P120, P130, P131, P132 Total of...
Page 674: Oscillator Characteristics
CHAPTER 28 ELECTRICAL SPECIFICATIONS ((A2) GRADE PRODUCTS) 28.2 Oscillator Characteristics (1) Main System Clock (Crystal/Ceramic) Oscillator Characteristics = −40 to +125°C, 2.7 V ≤ V ≤ 5.5 V, V = EV = EV = AV = 0 V) Resonator Recommended Circuit Parameter Conditions MIN.
Page 675 CHAPTER 28 ELECTRICAL SPECIFICATIONS ((A2) GRADE PRODUCTS) (2) On-chip Internal Oscillator Characteristics = −40 to +125°C, 2.7 V ≤ V ≤ 5.5 V, V = EV = EV = AV = 0 V) Resonator Parameter Conditions MIN. TYP. MAX. Unit 2.7 V ≤...
Page 676: Dc Characteristics
CHAPTER 28 ELECTRICAL SPECIFICATIONS ((A2) GRADE PRODUCTS) 28.3 DC Characteristics DC Characteristics (1/6) = −40 to +125°C, 4.0 V ≤ V ≤ 5.5 V, V = EV = EV = AV = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit −1.5 Note 1...
Page 677 CHAPTER 28 ELECTRICAL SPECIFICATIONS ((A2) GRADE PRODUCTS) DC Characteristics (2/6) = −40 to +125°C, 2.7 V ≤ V = EV < 4.0 V, V = EV = AV = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit −1.0 Note 1 Output current, high Per pin for P00, P01, P05, P06, P10 to P17, P30 to P33, P40 to P47, P50 to P57, P64 to P67,...
Page 678 CHAPTER 28 ELECTRICAL SPECIFICATIONS ((A2) GRADE PRODUCTS) DC Characteristics (3/6) = −40 to +125°C, 2.7 V ≤ V ≤ 5.5 V, V = EV = EV = AV = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit Input voltage, high P12, P13, P15, P40 to P47, P50 to P57, P64 to P67, 0.7V P70, P74, P121 to P124...
Page 679 CHAPTER 28 ELECTRICAL SPECIFICATIONS ((A2) GRADE PRODUCTS) DC Characteristics (4/6) = −40 to +125°C, 2.7 V ≤ V ≤ 5.5 V, V = EV = EV = AV = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit μ P00, P01, P05, P06, P10 to P17, Input leakage current, LIH1 P30 to P33, P40 to P47, P50 to P57,...
Page 680 CHAPTER 28 ELECTRICAL SPECIFICATIONS ((A2) GRADE PRODUCTS) DC Characteristics (5/6) = −40 to +125°C, 2.7 V ≤ V ≤ 5.5 V, 2.7 V ≤ AV ≤ V = EV = EV = AV = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit Note 1 Supply current Operating...
Page 681 LVI operating current Notes 1. Current flowing only to the A/D converter (AVREF-pin). The current value of the 78K0/FF2 is the sum of or I and I when the A/D converter operates in an operation mode or the HALT mode.
Page 682: Ac Characteristics
CHAPTER 28 ELECTRICAL SPECIFICATIONS ((A2) GRADE PRODUCTS) 28.4 AC Characteristics (1) Basic operation = −40 to +125°C, 2.7 V ≤ V ≤ 5.5 V, V = EV = EV = AV = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit μ...
Page 683 CHAPTER 28 ELECTRICAL SPECIFICATIONS ((A2) GRADE PRODUCTS) vs. V (Main System Clock Operation) 20.0 10.0 Guaranteed operation range Supply voltage V User’s Manual U17553EJ4V0UD...
Page 684 CHAPTER 28 ELECTRICAL SPECIFICATIONS ((A2) GRADE PRODUCTS) AC Timing Test Points (Excluding X1, XT1) 0.8V 0.8V Test points 0.2V 0.2V External clock input timing EXTL EXTH 0.8V EXCLK 0.2V EXTS EXTSL EXTSH 0.8V EXCLKS 0.2V TI Timing TIL0 TIH0 TI000, TI001, TI002, TI003, TI010, TI011, TI012, TI013 TIL5 TIH5...
Page 685 CHAPTER 28 ELECTRICAL SPECIFICATIONS ((A2) GRADE PRODUCTS) RESET Input Timing RESET (2) Serial interface = −40 to +125°C, 2.7V ≤ V ≤ 5.5 V, V = EV = EV = AV = 0 V) (a) UART mode (UART6n, dedicated baud rate generator output) Parameter Symbol Conditions...
Page 686 CHAPTER 28 ELECTRICAL SPECIFICATIONS ((A2) GRADE PRODUCTS) Serial Transfer Timing 3-wire serial I/O mode: KCYm SCK1n SIKm KSIm SI1n Input data KSOm SO1n Output data Remark m = 1, 2 n = 0, 1 User’s Manual U17553EJ4V0UD...
Page 687 ) = Internal Transfer Delay (t ) + Internal Receive Delay (t NODE output input Note CAN Internal clock (f ): CAN baud rate clock CTxD pin 78K0/FF2 Internal Transfer Delay macro Internal Receive Delay CRxD pin Image figure of internal delay User’s Manual U17553EJ4V0UD...
Page 688 CHAPTER 28 ELECTRICAL SPECIFICATIONS ((A2) GRADE PRODUCTS) (4) A/D Converter Characteristics = −40 to +125°C, 2.7 V ≤ V ≤ 5.5 V, 2.7 V ≤ AV ≤ V = EV = EV = AV = 0 V) Parameter Symbol Conditions MIN.
Page 689 CHAPTER 28 ELECTRICAL SPECIFICATIONS ((A2) GRADE PRODUCTS) (5) POC Circuit Characteristics = −40 to +125°C, V = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit Detection voltage 1.44 1.59 1.74 POC0 : 0 V → V Power supply rise time V/ms POC0 μ...
Page 690 CHAPTER 28 ELECTRICAL SPECIFICATIONS ((A2) GRADE PRODUCTS) (6) LVI Circuit Characteristics = −40 to +125°C, V ≤ V ≤ 5.5 V, AV ≤ V = EV = EV = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit Detection Supply voltage level 4.14 4.24 4.34...
Page 691 CHAPTER 28 ELECTRICAL SPECIFICATIONS ((A2) GRADE PRODUCTS) (7) Power Supply Starting Time = −40 to +125°C, V = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit Note1 LVI starting option invalid Starting maximum time to V min (2.7V) PUP1 When pin RESET intact : 0 V→2.7V) Note1...
Page 692: Data Retention Characteristics
CHAPTER 28 ELECTRICAL SPECIFICATIONS ((A2) GRADE PRODUCTS) 28.5 Data Retention Characteristics = −40 to +125°C) Data Memory STOP Mode Low Supply Voltage Data Retention Characteristics (T Parameter Symbol Conditions MIN. TYP. MAX. Unit Note Data retention supply voltage 1.44 DDDR Note The value depends on the POC detection voltage.
Page 693: Flash Eeprom Programming Characteristics
CHAPTER 28 ELECTRICAL SPECIFICATIONS ((A2) GRADE PRODUCTS) 28.6 Flash EEPROM Programming Characteristics (1) Basic characteristics = −40 to +125°C, 2.7 V ≤ V ≤ 5.5 V, V = EV = EV = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit supply current = 10 MHz (TYP.), 20 MHz (MAX.)
Page 694: Chapter 29 Package Drawings
CHAPTER 29 PACKAGE DRAWINGS μ • PD78F0891GC(A)-GAD-AX, 78F0891GC(A2)-GAD-AX, 78F0892GC(A)-GAD-AX, 78F0892GC(A2)-GAD-AX, 78F0893GC(A)-GAD-AX, 78F0893GC(A2)-GAD-AX 80-PIN PLASTIC LQFP (14x14) detail of lead end θ (UNIT:mm) ITEM DIMENSIONS 14.00±0.20 14.00±0.20 17.20±0.20 17.20±0.20 1.70 MAX. 0.125±0.075 1.40±0.05 0.25 +0.08 0.30 −0.04 0.125 +0.075 −0.025 0.80 0.886±0.15 1.60±0.20 3°...
Page 695 CHAPTER 29 PACKAGE DRAWINGS μ • PD78F0891GK(A)-GAK-AX, 78F0891GK(A2)-GAK-AX, 78F0892GK(A)-GAK-AX, 78F0892GK(A2)-GAK-AX, 78F0893GK(A)-GAK-AX, 78F0893GK(A2)-GAK-AX 80-PIN PLASTIC LQFP (FINE PITCH) (12x12) detail of lead end θ (UNIT:mm) ITEM DIMENSIONS 12.00±0.20 12.00±0.20 14.00±0.20 14.00±0.20 1.60 MAX. 0.10±0.05 1.40±0.05 0.25 +0.07 0.20 −0.03 0.125 +0.075 −0.025 0.50 0.60±0.15...
Page 696: Chapter 30 Recommended Soldering Conditions
CHAPTER 30 RECOMMENDED SOLDERING CONDITIONS These products should be soldered and mounted under the following recommended conditions. For soldering methods and conditions other than those recommended below, please contact an NEC Electronics sales representative. For technical information, see the following website. Semiconductor Device Mount Manual (http://www.necel.com/pkg/en/mount/index.html) Table 30-1.
Page 697: Chapter 31 Cautions For Wait
CHAPTER 31 CAUTIONS FOR WAIT 31.1 Cautions for Wait This product has two internal system buses. One is a CPU bus and the other is a peripheral bus that interfaces with the low-speed peripheral hardware. Because the clock of the CPU bus and the clock of the peripheral bus are asynchronous, unexpected illegal data may be passed if an access to the CPU conflicts with an access to the peripheral hardware.
Page 698: Peripheral Hardware That Generates Wait
CHAPTER 31 CAUTIONS FOR WAIT 31.2 Peripheral Hardware That Generates Wait Table 31-1 lists the registers that issue a wait request when accessed by the CPU, and the number of CPU wait clocks. Table 31-1. Registers That Generate Wait and Number of CPU Wait Clocks Peripheral Register Access...
Page 699 CHAPTER 31 CAUTIONS FOR WAIT Table 31-2 RAM Access That Generate Wait and Number of CPU Wait Clocks number of wait clocks Cause Peripheral Register Access Hardware MIN. MAX. Global Reg. Read/Write synchronizaition of NPB signals with VPCLK CANmodule <Calculating number of wait clocks> MIN.
Page 700: Example Of Wait Occurrence
CHAPTER 31 CAUTIONS FOR WAIT 31.3 Example of Wait Occurrence • Serial interface UART61 <On execution of MOV A, ASIS61> Number of execution clocks: 6 (5 clocks when data is read from a register that does not issue a wait (MOV A, sfr).) User’s Manual U17553EJ4V0UD...
Page 701: Appendix A Development Tools
APPENDIX A DEVELOPMENT TOOLS The following development tools are available for the development of systems that employ the 78K0/FF2. Figure A-1 shows the development tool configuration. • Support for PC98-NX series Unless otherwise specified, products supported by IBM PC/AT compatibles are compatible with PC98-NX series computers.
Page 702 Flash memory Target system Notes 1. Download the device file for 78K0/FF2 (DF780893) from the download site for development tools (http://www.necel.com/micro/ods/eng/index.html). The C library source file is not included in the software package. The project manager PM+ is included in the assembler package.
Page 703 Target connector Target system Notes 1. Download the device file for 78K0/FF2 (DF780893) from the download site for development tools (http://www.necel.com/micro/ods/eng/index.html). The C library source file is not included in the software package. The project manager PM+ is included in the assembler package.
Page 704 Target connector Target system Notes 1. Download the device file for 78K0/FF2 (DF780893) and the integrated debugger (ID78K0-QB) from the download site for development tools (http://www.necel.com/micro/ods/eng/index.html). The C library source file is not included in the software package. The project manager PM+ is included in the assembler package.
Page 705: Software Package
APPENDIX A DEVELOPMENT TOOLS A.1 Software Package SP78K0 Development tools (software) common to the 78K/0 Series are combined in this package. 78K/0 Series software package μ Part number: S××××SP78K0 Remark ×××× in the part number differs depending on the host machine and OS used. μ...
Page 706: Control Software
APPENDIX A DEVELOPMENT TOOLS Remark ×××× in the part number differs depending on the host machine and OS used. μ S××××RA78K0 μ S××××CC78K0 μ S××××CC78K0-L ×××× Host Machine Supply Medium AB17 PC-9800 series, Windows (Japanese version) CD-ROM IBM PC/AT compatibles BB17 Windows (English version) 3P17...
Page 707: Flash Memory Programming Tools
APPENDIX A DEVELOPMENT TOOLS A.4 Flash Memory Programming Tools A.4.1 When using flash memory programmer FG-FP4, FL-PR4, PG-FPL3, and FP-LITE3 PG-FP4, FL-PR4 Flash memory programmer dedicated to microcontrollers with on-chip flash memory. Flash memory programmer PG-FPL3, FP-LITE3 Simple flash memory programmer dedicated to microcontrollers with on-chip flash Simple flash memory programmer memory.
Page 708: Debugging Tools (Hardware)
APPENDIX A DEVELOPMENT TOOLS A.5 Debugging Tools (Hardware) A.5.1 When using in-circuit emulator QB-78K0FX2 Note QB-78K0FX2 The in-circuit emulator serves to debug hardware and software when developing application In-circuit emulator systems using the 78K0/Fx2. It supports the integrated debugger (ID78K0-QB). This emulator should be used in combination with a power supply unit and emulation probe, and the USB is used to connect this emulator to the host machine.
Page 709: When Using On-Chip Debug Emulator With Programming Function Qb-Mini2
APPENDIX A DEVELOPMENT TOOLS A.5.3 When using on-chip debug emulator with programming function QB-MINI2 QB-MINI2 This on-chip debug emulator serves to debug hardware and software when developing On-chip debug emulator with application systems using the 78K0/Fx2. It is available also as flash memory programming function programmer dedicated to microcontrollers with on-chip flash memory.
Page 710: Appendix B Notes On Target System Design
APPENDIX B NOTES ON TARGET SYSTEM DESIGN This chapter shows areas on the target system where component mounting is prohibited and areas where there are component mounting height restrictions when the QB-78K0FX2 is used. (a) Case of 80-pin GC package Figure B-1.
Page 711 APPENDIX B NOTES ON TARGET SYSTEM DESIGN (b) Case of 80-pin GK package Figure B-2. The Restriction Domain on a Target System (Case of 80-pin GK Package) 13.375 17.375 Note : Exchange adapter area: Components up to 17.45 mm in height can be mounted Note : Emulation probe tip area: Components up to 24.45 mm in height can be mounted...
Page 712: Appendix C Register Index
APPENDIX C REGISTER INDEX C.1 Register Index (In Alphabetical Order with Respect to Register Names) 10-bit A/D conversion result register (ADCR)......................290 16-bit timer capture/compare register 000 (CR000) ....................165 16-bit timer capture/compare register 001 (CR001) ....................165 16-bit timer capture/compare register 002 (CR002) ....................165 16-bit timer capture/compare register 003 (CR003) ....................165 16-bit timer capture/compare register 010 (CR010) ....................167 16-bit timer capture/compare register 011 (CR011) ....................167...
Page 713 APPENDIX C REGISTER INDEX A/D port configuration register (ADPC) ........................293 Analog input channel specification register (ADS) ......................292 Asynchronous serial interface control register 60 (ASICL60)..................328 Asynchronous serial interface control register 61 (ASICL61)..................328 Asynchronous serial interface operation mode register 60 (ASIM60) .................315 Asynchronous serial interface operation mode register 61 (ASIM61) .................315 Asynchronous serial interface reception error status register 60 (ASIS60)..............320 Asynchronous serial interface reception error status register 61 (ASIS61)..............320...
Page 714 CAN module receive history list register (C0RGPT)....................441 CAN module time stamp register (C0TS) ........................444 CAN module transmit history list register (C0TGPT)....................443 Capture/compare control register 00 (CRC00)......................175 Capture/compare control register 01 (CRC01)......................175 Capture/compare control register 02 (CRC02)......................175 Capture/compare control register 03 (CRC03)......................175 Clock operation mode select register (OSCCTL) ......................132 Clock output selection register (CKS) .........................280 Clock selection register 60 (CKSR60).........................324...
Page 715 APPENDIX C REGISTER INDEX Oscillation stabilization time counter status register (OSTC) ..................134 Oscillation stabilization time select register (OSTS)....................135 Port mode register 0 (PM0)............................116 Port mode register 1 (PM1)............................116 Port mode register 12 (PM12).............................116 Port mode register 13 (PM13).............................116 Port mode register 3 (PM3)............................116 Port mode register 4 (PM4)............................116 Port mode register 5 (PM5)............................116 Port mode register 6 (PM6)............................116...
Page 716 Pull-up resistor option register 7 (PU7) ........................120 Receive buffer register 60 (RXB60) ..........................314 Receive buffer register 61 (RXB61) ..........................314 Receive shift register 60 (RXS60) ..........................314 Receive shift register 61 (RXS61) ..........................314 Remainder data register 0 (SDR0)..........................563 Reset control flag register (RESF) ..........................560 Serial clock selection register 10 (CSIC10) .........................361 Serial clock selection register 11 (CSIC11) .........................361 Serial operation mode register 10 (CSIM10) .......................359...
Page 717: Register Index (In Alphabetical Order With Respect To Register Symbol)
APPENDIX C REGISTER INDEX C.2 Register Index (In Alphabetical Order with Respect to Register Symbol) ADCR: 10-bit A/D conversion result register ....................290 ADCRH: 8-bit A/D conversion result register.....................291 ADM: A/D converter mode register .......................287 ADPC: A/D port configureation register ......................293 ADS: Analog input channel specification register..................292 ASICL60:...
Page 718 C0MASK3H: CAN module mask control register 3H....................425 C0MASK3L: CAN module mask control register 3L ....................425 C0MASK4H: CAN module mask control register 4H....................425 C0MASK4L: CAN module mask control register 4L ....................425 C0MIDHm: CAN message id register Hm ........................450 C0MIDLm: CAN message id register Lm .........................450 C0RGPT: CAN module receive history list register ....................441 C0TGPT:...
Page 719 APPENDIX C REGISTER INDEX IF0L: Interrupt request flag register 0L ......................523 IF1H: Interrupt request flag register 1H ......................523 IF1L: Interrupt request flag register 1L ......................523 IMS: Internal memory size switching register....................599 ISC: Input switch control register........................332 IXS: Internal expansion RAM size switching register ..................600 LVIM: Low-voltage detection register ........................578 LVIS:...
Page 720 PM4: Port mode register 4 ..........................116 PM5: Port mode register 5 ..........................116 PM6: Port mode register 6 ..........................116 PM7: Port mode register 7 ..........................116 PM8: Port mode register 8 ..........................116 PM9: Port mode register 9 ..........................116 PR0H: Priority specification flag register 0H .......................526 PR0L: Priority specification flag register 0L ......................526 PR1H:...
Page 721 APPENDIX C REGISTER INDEX TM50: 8-bit timer counter 50 ..........................223 TM51: 8-bit timer counter 51 ..........................223 TMC00: 16-bit timer mode control register 00.......................170 TMC01: 16-bit timer mode control register 01.......................170 TMC02: 16-bit timer mode control register 02.......................170 TMC03: 16-bit timer mode control register 03.......................170 TMC50: 8-bit timer mode control register 50......................227 TMC51:...
Page 722: Appendix D Revision History
APPENDIX D REVISION HISTORY The mark <R> shows major revised points. The revised points can be easily searched by copying an “<R>” in the PDF file and specifying it in the “Fine what:” field. D.1 Main Revisions in this Edition Page Description Addition of QB-MINI2 in Documents Related to Development Tools (Hardware) (User’s Manuals)
Page 723: Revision History Of Preceding Editions
APPENDIX D REVISION HISTORY D.2 Revision History of Preceding Editions Here is the revision history of the preceding editions. Chapter indicates the chapter of each edition. (1/10) Edition Description Addition of PG-FPL3 in Documents Related to Flash Memory Programming Addition of Caution 1 to 4 to 1.4 Pin Configuration (Top View) Change of 10-bit A/D converter number for 78K0/FC2 in 1.5.1 78K0/Fx2 product lineup Change of EV and V...
Page 724 APPENDIX D REVISION HISTORY (2/10) Edition Description Figure 6-12 Operation of the clock generating circuit when power supply voltage injection (When 1.59 V POC mode setup (option byte: LVISTART = 0)) • Change of Figure 6-12 and Note 2 • Addition of Note 1 Figure 6-13 Operation of the clock generating circuit when power supply voltage injection (When 2.7 V/1.59V POC mode setup (option byte: LVISTART = 1)) •...
Page 725 APPENDIX D REVISION HISTORY (3/10) Edition Description Change of Caution 1 in Figure 9-5. Format of 8-Bit Timer H Mode Register 0 (TMHMD0) Change of Figure 9-6. Format of 8-Bit Timer H Mode Register 1 (TMHMD1) Change of Caution 1 in Figure 9-6. Format of 8-Bit Timer H Mode Register 1 (TMHMD1) Change of Figure 9-7.
Page 726 APPENDIX D REVISION HISTORY (4/10) Edition Description Addition of Caution 4 and 5 in Figure 14-8. Format of Asynchronous Serial Interface Operation Mode Register 61 (ASIM61) (2/2) Change of bit 0 from INTSR6n to TXSF6n of 14.3 (3) Asynchronous serial interface transmission status register 6n (ASIF6n), Figure 14-11.
Page 727 APPENDIX D REVISION HISTORY (5/10) Edition Description Change of Table 16-11. Error Types Change of Table 16-13. Types of Error States Change of explanation in 16.3.6 (4) (b) Error counter Change of Caution in 16.3.6 (4) (c) Occurrence of bit error in intermission Change of explanation in 16.3.6 (5) Recovery from bus-off state Change of explanation and Caution 2 and Addition of Caution 1 in 16.3.6 (5) (a) Recovery operation from bus-off state through normal recovery sequence...
Page 728 APPENDIX D REVISION HISTORY (6/10) Edition Description Addition of Note in Figure 16-47. Transmission Abort Processing (Except Normal Operation Mode with ABT) Addition of Note in Figure 16-48. Transmission Abort Processing Except for ABT Transmission (Normal Operation Mode with ABT) Change of Figure 16-51.
Page 729 APPENDIX D REVISION HISTORY (7/10) Edition Description Figure 21-2. Timing of Generation of Internal Reset Signal by Power-on-Clear Circuit and Low-Voltage Detector (2/2) • Change of Figure and Note 2 • Addition of Note 1 and Caution 2 Change of Figure 21-3. Example of Software Processing After Reset Release (1/2) Change of explanation in 22.1 Functions of Low-Voltage Detector Change of Figure 22-1.
Page 730 APPENDIX D REVISION HISTORY (8/10) Edition Description Change of Note 1 in Table 24-7. Communication Modes Addition of 24.8 Security Settings Addition of 24.9 Processing Time for Each Command When PG-FP4 Is Used (Reference) Change of Figure 24-16. Self-Programming Procedure Addition of Table 24-14.
Page 731 APPENDIX D REVISION HISTORY (9/10) Edition Description 27.4 (4) A/D Converter Characteristics • Addition of MAX. value of Overall, Conversion time, Zero-scale error, Full-scale error, Integral non-linearity error, Differential non-linearity error Change of MIN. value of Power supply rise time, Minimum pulse width in 27.4 (5) POC Circuit Characteristics 27.4 (6) LVI Circuit Characteristics •...
Page 732 APPENDIX D REVISION HISTORY (10/10) Edition Description Addition of Caution in 23.7.4 Port pins Addition of Caution 3 in 23.7.6 Other signal pins Modification of standard setting in Table 23-7 Communication Modes Modification of Note 4 in 26.3 DC characteristics User’s Manual U17553EJ4V0UM...
Page 733 [MEMO] User’s Manual U17553EJ4V0UD...
Page 734 For further information, please contact: NEC Electronics Corporation 1753, Shimonumabe, Nakahara-ku, Kawasaki, Kanagawa 211-8668, Japan Tel: 044-435-5111 http://www.necel.com/ [America] [Asia & Oceania] [Europe] NEC Electronics (China) Co., Ltd NEC Electronics America, Inc. NEC Electronics (Europe) GmbH 7th Floor, Quantum Plaza, No. 27 ZhiChunLu Haidian 2880 Scott Blvd.

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Renesas 78K0/FF2 User Manual

Chapter 1 Outline

Chapter 2 Pin Functions

Chapter 3 Cpu Architecture

CHAPTER 4 MEMORY BANK SELECT FUNCTION ( Μ PD78F0892, 78F0893 ONLY)

Chapter 5 Port Functions

Chapter 6 Clock Generator

Chapter 7 16-Bit Timer/Event Counters 00 to 03

Chapter 8 8-Bit Timer/Event Counters 50 and 51

Chapter 9 8-Bit Timers H0 and H1

Chapter 10 Watch Timer

Chapter 11 Watchdog Timer

Chapter 12 Clock Output/Buzzer Output Controller

Chapter 13 A/D Converter

Chapter 14 Serial Interfaces Uart60 and Uart61

Chapter 15 Serial Interfaces Csi10 and Csi11

Chapter 16 Can Controller

Chapter 17 Interrupt Functions

Chapter 18 Standby Function

Chapter 19 Reset Function

Chapter 20 Multiplier/Divider

Chapter 21 Power-On-Clear Circuit

Chapter 22 Low-Voltage Detector

Chapter 23 Option Byte

Chapter 24 Flash Memory

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Summary of Contents for Renesas 78K0/FF2