Renesas M16C/64A Series User Manual page 838

REVISION HISTORY
Rev. Date
Page
1.10 Jul 15, 2009 576
577, 578 Figure 25.22 "Generating a Stop Condition" and Figure 25.23 "Abnormal Waveform" added
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685, 687 Table 30.18, Table 30.20 Pin Functions (Flash Memory Standard Serial I/O Mode) partially modified
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M16C/64A Group Hardware Manual
25.5.3 "Generating Stop Condition" added
26.2.1 "CEC Function Control Register 1 (CECC1)" partially modified
26.2.2 "CEC Function Control Register 2 (CECC2)" partially deleted
Figure 26.10 "Reception Example (Change from Error Low Pulse Output Disabled to Enabled
When an Error Occurs)" partially modified
Figure 26.12 "Falling Timing of Transmit Signal" 000b → 00b
26.5.2 "Low Level Period of ACK Input/Output" deleted
Figure 27.1 "A/D Converter Block Diagram" partially modified
27.2.6 "A/D Control Register 1 (ADCON1)" partially modified
Figure 27.3 "A/D Conversion Timing" 2.5 φAD → 25 φAD
Figure 27.5 "A/D conversion Start Timing When External Trigger Input" added
Table 27.9, Table 27.11, Table 27.13, Table 27.15, and Table 27.17 "Registers and Settings "
partially modified
27.7.2 "φA/D frequency" deleted
30.2 "Memory Map" partially modified
Table 30.3 "Program ROM 1, Program ROM 2, and Data Flash" User boot program line added
30.3.1 "Flash Memory Control Register 0 (FMR0)" partially modified
30.3.2 "Flash Memory Control Register 1 (FMR1)" partially added
30.3.4 "Flash Memory Control Register 6 (FMR6)" partially modified
30.4 "Optional Function Select Area" partially modified
Figure 30.2 "Option Function Select Area" added
30.4.1 "Optional Function Select Address 1 (OFS1)" partially modified
Figure 30.3 "User Boot Code Area" 13800h → 13000h
30.8.3.8 "Block Blank Check Command" partially added
30.8.4 "Status Register" partially modified
Table 30.13 "Difference in Reading of Status Register" added
30.8.4.1 to 30.8.4.3 "Sequencer Status (Bits SR7 and FMR00)", Erase Status (Bits SR5 and
FMR07), Program Status (Bits SR4 and FMR06) deleted
30.8.4.2 "Handling Procedure for Errors" added
30.8.5 "EW0 Mode" partially modified
30.8.6 "EW1 Mode" partially modified
30.9.4 "Standard Serial I/O Mode 1" partially deleted
30.9.5 "Standard Serial I/O Mode 2" partially deleted
Figure 30.17 "Circuit Application in Standard Serial I/O Mode 2" note added
30.11.3.2 "CPU Rewrite Mode Select" added
30.11.3.10 "Software Command" partially modified
30.11.4.1 "Location of User Boot Mode Program" added
30.11.5 "EW1 Mode" added
Table 31.1 "Absolute Maximum Ratings" partially modified
Table 31.2 "Recommended Operating Conditions (1/3)" partially modified
Table 31.3 "Recommended Operating Conditions (2/3)" partially modified
Table 31.4 "Recommended Operating Conditions (3/3)" added
Figure 31.1 "Ripple Waveform" added
Table 31.5 "A/D Conversion Characteristics (1/2)" partially modified
Figure 31.2 "A/D Accuracy Measure Circuit" added
Table 31.6 "A/D Conversion Characteristics (2/2)" partially modified
Table 31.8 "CPU Clock When Operating Flash Memory (f
Table 31.9 "Flash Memory (Program ROM 1, 2) Electrical Characteristics" notes modified
Table 31.11 "Voltage Detector 0 Electrical Characteristics" partially modified
Table 31.12 "Voltage Detector 1 Electrical Characteristics" partially modified
Table 31.13 "Voltage Detector 2 Electrical Characteristics" partially modified
Description
Summary
C - 5
)" partially modified
(BCLK)