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M16C/64A Group
6.5.3
OSDR Bit (Oscillation Stop Detect Reset Detect Flag)
When an oscillator stop detect reset is generated, the MCU is reset and then stopped. This state is
canceled by hardware reset or voltage monitor 0 reset.
Note that the OSDR bit in the RSTFR register is not affected by a hardware reset, but becomes 0 (not
detected) from a voltage monitor 0 reset.
6.5.4
Hardware Reset when VCC1 < Vdet0
When a hardware reset is executed while VCC1 < Vdet0, the voltage monitor 0 reset is not performed
after the hardware reset even if the LVDAS bit in the OFS1 address is 0 (voltage monitor 0 reset
enabled after hardware reset).
VCC1
Vdet0
RESET
Voltage monitor 0 reset
Figure 6.9
Hardware Reset when VCC1 < Vdet0
R01UH0136EJ0210 Rev.2.10
Jul 31, 2012
(Voltage monitor 0 reset is canceled)
(Reset is not released)
Hardware reset
Voltage monitor
Reset sequence
0 reset
by hardware reset
6. Resets
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