Renesas M16C/64A Series User Manual page 309

M16C/64A Group
TAiIN input
FFFFh
Counter
operations
n
0000h
TAiS bit in the
TABSR register
TAiUD bit in the
UDF register
TAiOUT output
POFSi = 0
POFSi = 1
IR bit in the
TAiIC register
i = 0 to 4
n: TAi register setting
POFSi: Bits in the TAPOFS register
The above timing diagram assumes the following:
- Bits TAiTGH to TAiTGL in the ONSF or TRGSR register = 00b
- The MR1 bit in the TAiMR register
- The MR0 bit in the TAiMR register
- The TCK0 bit in the TAiMR register
Figure 17.6 Operation Example in Event Counter Mode
R01UH0136EJ0210 Rev.2.10
Jul 31, 2012
Count started
Underflow
n+1
reload
Low-level output
Output inverted at underflow or overflow
at count stop
High-level output
at count stop
Becomes 0 by accepting an interrupt request, or by a program.
Overflow and
reload
Increment
FFFFh-n+1
(The falling edges of the TAiIN pin input is counted.)
= 0
= 1 (pulse output)
= 0 (reload type)
17. Timer A
Decrement
Count
stopped
Low-level output at count stop
High-level output at count stop
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