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M16C/64A Group
24.3.5
Function for Selecting SOUTi State after Transmission
The SOUTi pin state after transmission can be selected when the SMi6 bit in the SiC register is set to 1
(internal clock). If bits SM26 and SM27 in the S34C2 register are both set to 1 (last bit level retained),
output from the SOUTi pin retains the last bit level after transmission. Figure 24.5 shows SOUT3 Pin
Level after Transmission.
SI/O internal clock
CLK3 output
When SM26 = 0
(high-impedance)
SOUT3
output
When SM26 = 1
(last bit level retained)
The above SOUT3 example assumes the following:
The SM32 bit in the S3C register is 0 (SOUT3 output),
The SM33 bit in the S3C register is 1 (SOUT3 output, CLK3 selected),
The SM34 bit in the S3C register is 0 (transmit data output at the falling edge of the transmit/receive
The SM35 bit in the S3C register is 0 (LSB first),
The SM36 bit in the S3C register is 1 (internal clock)
Figure 24.5
SOUT3 Pin Level after Transmission
R01UH0136EJ0210 Rev.2.10
Jul 31, 2012
High
Low
High
Low
D6
D6
clock and the receive data is input at the rising edge ),
24. Serial Interface SI/O3 and SI/O4
Hi-Z
D7
D7
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