Renesas M16C/64A Series User Manual page 728

M16C/64A Group
Table 30.24 Setting of Standard Serial I/O Mode 2
Signal
CNVSS
EPM
RESET
CE
P6_5/CLK1
TXD output
Monitor output
RXD input
Reset input
Notes:
1. Control pins vary by programmer. For more information, refer to the programmer manual.
2. In this example, modes are switched between single-chip mode and standard serial I/O
mode by controlling the CNVSS pin input with a switch.
Figure 30.18 Circuit Application in Standard Serial I/O Mode 2
30.10 Parallel I/O Mode
In parallel I/O mode, program ROM 1, program ROM 2, and data flash can be rewritten using a parallel
programmer supporting the M16C/64A Group. Contact the parallel programmer manufacturer for more
information. Refer to the user's manual included with your parallel programmer for instructions.
30.10.1 ROM Code Protect Function
The ROM code protect function disables the flash memory from being read or rewritten during
parallel I/O mode. Refer to 30.4.1 "Optional Function Select Address 1 (OFS1)". The OFS1 address
is located in block 0 of program ROM 1.
When the ROMCR bit in the OFS1 address is 1 (ROMCP1 bit enabled) and the ROMCP1 bit is set to
0, the ROM code protect function is enabled.
To cancel ROM code protect, erase block 0 including the OFS1 address using standard serial I/O
mode or CPU rewrite mode.
R01UH0136EJ0210 Rev.2.10
Jul 31, 2012
Input Level
VCC1
VSS
VSS → VCC1
VCC2
VSS
VCC1
User reset signal
MCU
P5_0 (CE)
P6_7/TXD1
P5_5 (EPM)
P6_4/RTS1
P6_6/RXD1 CNVSS
P6_5/CLK1
RESET
30. Flash Memory
VCC2
VCC1
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