Interrupts - Renesas M16C/64A Series User Manual

M16C/64A Group
22.4

Interrupts

The remote control signal receiver has remote control signal receiver 0 interrupt and remote control signal
receiver 1 interrupt. The remote control signal receiver 0 interrupt and remote control signal receiver 1
interrupt are interrupts in PMC0 and PMC1, respectively.
A remote control signal receiver i interrupt request signal is generated every time the conditions are met.
If the interrupt enable bit in the PMCiCON2 or PMCiINT register is 1, the IR bit in the PMCiIC register
becomes 1 (interrupt request) when the corresponding interrupt request signal is generated. Table 22.21
lists Interrupt Source of Remote Control Signal Receiver i Interrupt (i = 0, 1).
Table 22.21 Interrupt Source of Remote Control Signal Receiver i Interrupt (i = 0, 1)
Interrupt
Mode
Source
Completion of
data reception
Header match
Data 0/1
match
Special data
match
Pattern
match
mode
Receive error
Receive
buffer full
Compare
match
Timer
measurement
Timer
Input
measurement
capture
Counter
mode
overflow
Measured result: Content of the PMCiTIM register
R01UH0136EJ0210 Rev.2.10
Jul 31, 2012
Interrupt Request Generating Condition
Counter value is larger than values of
registers PMCiHDPMAX, PMCiD0PMAX, and
PMCiD1PMAX
The measured result is within the range set by
registers PMCiHDPMIN and PMCiHDPMAX
(when header is enabled)
The measured result is within the range set by
registers PMCiD0PMIN and PMCiD0PMAX or
registers PMCiD1PMIN and PMCiD1PMAX
The measured result is within the range set by
registers PMCiHDPMIN and PMCiHDPMAX
(when special data is enabled)
Input signal width is not the header, data 0,
data 1, or special data.
Data 0 or data 1 is detected before detecting
the header when the HDEN bit is 1
The value of the PMC0RBIT register is 48
The values of registers PMC0CPD and
PMC0DAT0 are matched (only bits selected
by bits CPN2 to CPN0 in the PMC0CPC
register are compared)
Measurement end edge of PMCi internal input
signal
Measurement end edge of PMCi internal input
signal
Counter overflow (counter value exceeds
FFFFh and becomes 0000h)
22. Remote Control Signal Receiver
Interrupt Request Bit Interrupt Enable Bit
Register Bit Register
DRFLG
PMCiSTS PMCiINT
(Changes
from 1 to 0)
PMCiSTS PTHDFLG PMCiINT PTHDINT
PMCiSTS PTD0FLG
PMCiINT
PMCiSTS PTD1FLG
PMC0STS SDFLG PMC0INT
PMCiSTS REFLG PMCiINT
PMC0STS BFULFLG PMC0INT BFULINT
PMC0STS CPFLG PMC0INT
- - PMCiINT
- - PMCiINT
PMCiCON2 CEFLG PMCiCON2
Bit
DRINT
PTDINT
SDINT
REINT
CPINT
TIMINT
TIMINT
CEINT
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