Renesas M16C/64A Series User Manual page 623

M16C/64A Group
26.2.4 CEC Function Control Register 4 (CECC4)
CEC Function Control Register 4
b7 b6 b5 b4 b3 b2 b1 b0
CRISE2-CRISE0 (Rising timing select bit) (b2-b0)
The rising timing of the signal in transmission is selected. The rising timing is common to the start bit
and data bit. Do not write to bits CRISE2 to CRISE0 while transmitting/receiving.
CABTEN (Error low pulse output enable bit) (b3)
When the CRXDEN bit is 0 (receive disabled), if the CABTEN bit is set to 1 (low pulse output enabled in
receive error) and then the CRXDEN bit is set to 1 (receive enabled), a 3.6 ms low-level pulse is output
if the data bit during reception exceeds the tolerated range. Output timing is selected by setting the
CABTWEN bit.
After setting the CRXDEN bit to 1 (receive enabled) and then setting the CABTEN bit to 1 while not
receiving, a low pulse is output when writing to the CABTEN bit.
After setting the CRXDEN bit to 1 (receive enabled) and then setting the CABTEN bit to 1 if the
receiving data bit exceeds the tolerated range, a low pulse is output.
R01UH0136EJ0210 Rev.2.10
Jul 31, 2012
Symbol
CECC4
Bit Symbol Bit Name
CRISE0
CRISE1 Rising timing select bit
CRISE2
Error low pulse output
CABTEN
enabled bit
CFALL0
Falling timing select bit
CFALL1
CREGFLG Receive edge detect flag
Error low pulse output wait
CABTWEN
control bit
26. Consumer Electronics Control (CEC) Function
Address
0353h
Function
b2 b1 b0
0 0 0: Standard value
1: Standard value - 30 μ s
0 0
0: Standard value - 60 μ s
0 1
1: Standard value - 90 μ s
0 1
0: Standard value - 120 μ s
1 0
1: Standard value - 150 μ s
1 0
0: Standard value - 180 μ s
1 1
1: Standard value + 30 μ s
1 1
0: Disabled
1: Enabled
Refer to the following.
0: Not detected
1: Detected
0: Low pulse output regardless of
CEC signal state
1: Low pulse output at the rising edge
of the CEC signal
Reset Value
00h
RW
RW
RW
RW RW
RW
RW
RW
RO
RW
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