Renesas M16C/64A Series User Manual page 482

M16C/64A Group
RXD polarity
RXD0
switching circuit
Clock source selection
CLK1 to CLK0
CKDIR
f1SIO or
00b
f2SIO
01b
0
f8SIO
10b
f32SIO
1
CKPOL
CLK
polarity
CLK0
reversing
circuit
CTS/RTS selected
CTS0/
1
RTS0
CRS 0
CTS0 from UART1
n: Value set to the U0BRG register
PCLK1
SMD2 to SMD0, CKDIR
CLK1 to CLK0, CKPOL, CRD, CRS : Bits in the U0C0 register
RCSP
Figure 23.1 UART0 Block Diagram
R01UH0136EJ0210 Rev.2.10
Jul 31, 2012
f1
UART reception
100b, 101b, 110b
1/16
U0BRG
Internal
register
UART transmission
1/(n+1)
1/16
100b, 101b, 110b
External
Clock synchronous type
(when internal clock is selected)
1/2
Clock synchronous type
(when external clock is selected)
Clock synchronous type
(when internal clock is selected)
CTS/RTS disabled
RCSP
0 CTS/RTS disabled
0
1
1
CRD
VSS
: Bit in the PCLKR register
: Bits in the U0MR register
: Bit in the UCON register
23. Serial Interface UARTi (i = 0 to 2, 5 to 7)
PCLK1
f2SIO
0
1/2 1/2
f1SIO
1
1/8
SMD2 to SMD0
Reception
Clock sync type
control
circuit
001b, 010b
Transmission
control circuit
Clock sync type
001b, 010b
0
1
CKDIR
RTS0
CTS0
f1SIO or f2SIO
f8SIO
1/4
f32SIO
Receive
Transmit/
clock
receive
unit
Transmit
clock
TXD0
TXD
polarity
switching
circuit
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