Renesas M16C/64A Series User Manual page 18

22.2.6 PMCi Interrupt Source Register (PMCiINT) (i = 0, 1) ...................................................... 415
22.2.7 PMCi Header Pattern Set Register (MIN) (PMCiHDPMIN) (i = 0, 1)
PMCi Header Pattern Set Register (MAX) (PMCiHDPMAX) (i = 0, 1) ............................ 416
22.2.8 PMCi Data 0 Pattern Set Register (MIN) (PMCiD0PMIN) (i = 0, 1)
PMCi Data 0 Pattern Set Register (MAX) (PMCiD0PMAX) (i = 0, 1)
PMCi Data 1 Pattern Set Register (MIN) (PMCiD1PMIN) (i = 0, 1)
PMCi Data 1 Pattern Set Register (MAX) (PMCiD1PMAX) (i = 0, 1) .............................. 418
22.2.9 PMCi Measurements Register (PMCiTIM) (i = 0, 1) ........................................................ 419
22.2.10 PMC0 Receive Bit Count Register (PMC0RBIT) ............................................................. 419
22.2.11 PMC0 Receive Data Store Register i (PMC0DATi) (i = 0 to 5) ........................................ 420
22.2.12 PMC0 Compare Control Register (PMC0CPC) ............................................................... 421
22.2.13 PMC0 Compare Data Register (PMC0CPD) ................................................................... 422
22.3 Operations ................................................................................................................................ 423
Common Operations in Multiple Modes .......................................................................... 423
22.3.1
22.3.2 Pattern Match Mode (PMC0 and PMC1 Operate Independently) ................................... 425
22.3.3 Pattern Match Mode (Combined Operation of PMC0 and PMC1) .................................. 431
22.3.4 Input Capture Mode (Operating PMC0 and PMC1 Independently) ................................. 436
22.3.5 Input Capture Mode (Simultaneous Count Operation of PMC0 and PMC1) ................... 440
22.4 Interrupts................................................................................................................................... 443
22.5 Notes on Remote Control Signal Receiver ............................................................................... 446
22.5.1 Starting/Stopping PMCi ................................................................................................... 446
22.5.2 Reading the Register ....................................................................................................... 446
22.5.3 Rewriting the Register ..................................................................................................... 446
22.5.4 Combined Operation ....................................................................................................... 447
23. Serial Interface UARTi (i = 0 to 2, 5 to 7) ................................................................. 448
23.1 Introduction ............................................................................................................................... 448
23.2 Registers................................................................................................................................... 453
23.2.1 Peripheral Clock Select Register (PCLKR) ..................................................................... 455
23.2.2 UARTi Transmit/Receive Mode Register (UiMR) (i = 0 to 2, 5 to 7) ................................ 456
23.2.3 UARTi Bit Rate Register (UiBRG) (i = 0 to 2, 5 to 7) ....................................................... 457
23.2.4 UARTi Transmit Buffer Register (UiTB) (i = 0 to 2, 5 to 7) .............................................. 457
23.2.5 UARTi Transmit/Receive Control Register 0 (UiC0) (i = 0 to 2, 5 to 7) ........................... 458
23.2.6 UARTi Transmit/Receive Control Register 1 (UiC1) (i = 0 to 2, 5 to 7) ........................... 460
23.2.7 UARTi Receive Buffer Register (UiRB) (i = 0 to 2, 5 to 7) ............................................... 461
23.2.8 UART Transmit/Receive Control Register 2 (UCON) ...................................................... 463
23.2.9 UARTi Special Mode Register 4 (UiSMR4) (i = 0 to 2, 5 to 7) ......................................... 464
23.2.10 UARTi Special Mode Register 3 (UiSMR3) (i = 0 to 2, 5 to 7) ......................................... 466
23.2.11 UARTi Special Mode Register 2 (UiSMR2) (i = 0 to 2, 5 to 7) ......................................... 467
23.2.12 UARTi Special Mode Register (UiSMR) (i = 0 to 2, 5 to 7) .............................................. 468
23.3 Operations ................................................................................................................................ 469
23.3.1 Clock Synchronous Serial I/O Mode ............................................................................... 469
23.3.2 Clock Asynchronous Serial I/O (UART) Mode ................................................................ 477
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