Renesas M16C/64A Series User Manual page 514

M16C/64A Group
Example of Receive Timing When Character Bit Length is 8 Bits
Clock divided
by UiBRG
1
RE bit in
UiC1 register
0
RXDi
Transmit/
receive clock
1
RI bit in
UiC1 register
0
High
RTSi
Low
IR bit in 1
SiRIC register
0
i = 0 to 2, 5 to 7
The above assumes the following:
• The PRYE bit in the UiMR register is 0 (parity disabled).
• The STPS bit in the UiMR register is 0 (1 stop bit).
• The CRD bit in the UiC0 register is 0 ( CTSi / RTSi enabled)
• The CRS bit in the UiC0 register is 1 ( RTSi selected)
Figure 23.13 Receive Timing in UART Mode
R01UH0136EJ0210 Rev.2.10
Jul 31, 2012
Start bit
Sampled as low
Reception triggered when transmit/receive
clock is generated by falling edge of start bit.
23. Serial Interface UARTi (i = 0 to 2, 5 to 7)
(Parity Disabled, 1 Stop Bit)
D1
D0
Receive data taken in
Transferred from UARTi receive register
to UiRB register.
acknowledgment or by a program.
Stop bit
D7
Set to 0 by an interrupt request
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