Special Mode 2 - Renesas M16C/64A Series User Manual

M16C/64A Group
23.3.4

Special Mode 2

In special mode 2, the serial interface module allows serial communication between one master and
multiple slaves. The transmit/receive clock polarity and phase are selectable. Table 23.20 lists Special
Mode 2 Specifications.
Table 23.20 Special Mode 2 Specifications
Item
Data format
Transmit/receive clock
Transmit/receive control
Transmission start conditions
Reception start conditions
Interrupt request generation
timing
Error detection
Selectable functions
i = 0 to 2, 5 to 7
Note:
1. If an overrun error occurs, the received data of the UiRB register will be undefined. The IR bit in the SiRIC
register does not change.
R01UH0136EJ0210 Rev.2.10
Jul 31, 2012
Character data length: 8 bits
•
Master mode
The CKDIR bit in the UiMR register = 0 (internal clock):
fj = f1SIO, f2SIO, f8SIO, f32SIO
n: Setting value of UiBRG register 00h to FFh
Controlled by I/O ports
To start transmission, satisfy the following requirements:
•
The TE bit in the UiC1 register is 1 (transmission enabled)
•
The TI bit in the UiC1 register is 0 (data present in UiTB register)
To start reception, satisfy the following requirements:
•
The RE bit in the UiC1 register is 1 (reception enabled)
•
The TE bit is 1 (transmission enabled)
•
The TI bit is 0 (data present in the UiTB register)
For transmit interrupt, one of the following conditions can be selected
•
The UiIRS bit in the UiC1 or UCON register is 0 (transmit buffer empty):
When transferring data from the UiTB register to the UARTi transmit register (at
start of transmission)
•
The UiIRS bit is 1 (transfer completed):
When the serial interface completed sending data from the UARTi transmit register
For receive interrupt
•
When transferring data from the UARTi receive register to the UiRB register (at
completion of reception)
(1)
Overrun error
This error occurs if the serial interface starts receiving the next data before reading
the UiRB register and receives the 7th bit of the next data
•
CLK polarity selection
Whether transfer data is output/input at the rising or falling edge of the transfer clock
can be selected.
•
LBS first, MSB first selection
Whether to start sending/receiving data beginning with bit 0 or beginning with bit 7.
•
Continuous receive mode selection
Reception is enabled by reading the UiRB register
•
Serial data logic switching
Function to invert the logic value of the transmit/receive data.
•
Clock phase setting
Selectable from four combinations of transmit/receive clock polarities and phases.
23. Serial Interface UARTi (i = 0 to 2, 5 to 7)
Specification
fj
-------------------- -
(
2 n
)
+ 1
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