Renesas M16C/64A Series User Manual page 182

M16C/64A Group
11.3.5.8 External Bus Status When Internal Area is Accessed
Table 11.9 lists the External Bus Status When an Internal Area is Accessed. Figure 11.5 shows the
Typical Bus Timings When Accessing SFRs.
Table 11.9 External Bus Status When an Internal Area is Accessed
Item
A0 to A19
Read
D0 to
D15
Write
RD , WR , WRL , WRH
BHE
CS0 to CS3
ALE
(1) 1 Wait State (1φ + 1φ)
BCLK
Address
WR , WRL , WRH
(2) 2 Wait States (1φ + 2φ)
Address
WR , WRL , WRH
i = 0 to 3
A : Address
Figure 11.5 Typical Bus Timings When Accessing SFRs
R01UH0136EJ0210 Rev.2.10
Jul 31, 2012
SFR Accessed
Address output
High-impedance
Data output
RD , WR , WRL , WRH output
BHE output
High-level output
Low-level output
Bus cycle = 2φ
High
CSi
Data
RD
BCLK
High
CSi
Data
RD
RD : Read data WD : Write data
Internal ROM or RAM Accessed
Retain the last accessed address of external area or SFR
High-impedance
Undefined
High-level output
Retain the last accessed status of external area or SFRs
High-level output
Low-level output
Bus cycle = 2φ
A
WD
Bus cycle = 3φ
A
WD
A
RD
Bus cycle = 3φ
A
RD
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11. Bus