Renesas M16C/64A Series User Manual page 589

M16C/64A Group
25.3 Operations
25.3.1 Clock
Figure 25.5 shows the I
f1
Divide-by-2
S20 register
FASTMODE = 0
FASTMODE = 1
m: 2, 4, 8, 2.5, 3, 5, 6
(selectable by bits ICK1 to ICK0 in the S3D0 register and bits ICK4 to ICK2 in the S4D0 register)
n: 3 to 31 (value set to bits CCR4 to CCR0 in the S20 register)
Note:
1. Set the CPU clock to 100 kHz or lower in standard clock mode, and 400 kHz or lower in fast-mode.
2
Figure 25.5 I C-bus Interface Clock
25.3.1.1 fVIIC
fVIIC is determined by setting a combination of the following:
•
The frequency of peripheral clock f1
•
The PCLK0 bit in the PCLKR register
•
Bits ICK1 to ICK0 in the S3D0 register
•
Bits ICK4 to ICK2 in the S4D0 register
fVIIC stops when the ES0 bit in the S1D0 register is 0 (I
See Table 25.8 "I
R01UH0136EJ0210 Rev.2.10
Jul 31, 2012
2
C-bus Interface Clock.
PCLKR register
PCLK0 = 1
f1IIC
f2IIC
PCLK0 = 0
Divide-by-8
≠
5
Divide-by-4
= 5
Divide-by-2
CCR4 to CCR0
2
C-bus System Clock Select Bits" for details.
25. Multi-master I
System clock select
fIIC
circuit
Divide-by-m
Divide-by-n
2
C interface disabled).
2
C-bus Interface
2
I C-bus system clock
fVIIC
Clock control circuit
(1)
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