Renesas M16C/64A Series User Manual page 544

M16C/64A Group
23.3.6.2 Formats
Two formats are available: direct format and inverse format.
For direct format, set the PRYE bit in the U2MR register to 1 (parity enabled), the PRY bit to 1 (even
parity), the UFORM bit in the U2C0 register to 0 (LSB first), and the U2LCH bit in the U2C1 register to 0
(not inverted). When data is transmitted, data set in the U2TB register are transmitted with the even-
numbered parity, starting from D0. When data is received, the received data is stored in the U2RB
register, starting from D0. The even-numbered parity is used to determine whether a parity error occurs.
For inverted format, set the PRYE bit to 1, the PRY bit to 0 (odd parity), the UFORM bit to 1 (MSB first),
and the U2LCH bit to 1 (inverted). When data is transmitted, values set in the U2TB register are
logically inverted and are transmitted with the odd-numbered parity, starting from D7. When data is
received, the received data is logically inverted to be stored in the U2RB register, starting from D7. The
odd-numbered parity is used to determine whether a parity error occurs.
Figure 23.38 shows the SIM Interface Format.
(1) Direct format
Transmit/receive clock
TXD2
(2) Inverse format
Transmit/receive clock
TXD2
Figure 23.38 SIM Interface Format
R01UH0136EJ0210 Rev.2.10
Jul 31, 2012
High
Low
High
D0 D1
Low
High
Low
High
D7 D6
Low
23. Serial Interface UARTi (i = 0 to 2, 5 to 7)
D2 D3 D4 D5 D6
D5 D4 D3 D2 D1
D7 P
P: Even parity
D0 P
P: Odd parity
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