Renesas M16C/64A Series User Manual page 506

M16C/64A Group
23.3.1.1 CLK Polarity Select Function
Use the CKPOL bit in the UiC0 register (i = 0 to 2, 5 to 7) to select the transmit/receive clock polarity.
Figure 23.6 shows the Transmit/Receive Clock Polarity.
(1) CKPOL bit in the UiC0 register is 0 (transmit data is output at the falling edge and the
receive data is input at the rising edge of the transmit/receive clock)
CLKi
TXDi
RXDi
(2) CKPOL bit is 1 (transmit data is output at the rising edge and the receive data is input at
the falling edge of the transmit/receive clock)
CLKi
TXDi
RXDi
i = 0 to 2, 5 to 7
The above assumes the following:
• The CKDIR bit in the UiMR register is 0 (internal clock).
• The UFORM bit in the UiC0 register is 0 (LSB first).
• The UiLCH bit in the UiC1 register is 0 (not inverted).
Figure 23.6 Transmit/Receive Clock Polarity
R01UH0136EJ0210 Rev.2.10
Jul 31, 2012
D0 D1 D2 D3
D0 D1 D2 D3
D0 D1 D2 D3
D0 D1 D2 D3
23. Serial Interface UARTi (i = 0 to 2, 5 to 7)
A high-level signal is output from the CLKi
pin while no data transmitted/received.
D4 D5 D6 D7
D4 D5 D6 D7
A low-level signal is output from the CLKi
pin while no data transmitted/received.
D4 D5 D6 D7
D4 D5 D6 D7
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