Renesas M16C/64A Series User Manual page 845

REVISION HISTORY
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512, 513 23.5.2.2 Transmission and 23.5.2.3 Reception:
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514 to 515 23.5.3.3 Low/High-level Input Voltage and Low-level Output Voltage to 23.5.3.7 Requirements to
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Serial Interface SI/O3 and SI/O4
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Multi-Master I
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M16C/64A Group Hardware Manual
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Table 23.18 I C Mode Functions:
• Deleted the description that the I
UiSMR3 register.
• Deleted "CKPH = 0" fields.
• Changed the IICM2 = 1 column in the Transmission, NACK interrupt and Timing for transferring
data from UART reception shift register to UiRB register rows.
• Deleted the Noise filter width row.
• Changed the IICM2 = 1 column in the Read received data row.
• Added note 3.
Figure 23.20 Transfer to UiRB Register and Interrupt Timing:
Deleted "(1) IICM2 = 0 (ACK and NACK interrupts), CKPH = 0 (no clock delay)" and "(3) IICM2 = 1
(UART transmit/receive interrupt), CKPH = 0".
23.3.3.1 Detecting Start and Stop Conditions:
• Changed lines 1 and 2.
• Added the last 3 lines.
Figure 23.21 Detecting Start and Stop Conditions: Rewritten.
23.3.3.2 Generating Start and Stop Conditions: Changed the title. from "Outputting Start and Stop
Conditions".
Figure 23.22 STSPSEL Bit Functions: Rewritten.
Figure 23.23 Register Setting Procedures for Condition Generation: Added.
23.3.3.3 Arbitration: Rewritten.
23.3.3.4 SCL Control and Clock Synchronization: Added, including Figure 23.24 and Figure 23.25.
23.3.3.5 SCL Clock Frequency: Added, including Figure 23.26.
23.3.3.6 SDA Output Control: Rewritten and added Figure 23.27 and Figure 23.28.
23.3.3.7 SDA Digital Delay: Added, including Figure 23.28.
23.3.3.8 SDA Input: Rewritten and added Figure 23.30 and Figure 23.31.
23.3.3.9 ACK and NACK: Rewritten.
23.3.3.10 Initialization of Transmission/Reception: Added the last 2 lines.
Table 23.20 Special Mode 2 Specifications:
• Deleted the description of slave mode in the Transmit/receive clock row.
• Deleted note 1.
Figure 23.32 Serial Bus Communication Control Example in Special Mode 2 (UART2):
Changed the pin names in the MCU (slave).
Table 23.21 I/O Pin Functions in Special Mode 2: Deleted Input field in the CLKi row.
Table 23.22 Registers Used and Settings in Special Mode 2:
Deleted "in master mode or 1 in slave mode" in the CKDIR bit row.
Table 23.24 SIM Mode Specifications: Changed note 2.
Figure 23.35 Transmit/Receive Timing in SIM Mode:
Added the timing when the IR bit in the S2TIC register becomes 1.
23.4.1 Interrupt Related Registers: Changed the description about Special mode 4 (SIM mode).
Changed the explanations about the external clock level into bullet lists.
23.5.3.1 Generating Start and Stop Conditions: Added the technical update number.
Start Transmission/Reception in Slave Mode: Added.
23.5.4 Special Mode 4 (SIM Mode):
• Added the technical update number.
• Changed the conditions to generate a transmit interrupt request.
24.5.5 Pin Function Switch When Using the Internal Clock: Added the technical update number.
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C-bus Interface
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Table 25.2 I C Interface Detection Function:
Added "SCLMM pin" to the Arbitration lost detection row.
25.2.4 I2C0 Control Register 0 (S1D0):
• Corrected the typo "00X0 0000b" to "00h" in the register diagram.
• Deleted "stop condition" from explanation of bits BC2 to BC0.
C - 12
Description
Summary
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C mode functions vary depending on the CKPH bit in the