Page 1 User’s Manual 78K0R/KF3 16-bit Single-Chip Microcontrollers μ PD78F1152, 78F1152A, 78F1152A(A) μ PD78F1153, 78F1153A, 78F1153A(A) μ PD78F1154, 78F1154A, 78F1154A(A) μ PD78F1155, 78F1155A, 78F1155A(A) μ PD78F1156, 78F1156A, 78F1156A(A) Document No. U17893EJ8V0UD00 (8th edition) Date Published September 2009 NS 2006 Printed in Japan...
Page 2 [MEMO] User’s Manual U17893EJ8V0UD...
Page 3 NOTES FOR CMOS DEVICES VOLTAGE APPLICATION WAVEFORM AT INPUT PIN Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the CMOS device stays in the area between V (MAX) and V (MIN) due to noise, etc., the device may malfunction.
Page 4 Windows and Windows NT are registered trademarks or trademarks of Microsoft Corporation in the United States and/or other countries. PC/AT is a trademark of International Business Machines Corporation. EEPROM is a trademark of NEC Electronics Corporation. SuperFlash is a registered trademark of Silicon Storage Technology, Inc. in several countries including the United States and Japan.
Page 5 This manual is intended to give users an understanding of the functions described in the Organization below. Organization The 78K0R/KF3 manual is separated into two parts: this manual and the instructions edition (common to the 78K0R Microcontroller Series). 78K0R/KF3 78K0R Microcontroller User’s Manual...
Page 6 The related documents indicated in this publication may include preliminary versions. However, preliminary versions are not marked as such. Documents Related to Devices Document Name Document No. 78K0R/KF3 User’s Manual This manual 78K0R Microcontroller Instructions User’s Manual U17792E Note 78K0R Microcontroller Self Programming Library Type01 User’s Manual U18706E Note This document is under engineering management.
Page 7 Documents Related to Flash Memory Programming Document Name Document No. PG-FP4 Flash Memory Programmer User’s Manual U15260E PG-FP5 Flash Memory Programmer U18865E Caution The related documents listed above are subject to change without notice. Be sure to use the latest version of each document when designing.
Page 8: Table Of Contents
CONTENTS CHAPTER 1 OUTLINE ..........................17 μ 1.1 Differences Between Conventional-Specification Products ( PD78F115x) and Expanded- μ Specification Products ( PD78F115xA)..................17 1.2 Features............................18 1.3 Applications ..........................19 1.4 Ordering Information........................19 1.5 Pin Configuration (Top View) ...................... 20 1.6 78K0R/Kx3 Microcontroller Lineup.....................
Page 9 3.1.5 Extended special function register (2nd SFR: 2nd Special Function Register) area ......59 3.1.6 Data memory addressing ........................60 3.2 Processor Registers ........................65 3.2.1 Control registers..........................65 3.2.2 General-purpose registers ........................67 3.2.3 ES and CS registers .........................69 3.2.4 Special function registers (SFRs)......................70 3.2.5 Extended special function registers (2nd SFRs: 2nd Special Function Registers)......76 3.3 Instruction Address Addressing ....................
Page 10 CHAPTER 5 CLOCK GENERATOR ....................151 5.1 Functions of Clock Generator....................151 5.2 Configuration of Clock Generator .................... 152 5.3 Registers Controlling Clock Generator..................154 5.4 System Clock Oscillator ......................168 5.4.1 X1 oscillator.............................168 5.4.2 XT1 oscillator ..........................168 5.4.3 Internal high-speed oscillator ......................171 5.4.4 Internal low-speed oscillator......................171 5.4.5 Prescaler ............................171 5.5 Clock Generator Operation .......................
Page 11 6.8.2 Operation as one-shot pulse output function...................259 6.8.3 Operation as multiple PWM output function ..................266 CHAPTER 7 REAL-TIME COUNTER ....................273 7.1 Functions of Real-Time Counter....................273 7.2 Configuration of Real-Time Counter ..................273 7.3 Registers Controlling Real-Time Counter ................275 7.4 Real-Time Counter Operation ....................
Page 12 10.5.4 Procedures for using temperature sensors ...................334 10.6 How to Read A/D Converter Characteristics Table............... 337 10.7 Cautions for A/D Converter ..................... 339 CHAPTER 11 D/A CONVERTER ......................344 11.1 Function of D/A Converter....................... 344 11.2 Configuration of D/A Converter ....................344 11.3 Registers Used in D/A Converter....................
Page 13 12.8 Relationship Between Register Settings and Pins ............... 487 CHAPTER 13 SERIAL INTERFACE IIC0 ................... 494 13.1 Functions of Serial Interface IIC0 ................... 494 13.2 Configuration of Serial Interface IIC0..................497 13.3 Registers to Controlling Serial Interface IIC0................ 500 13.4 I C Bus Mode Functions ......................
Page 14 15.5.5 UART consecutive reception + ACK transmission ................589 15.5.6 Holding DMA transfer pending by DWAITn ...................591 15.5.7 Forced termination by software .....................592 15.6 Cautions on Using DMA Controller ..................594 CHAPTER 16 INTERRUPT FUNCTIONS .................... 597 16.1 Interrupt Function Types ......................597 16.2 Interrupt Sources and Configuration ..................
Page 15 24.9.1 Boot swap function........................696 24.9.2 Flash shield window function ......................698 CHAPTER 25 ON-CHIP DEBUG FUNCTION ..................699 25.1 Connecting QB-MINI2 to 78K0R/KF3..................699 25.2 On-Chip Debug Security ID ..................... 700 25.3 Securing of user resources..................... 700 CHAPTER 26 BCD CORRECTION CIRCUIT ..................702 26.1 BCD Correction Circuit Function....................
Page 16 CHAPTER 27 INSTRUCTION SET......................705 27.1 Conventions Used in Operation List ..................706 27.1.1 Operand identifiers and specification methods................706 27.1.2 Description of operation column....................707 27.1.3 Description of flag operation column .....................708 27.1.4 PREFIX Instruction........................708 27.2 Operation List ........................... 709 CHAPTER 28 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS) ........726 CHAPTER 29 ELECTRICAL SPECIFICATIONS ((A) GRADE PRODUCTS) ........
Page 17: Chapter 1 Outline
μ 1.1 Differences Between Conventional-Specification Products ( PD78F115x) and Expanded- μ Specification Products ( PD78F115xA) This manual describes the functions of the 78K0R/KF3 microcontroller products with conventional specifications μ μ PD78F115x) and expanded specifications ( PD78F115xA). μ The differences between the conventional-specification products ( PD78F115x) and expanded-specification μ...
Page 18: Features
CHAPTER 1 OUTLINE 1.2 Features μ Minimum instruction execution time can be changed from high speed (0.05 s: @ 20 MHz operation with high- μ speed system clock) to ultra low-speed (61 s: @ 32.768 kHz operation with subsystem clock) General-purpose register: 8 bits ×...
Page 19: Applications
CHAPTER 1 OUTLINE 1.3 Applications Home appliances • Laser printer motors • Clothes washers • Air conditioners • Refrigerators Home audio systems Digital cameras, digital video cameras 1.4 Ordering Information • Flash memory version (lead-free products) Quality Grade Part Number Package μ...
Page 20: Pin Configuration (Top View)
CHAPTER 1 OUTLINE 1.5 Pin Configuration (Top View) • 80-pin plastic LQFP (14 × 14) • 80-pin plastic LQFP (fine pitch) (12 × 12) 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 P120/INTP0/EXLVI REF0...
Page 21 CHAPTER 1 OUTLINE Pin Identification ANI0 to ANI7: Analog input REGC: Regulator capacitance ANO0, ANO1: Analog output RESET: Reset Analog reference voltage RTC1HZ: Real-time counter correction clock REF0, REF1 (1 Hz) output Analog ground RTCCL: Real-time counter clock (32 kHz Power supply for port original oscillation) output Ground for port...
Page 22: 78K0R/Kx3 Microcontroller Lineup
CHAPTER 1 OUTLINE 1.6 78K0R/Kx3 Microcontroller Lineup 78K0R/KE3 78K0R/KF3 78K0R/KG3 78K0R/KH3 78K0R/KJ3 64 Pins 80 Pins 100 Pins 128 Pins 144 Pins μ μ μ − − 512 KB 30 KB PD78F1168 PD78F1178 PD78F1188A μ μ PD78F1168A PD78F1178A μ μ...
Page 23: Block Diagram
CHAPTER 1 OUTLINE 1.7 Block Diagram TIMER ARRAY PORT 0 P00 to P06 UNIT (8ch) TI00/P00 TO00/P01 PORT 1 P10 to P17 TI01/TO01/P16 PORT 2 P20 to P27 TI02/TO02/P17 PORT 3 P30, P31 TI03/TO03/P31 PORT 4 P40 to P47 TI04/TO04/P42 PORT 5 P50 to P55 TI05/TO05/P05...
Page 24: Outline Of Functions
CHAPTER 1 OUTLINE 1.8 Outline of Functions (1/2) μ μ μ μ μ Item PD78F1152, PD78F1153, PD78F1154, PD78F1155, PD78F1156, μ μ μ μ μ PD78F1152A PD78F1153A PD78F1154A PD78F1155A PD78F1156A Internal Flash memory 64 KB 96 KB 128 KB 192 KB 256 KB memory (self-programming...
Page 25 CHAPTER 1 OUTLINE (2/2) μ μ μ μ μ Item PD78F1152, PD78F1153, PD78F1154, PD78F1155, PD78F1156, μ μ μ μ μ PD78F1152A PD78F1153A PD78F1154A PD78F1155A PD78F1156A • UART supporting LIN-bus: 1 channel Serial interface • CSI: 2 channels/UART: 1 channel • CSI: 1 channel/UART: 1 channel/simplified I C: 1 channel •...
Page 26: Chapter 2 Pin Functions
CHAPTER 2 PIN FUNCTIONS 2.1 Pin Function List There are four types of pin I/O buffer power supplies: AV , AV , EV , and V . The relationship between REF0 REF1 these power supplies and the pins is shown below. Table 2-1.
Page 27 CHAPTER 2 PIN FUNCTIONS (1) Port functions (1/2) Function Name Function After Reset Alternate Function Port 0. Input port TI00 7-bit I/O port. TO00 Input of P03 and P04 can be set to TTL input buffer. SO10/TxD1 Output of P02 to P04 can be set to N-ch open-drain output SI10/RxD1/SDA10 tolerance).
Page 28 CHAPTER 2 PIN FUNCTIONS (1) Port functions (2/2) Function Name Function After Reset Alternate Function Port 6. Input port SCL0 8-bit I/O port. SDA0 Output of P60 to P63 can be set to N-ch open-drain output (6 − V tolerance). −...
Page 29 CHAPTER 2 PIN FUNCTIONS (2) Non-port functions (1/3) Function Name Function After Reset Alternate Function ANI0 to ANI7 Input A/D converter analog input Digital input P20 to P27 port ANO0 Output D/A converter analog output Input port P110 ANO1 Output D/A converter analog output Input port P111...
Page 30 CHAPTER 2 PIN FUNCTIONS (2) Non-port functions (2/3) Function Name Function After Reset Alternate Function SCL0 Clock input/output for I Input port SCL10 Clock input/output for simplified I Input port P04/SCK10 SCL20 Clock input/output for simplified I Input port P142/SCK20 SDA0 Serial data I/O for I Input port...
Page 31 CHAPTER 2 PIN FUNCTIONS (2) Non-port functions (3/3) Function Name Function After Reset Alternate Function − − − Positive power supply (P121 to P124 and other than ports (excluding RESET and FLMD0 pins)) − − − Positive power supply for ports (other than P20 to P27, P110, P111 and P121 to P124) and RESET and FLMD0 pins •...
Page 32: Description Of Pin Functions
CHAPTER 2 PIN FUNCTIONS 2.2 Description of Pin Functions 2.2.1 P00 to P06 (port 0) P00 to P06 function as a 7-bit I/O port. These pins also function as timer I/O, serial interface data I/O, and clock I/O. Input to the P03 and P04 pins can be specified through a normal input buffer or a TTL input buffer in 1-bit units, using port input mode register 0 (PIM0).
Page 33: P10 To P17 (Port 1)
CHAPTER 2 PIN FUNCTIONS Caution To use P02/SO10/TxD1 and P04/SCK10/SCL10 as general-purpose ports, set serial communication operation setting register 02 (SCR02) to the default status (0087H). In addition, clear port output mode register 0 (POM0) to 00H. 2.2.2 P10 to P17 (port 1) P10 to P17 function as an 8-bit I/O port.
Page 34: P20 To P27 (Port 2)
CHAPTER 2 PIN FUNCTIONS TO01, TO02 These are the timer output pins of 16-bit timers 01 and 02. INTP5 This is an external interrupt request input pin for which the valid edge (rising edge, falling edge, or both rising and falling edges) can be specified. (k) RTCDIV This is a real-time counter clock (32 kHz, divided) output pin.
Page 35: P40 To P47 (Port 4)
CHAPTER 2 PIN FUNCTIONS (2) Control mode P30 and P31 function as external interrupt request input, timer I/O, and real-time counter correction clock output. (a) INTP3, INTP4 These are the external interrupt request input pins for which the valid edge (rising edge, falling edge, or both rising and falling edges) can be specified.
Page 36: P50 To P55 (Port 5)
CHAPTER 2 PIN FUNCTIONS (b) TOOL1 This is a clock output pin for a debugger. When the on-chip debug function is used, P41/TOOL1 pin can be used as follows by the mode setting on the debugger. 1-line mode: can be used as a port (P41). 2-line mode: used as a TOOL1 pin and cannot be used as a port (P41).
Page 37: P60 To P67 (Port 6)
CHAPTER 2 PIN FUNCTIONS (2) Control mode P50, P51 function as external interrupt request input. (a) INTP1, INTP2 These are the external interrupt request input pins for which the valid edge (rising edge, falling edge, or both rising and falling edges) can be specified. 2.2.7 P60 to P67 (port 6) P60 to P67 function as an 8-bit I/O port.
Page 38: P90 (Port 9)
CHAPTER 2 PIN FUNCTIONS 2.2.9 P90 (port 9) P90 function as an 1-bit I/O port. The port mode can be specified in 1-bit units. (1) Port mode P90 function as an 1-bit I/O port. P90 can be set to input or output port in 1-bit units using port mode register 9 (PM9).
Page 39: P130 (Port 13)
CHAPTER 2 PIN FUNCTIONS (e) XT1, XT2 These are the pins for connecting a resonator for subsystem clock. 2.2.12 P130 (port 13) P130 functions as a 1-bit output port. Remark When the device is reset, P130 outputs a low level. Therefore, to output a high level from P130 before the device is reset, the output signal of P130 can be used as a pseudo reset signal of the CPU (see the figure for Remark in 4.2.12 Port 13).
Page 40: Av Ref0
CHAPTER 2 PIN FUNCTIONS (g) SCK20 This is a serial clock I/O pin of serial interface CSI20. (h) TxD2 This is a serial data output pin of serial interface UART2. RxD2 This is a serial data input pin of serial interface UART2. SDA20 This is a serial data I/O pin of serial interface for simplified I (k) SCL20...
Page 41: Av Ref1
CHAPTER 2 PIN FUNCTIONS 2.2.15 AV REF1 This is the D/A converter reference voltage input pin and the positive power supply pin of P110, P111, and D/A converter. The voltage that can be supplied to AV varies as follows, depending on whether P110/ANI0, P111/ANO1 are REF1 used as digital I/Os or analog inputs.
Page 42: Vdd , Ev Dd
CHAPTER 2 PIN FUNCTIONS 2.2.19 V , EV is the positive power supply pin for P121 to P124 and pins other than ports (excluding the RESET and FLMD0 pins). is the positive power supply pin for ports other than P20 to P27, P110, P111 and P121 to P124 as well as for the RESET and FLMD0 pins.
Page 43: Pin I/O Circuits And Recommended Connection Of Unused Pins
CHAPTER 2 PIN FUNCTIONS 2.3 Pin I/O Circuits and Recommended Connection of Unused Pins Table 2-4 shows the types of pin I/O circuits and the recommended connections of unused pins. Table 2-4. Connection of Unused Pins (1/3) Pin Name I/O Circuit Type Recommended Connection of Unused Pins P00/TI00 Input:...
Page 44 CHAPTER 2 PIN FUNCTIONS Table 2-4. Connection of Unused Pins (2/3) Pin Name I/O Circuit Type Recommended Connection of Unused Pins P50/INTP1 Input: Independently connect to EV or EV via a resistor. Output: Leave open. P51/INTP2 P52 to P55 5-AG P60/SCL0 13-R Input:...
Page 45 CHAPTER 2 PIN FUNCTIONS Table 2-4. Connection of Unused Pins (3/3) Pin Name I/O Circuit Type Recommended Connection of Unused Pins − − Make this pin the same potential as EV or V REF1 See 2.2.15 AV when using P110 and P111. REF1 −...
Page 46 CHAPTER 2 PIN FUNCTIONS Figure 2-1. Pin I/O Circuit List (1/2) Type 2 Type 5-AG Pull-up P-ch enable Data P-ch IN/OUT Output N-ch Schmitt-triggered input with hysteresis characteristics disable Input enable Type 2-W Type 5-AN Pull-up P-ch enable pull-up P-ch enable Data P-ch...
Page 47 CHAPTER 2 PIN FUNCTIONS Figure 2-1. Pin I/O Circuit List (2/2) Type 11-G Type 13-R REF0 Data P-ch IN/OUT IN/OUT Output N-ch disable Data N-ch Output disable P-ch Comparator N-ch Series resistor string voltage Input enable Type 12-G Type 37-B REF1 Data P-ch...
Page 48: Chapter 3 Cpu Architecture
CHAPTER 3 CPU ARCHITECTURE 3.1 Memory Space Products in the 78K0R/KF3 can access a 1 MB memory space. Figures 3-1 to 3-5 show the memory maps. μ Figure 3-1. Memory Map ( PD78F1152, 78F1152A) F F F F F H...
Page 49 CHAPTER 3 CPU ARCHITECTURE μ Figure 3-2. Memory Map ( PD78F1153, 78F1153A) F F F F F H 1 7 F F F H Special function register (SFR) 256 bytes F F F 0 0 H F F E F F H General-purpose register 32 bytes F F E E 0 H...
Page 50 CHAPTER 3 CPU ARCHITECTURE μ Figure 3-3. Memory Map ( PD78F1154, 78F1154A) F F F F F H 1 F F F F H Special function register (SFR) 256 bytes F F F 0 0 H F F E F F H General-purpose register 32 bytes F F E E 0 H...
Page 51 CHAPTER 3 CPU ARCHITECTURE μ Figure 3-4. Memory Map ( PD78F1155, 78F1155A) F F F F F H 2 F F F F H Special function register (SFR) 256 bytes F F F 0 0 H F F E F F H General-purpose register 32 bytes F F E E 0 H...
Page 52 CHAPTER 3 CPU ARCHITECTURE μ Figure 3-5. Memory Map ( PD78F1156, 78F1156A) F F F F F H 3 F F F F H Special function register (SFR) 256 bytes F F F 0 0 H F F E F F H General-purpose register 32 bytes F F E E 0 H...
Page 53 CHAPTER 3 CPU ARCHITECTURE Remark The flash memory is divided into blocks (one block = 2 KB). For the address values and block numbers, see Table 3-1 Correspondence Between Address Values and Block Numbers in Flash Memory. 3 F F F F H Block 7FH 3 F 8 0 0 H 3 F 7 F F H...
Page 54 CHAPTER 3 CPU ARCHITECTURE Correspondence between the address values and block numbers in the flash memory are shown below. Table 3-1. Correspondence Between Address Values and Block Numbers in Flash Memory Address Value Block Address Value Block Address Value Block Address Value Block Number...
Page 55: Internal Program Memory Space
3.1.1 Internal program memory space The internal program memory space stores the program and table data. Normally, it is addressed with the program counter (PC). 78K0R/KF3 products incorporate internal ROM (flash memory), as shown below. Table 3-2. Internal ROM Capacity Part Number...
Page 56 CHAPTER 3 CPU ARCHITECTURE Table 3-3. Vector Table Vector Table Address Interrupt Source Vector Table Address Interrupt Source 00000H RESET input, POC, LVI, WDT, 0002CH INTTM00 TRAP 0002EH INTTM01 00004H INTWDTI 00030H INTTM02 00006H INTLVI 00032H INTTM03 00008H INTP0 00034H INTAD 0000AH INTP1...
Page 57: Mirror Area
CHAPTER 3 CPU ARCHITECTURE 3.1.2 Mirror area μ PD78F1152 and 78F1152A mirror the data flash area of 00000H to 0FFFFH, to F0000H to FFFFFH. μ PD78F1153, 78F1153A, 78F1154, 78F1154A, 78F1155, 78F1155A, 78F1156, 78F1156A mirror the data flash area of 00000H to 0FFFFH or 10000H to 1FFFFH, to F0000H to FFFFFH (the data flash area to be mirrored is set by the processor mode control register (PMC)).
Page 58: Internal Data Memory Space
μ 3. When the PD78F1152, 78F1152A is used, be sure to set bit 0 (MAA) of this register to 0. 3.1.3 Internal data memory space 78K0R/KF3 products incorporate the following RAMs. Table 3-4. Internal RAM Capacity Part Number Internal RAM μ...
Page 59: Special Function Register (Sfr) Area
CHAPTER 3 CPU ARCHITECTURE 3.1.4 Special function register (SFR) area On-chip peripheral hardware special function registers (SFRs) are allocated in the area FFF00H to FFFFFH (see Table 3-5 in 3.2.4 Special function registers (SFRs)). Caution Do not access addresses to which SFRs are not assigned. 3.1.5 Extended special function register (2nd SFR: 2nd Special Function Register) area On-chip peripheral hardware special function registers (2nd SFRs) are allocated in the area F0000H to F07FFH (see Table 3-6 in 3.2.5 Extended Special function registers (2nd SFRs: 2nd Special Function Registers)).
Page 60: Data Memory Addressing
Several addressing modes are provided for addressing the memory relevant to the execution of instructions for the 78K0R/KF3, based on operability and other considerations. For areas containing data memory in particular, special addressing methods designed for the functions of special function registers (SFR) and general-purpose registers are available for use.
Page 61 CHAPTER 3 CPU ARCHITECTURE μ <R> Figure 3-8. Correspondence Between Data Memory and Addressing ( PD78F1153, 78F1153A) F F F F F H SFR addressing Special function register (SFR) F F F 2 0 H 256 bytes F F F 1 F H F F F 0 0 H Short direct F F E F F H...
Page 62 CHAPTER 3 CPU ARCHITECTURE μ <R> Figure 3-9. Correspondence Between Data Memory and Addressing ( PD78F1154, 78F1154A) F F F F F H SFR addressing Special function register (SFR) F F F 2 0 H 256 bytes F F F 1 F H F F F 0 0 H F F E F F H General-purpose register...
Page 63 CHAPTER 3 CPU ARCHITECTURE μ <R> Figure 3-10. Correspondence Between Data Memory and Addressing ( PD78F1155, 78F1155A) F F F F F H SFR addressing Special function register (SFR) F F F 2 0 H F F F 1 F H 256 bytes F F F 0 0 H F F E F F H...
Page 64 CHAPTER 3 CPU ARCHITECTURE μ Figure 3-11. Correspondence Between Data Memory and Addressing ( PD78F1156, 78F1156A) <R> F F F F F H SFR addressing Special function register (SFR) F F F 2 0 H F F F 1 F H 256 bytes F F F 0 0 H F F E F F H...
Page 65: Processor Registers
CHAPTER 3 CPU ARCHITECTURE 3.2 Processor Registers The 78K0R/KF3 products incorporate the following processor registers. 3.2.1 Control registers The control registers control the program sequence, statuses and stack memory. The control registers consist of a program counter (PC), a program status word (PSW) and a stack pointer (SP).
Page 66 CHAPTER 3 CPU ARCHITECTURE (d) Auxiliary carry flag (AC) If the operation result has a carry from bit 3 or a borrow at bit 3, this flag is set (1). It is reset (0) in all other cases. (e) In-service priority flags (ISP1, ISP0) This flag manages the priority of acknowledgeable maskable vectored interrupts.
Page 67: General-Purpose Registers
CHAPTER 3 CPU ARCHITECTURE Figure 3-15. Data to Be Saved to Stack Memory PUSH PSW instruction PUSH rp instruction SP←SP−2 SP←SP−2 ↑ ↑ Register pair lower SP−2 SP−2 ↑ ↑ SP−1 SP−1 Register pair higher ↑ ↑ → → Interrupt, BRK instruction CALL, CALLT instructions (4-byte stack) (4-byte stack)
Page 68 CHAPTER 3 CPU ARCHITECTURE Figure 3-16. Configuration of General-Purpose Registers (a) Function name 16-bit processing 8-bit processing FFEFFH Register bank 0 FFEF8H Register bank 1 FFEF0H Register bank 2 FFEE8H Register bank 3 FFEE0H (b) Absolute name 16-bit processing 8-bit processing FFEFFH Register bank 0 FFEF8H...
Page 69: And Cs Registers
CHAPTER 3 CPU ARCHITECTURE 3.2.3 ES and CS registers The ES register is used for data access and the CS register is used to specify the higher address when a branch instruction is executed. The default value of the ES register after reset is 0FH, and that of the CS register is 00H. Figure 3-17.
Page 70: Special Function Registers (Sfrs)
CHAPTER 3 CPU ARCHITECTURE 3.2.4 Special function registers (SFRs) Unlike a general-purpose register, each SFR has a special function. SFRs are allocated to the FFF00H to FFFFFH area. SFRs can be manipulated like general-purpose registers, using operation, transfer, and bit manipulation instructions.
Page 71 CHAPTER 3 CPU ARCHITECTURE Table 3-5. SFR List (1/5) Address Special Function Register (SFR) Name Symbol Manipulable Bit Range After Reset 1-bit 8-bit 16-bit √ √ − FFF00H Port register 0 √ √ − FFF01H Port register 1 √ √ −...
Page 72 CHAPTER 3 CPU ARCHITECTURE Table 3-5. SFR List (2/5) Address Special Function Register (SFR) Name Symbol Manipulable Bit Range After Reset 1-bit 8-bit 16-bit √ √ − FFF30H A/D converter mode register √ √ − FFF31H Analog input channel specification register √...
Page 73 CHAPTER 3 CPU ARCHITECTURE Table 3-5. SFR List (3/5) Address Special Function Register (SFR) Name Symbol Manipulable Bit Range After Reset 1-bit 8-bit 16-bit − − √ FFF90H Sub-count register RSUBC 0000H FFF91H − √ − FFF92H Second count register −...
Page 74 CHAPTER 3 CPU ARCHITECTURE Table 3-5. SFR List (4/5) Address Special Function Register (SFR) Name Symbol Manipulable Bit Range After Reset 1-bit 8-bit 16-bit − √ − FFFB0H DMA SFR address register 0 DSA0 − √ − FFFB1H DMA SFR address register 1 DSA1 −...
Page 75 CHAPTER 3 CPU ARCHITECTURE Table 3-5. SFR List (5/5) Address Special Function Register (SFR) Name Symbol Manipulable Bit Range After Reset 1-bit 8-bit 16-bit √ √ √ FFFEEH Priority specification flag register 11L PR11L PR11 √ √ FFFEFH Priority specification flag register 11H PR11H −...
Page 76: Extended Special Function Registers (2Nd Sfrs: 2Nd Special Function Registers)
CHAPTER 3 CPU ARCHITECTURE 3.2.5 Extended special function registers (2nd SFRs: 2nd Special Function Registers) Unlike a general-purpose register, each extended SFR (2nd SFR) has a special function. Extended SFRs are allocated to the F0000H to F07FFH area. SFRs other than those in the SFR area (FFF00H to FFFFFH) are allocated to this area.
Page 77 CHAPTER 3 CPU ARCHITECTURE Table 3-6. Extended SFR (2nd SFR) List (1/5) Address Special Function Register (SFR) Name Symbol Manipulable Bit Range After Reset 1-bit 8-bit 16-bit − √ − F0017H A/D port configuration register ADPC √ √ − F0030H Pull-up resistor option register 0 √...
Page 78 CHAPTER 3 CPU ARCHITECTURE Table 3-6. Extended SFR (2nd SFR) List (2/5) Address Special Function Register (SFR) Name Symbol Manipulable Bit Range After Reset 1-bit 8-bit 16-bit − − √ F0110H Serial mode register 00 SMR00 0020H F0111H − − √...
Page 79 CHAPTER 3 CPU ARCHITECTURE Table 3-6. Extended SFR (2nd SFR) List (3/5) Address Special Function Register (SFR) Name Symbol Manipulable Bit Range After Reset 1-bit 8-bit 16-bit − √ √ F014CH Serial flag clear trigger register 12 SIR12L SIR12 0000H −...
Page 80 CHAPTER 3 CPU ARCHITECTURE Table 3-6. Extended SFR (2nd SFR) List (4/5) Address Special Function Register (SFR) Name Symbol Manipulable Bit Range After Reset 1-bit 8-bit 16-bit − − √ F0188H Timer counter register 04 TCR04 FFFFH F0189H − − √...
Page 81 CHAPTER 3 CPU ARCHITECTURE Table 3-6. Extended SFR (2nd SFR) List (5/5) Address Special Function Register (SFR) Name Symbol Manipulable Bit Range After Reset 1-bit 8-bit 16-bit √ √ √ F01B0H Timer enable status register 0 TE0L 0000H − − −...
Page 82: Instruction Address Addressing
CHAPTER 3 CPU ARCHITECTURE 3.3 Instruction Address Addressing 3.3.1 Relative addressing [Function] Relative addressing stores in the program counter (PC) the result of adding a displacement value included in the instruction word (signed complement data: −128 to +127 or −32768 to +32767) to the program counter (PC)’s value (the start address of the next instruction), and specifies the program address to be used as the branch destination.
Page 83 CHAPTER 3 CPU ARCHITECTURE 3.3.3 Table indirect addressing [Function] Table indirect addressing specifies a table address in the CALLT table area (0080H to 00BFH) with the 5-bit immediate data in the instruction word, stores the contents at that table address and the next address in the program counter (PC) as 16-bit data, and specifies the program address.
Page 84: Register Direct Addressing
CHAPTER 3 CPU ARCHITECTURE 3.3.4 Register direct addressing [Function] Register direct addressing stores in the program counter (PC) the contents of a general-purpose register pair (AX/BC/DE/HL) and CS register of the current register bank specified with the instruction word as 20-bit data, and specifies the program address.
Page 85: Addressing For Processing Data Addresses
CHAPTER 3 CPU ARCHITECTURE 3.4 Addressing for Processing Data Addresses 3.4.1 Implied addressing [Function] Instructions for accessing registers (such as accumulators) that have special functions are directly specified with the instruction word, without using any register specification field in the instruction word. [Operand format] Because implied addressing can be automatically employed with an instruction, no particular operand format is necessary.
Page 86: Direct Addressing
CHAPTER 3 CPU ARCHITECTURE 3.4.3 Direct addressing [Function] Direct addressing uses immediate data in the instruction word as an operand address to directly specify the target address. [Operand format] Identifier Description ADDR16 Label or 16-bit immediate data (only the space from F0000H to FFFFFH is specifiable) ES: ADDR16 Label or 16-bit immediate data (higher 4-bit addresses are specified by the ES register) Figure 3-25.
Page 87: Short Direct Addressing
CHAPTER 3 CPU ARCHITECTURE 3.4.4 Short direct addressing [Function] Short direct addressing directly specifies the target addresses using 8-bit data in the instruction word. This type of addressing is applied only to the space from FFE20H to FFF1FH. [Operand format] Identifier Description SADDR...
Page 88: Sfr Addressing
CHAPTER 3 CPU ARCHITECTURE 3.4.5 SFR addressing [Function] SFR addressing directly specifies the target SFR addresses using 8-bit data in the instruction word. This type of addressing is applied only to the space from FFF00H to FFFFFH. [Operand format] Identifier Description SFR name SFRP...
Page 89: Register Indirect Addressing
CHAPTER 3 CPU ARCHITECTURE 3.4.6 Register indirect addressing [Function] Register indirect addressing directly specifies the target addresses using the contents of the register pair specified with the instruction word as an operand address. [Operand format] Identifier Description − [DE], [HL] (only the space from F0000H to FFFFFH is specifiable) −...
Page 90: Based Addressing
CHAPTER 3 CPU ARCHITECTURE 3.4.7 Based addressing [Function] Based addressing uses the contents of a register pair specified with the instruction word as a base address, and 8-bit immediate data or 16-bit immediate data as offset data. The sum of these values is used to specify the target address.
Page 91 CHAPTER 3 CPU ARCHITECTURE Figure 3-32. Example of [HL + byte], [DE + byte] FFFFFH rp (HL/DE) Target memory F0000H OP code byte Memory Figure 3-33. Example of word[B], word[C] FFFFFH r (B/C) Target memory F0000H OP code Low Addr. High Addr.
Page 92 CHAPTER 3 CPU ARCHITECTURE Figure 3-35. Example of ES:[HL + byte], ES:[DE + byte] FFFFFH rp (HL/DE) Target memory OP code 00000H byte Memory Figure 3-36. Example of ES:word[B], ES:word[C] FFFFFH r (B/C) Target memory OP code 00000H Low Addr. Memory High Addr.
Page 93: Based Indexed Addressing
CHAPTER 3 CPU ARCHITECTURE 3.4.8 Based indexed addressing [Function] Based indexed addressing uses the contents of a register pair specified with the instruction word as the base address, and the content of the B register or C register similarly specified with the instruction word as offset address.
Page 94: Stack Addressing
CHAPTER 3 CPU ARCHITECTURE 3.4.9 Stack addressing [Function] The stack area is indirectly addressed with the stack pointer (SP) contents. This addressing is automatically employed when the PUSH, POP, subroutine call, and return instructions are executed or the register is saved/restored upon generation of an interrupt request.
Page 95: Chapter 4 Port Functions
• Pins other than port pins (except RESET pin and FLMD0 pin ) 78K0R/KF3 products are provided with the ports shown in Figure 4-1, which enable variety of control operations. The functions of each port are shown in Table 4-2.
Page 96 CHAPTER 4 PORT FUNCTIONS Table 4-2. Port Functions (1/2) Function Name Function After Reset Alternate Function Port 0. Input port TI00 7-bit I/O port. TO00 Input of P03 and P04 can be set to TTL input buffer. SO10/TxD1 Output of P02 to P04 can be set to N-ch open-drain output SI10/RxD1/SDA10 tolerance).
Page 97 CHAPTER 4 PORT FUNCTIONS Table 4-2. Port Functions (2/2) Function Name Function After Reset Alternate Function Port 6. Input port SCL0 8-bit I/O port. SDA0 Output of P60 to P63 can be set to N-ch open-drain output (6 − V tolerance). −...
Page 98: Port Configuration
CHAPTER 4 PORT FUNCTIONS 4.2 Port Configuration Ports include the following hardware. Table 4-3. Port Configuration Item Configuration Control registers Port mode registers (PM0 to PM7, PM9, PM11, PM12, PM14) Port registers (P0 to P7, P9, P11 to P14) Pull-up resistor option registers (PU0, PU1, PU3 to PU7, PU9, PU12, PU14) Port input mode registers (PIM0, PIM4, PIM14) Port output mode registers (POM0, POM4, POM14) A/D port configuration register (ADPC)
Page 99: Port 0
CHAPTER 4 PORT FUNCTIONS 4.2.1 Port 0 Port 0 is a 7-bit I/O port with an output latch. Port 0 can be set to the input mode or output mode in 1-bit units using port mode register 0 (PM0). When the P00 to P06 pins are used as an input port, use of an on-chip pull-up resistor can be specified in 1-bit units by pull-up resistor option register 0 (PU0).
Page 100 CHAPTER 4 PORT FUNCTIONS Figure 4-3. Block Diagram of P01 PU01 P-ch PORT Output latch (P01) P01/TO00 PM01 Alternate function Port register 0 PU0: Pull-up resistor option register 0 PM0: Port mode register 0 Read signal WR××: Write signal User’s Manual U17893EJ8V0UD...
Page 101 CHAPTER 4 PORT FUNCTIONS Figure 4-4. Block Diagram of P02 PU02 P-ch PORT Output latch (P02) P02/SO10/TxD1 POM0 POM02 PM02 Alternate function Port register 0 PU0: Pull-up resistor option register 0 PM0: Port mode register 0 POM0: Port output mode register 0 Read signal WR××: Write signal User’s Manual U17893EJ8V0UD...
Page 102 CHAPTER 4 PORT FUNCTIONS Figure 4-5. Block Diagram of P03 and P04 PIM0 PIM03, PIM04 PU03, PU04 P-ch Alternate function CMOS PORT Output latch P03/SI10/RxD1/SDA10, (P03, P04) P04/SCK10/SCL10 POM0 POM03, POM04 PM03, PM04 Alternate function Port register 0 PU0: Pull-up resistor option register 0 PM0: Port mode register 0 PIM0:...
Page 103 CHAPTER 4 PORT FUNCTIONS Figure 4-6. Block Diagram of P05 and P06 PU05, PU06 P-ch Alternate function PORT Output latch P05/TI05/TO05, (P05, P06) P06/TI06/TO06 PM05, PM06 Alternate function Port register 0 PU0: Pull-up resistor option register 0 PM0: Port mode register 0 Read signal WR××: Write signal User’s Manual U17893EJ8V0UD...
Page 104: Port 1
CHAPTER 4 PORT FUNCTIONS 4.2.2 Port 1 Port 1 is an 8-bit I/O port with an output latch. Port 1 can be set to the input mode or output mode in 1-bit units using port mode register 1 (PM1). When the P10 to P17 pins are used as an input port, use of an on-chip pull-up resistor can be specified in 1-bit units by pull-up resistor option register 1 (PU1).
Page 105 CHAPTER 4 PORT FUNCTIONS Figure 4-7. Block Diagram of P10 PU10 P-ch Alternate function PORT Output latch P10/SCK00 (P10) PM10 Alternate function Port register 1 PU1: Pull-up resistor option register 1 PM1: Port mode register 1 Read signal WR××: Write signal User’s Manual U17893EJ8V0UD...
Page 106 CHAPTER 4 PORT FUNCTIONS Figure 4-8. Block Diagram of P11 and P14 PU11, PU14 P-ch Alternate function PORT Output latch P11/SI00/RxD0, (P11, P14) P14/RxD3 PM11, PM14 Port register 1 PU1: Pull-up resistor option register 1 PM1: Port mode register 1 Read signal WR××: Write signal User’s Manual U17893EJ8V0UD...
Page 107 CHAPTER 4 PORT FUNCTIONS Figure 4-9. Block Diagram of P12 and P13 PU12, PU13 P-ch PORT Output latch P12/SO00/TxD0, (P12, P13) P13/TxD3 PM12, PM13 Alternate function Port register 1 PU1: Pull-up resistor option register 1 PM1: Port mode register 1 Read signal WR××: Write signal User’s Manual U17893EJ8V0UD...
Page 108 CHAPTER 4 PORT FUNCTIONS Figure 4-10. Block Diagram of P15 PU15 P-ch PORT Output latch P15/RTCDIV/RTCCL (P15) PM15 Alternate function Port register 1 PU1: Pull-up resistor option register 1 PM1: Port mode register 1 Read signal WR××: Write signal User’s Manual U17893EJ8V0UD...
Page 109 CHAPTER 4 PORT FUNCTIONS Figure 4-11. Block Diagram of P16 and P17 PU16, PU17 P-ch Alternate function PORT Output latch P16/TI01/TO01/INTP5, (P16, P17) P17/TI02/TO02 PM16, PM17 Alternate function Port register 1 PU1: Pull-up resistor option register 1 PM1: Port mode register 1 Read signal WR××: Write signal User’s Manual U17893EJ8V0UD...
Page 110: Port 2
CHAPTER 4 PORT FUNCTIONS 4.2.3 Port 2 Port 2 is an 8-bit I/O port with an output latch. Port 2 can be set to the input mode or output mode in 1-bit units using port mode register 2 (PM2). This port can also be used for A/D converter analog input. To use P20/ANI0 to P27/ANI7 as digital input pins, set them in the digital I/O mode by using the A/D port configuration register (ADPC) and in the input mode by using PM2.
Page 111: Port 3
CHAPTER 4 PORT FUNCTIONS Figure 4-12. Block Diagram of P20 to P27 PORT Output latch P20/ANI0 to (P20 to P27) P27/ANI7 PM20 to PM27 A/D converter Port register 2 PM2: Port mode register 2 Read signal WR××: Write signal 4.2.4 Port 3 Port 3 is a 2-bit I/O port with an output latch.
Page 112 CHAPTER 4 PORT FUNCTIONS Figure 4-13. Block Diagram of P30 and P31 PU30, PU31 P-ch Alternate function PORT Output latch P30/RTC1HZ/INTP3, (P30, P31) P31/TI03/TO03/INTP4 PM30, PM31 Alternate function Port register 3 PU3: Pull-up resistor option register 3 PM3: Port mode register 3 Read signal WR××: Write signal User’s Manual U17893EJ8V0UD...
Page 113: Port 4
CHAPTER 4 PORT FUNCTIONS 4.2.5 Port 4 Port 4 is an 8-bit I/O port with a output latch. Port 4 can be set to the input mode or output mode in 1-bit units using port mode register 4 (PM4). When the P40 to P47 pins are used as an input port, use of an on-chip pull-up Note resistor can be specified in 1-bit units by pull-up resistor option register 4 (PU4) Input to the P43 and P44 pins can be specified through a normal input buffer or a TTL input buffer in 1-bit units...
Page 114 CHAPTER 4 PORT FUNCTIONS Figure 4-14. Block Diagram of P40 PU40 P-ch Alternate function PORT Output latch (P40) P40/TOOL0 PM40 Alternate function Port register 4 PU4: Pull-up resistor option register 4 PM4: Port mode register 4 Read signal WR××: Write signal User’s Manual U17893EJ8V0UD...
Page 115 CHAPTER 4 PORT FUNCTIONS Figure 4-15. Block Diagram of P41 PU41 P-ch PORT Output latch (P41) P41/TOOL1 PM41 Alternate function Port register 4 PU4: Pull-up resistor option register 4 PM4: Port mode register 4 Read signal WR××: Write signal User’s Manual U17893EJ8V0UD...
Page 116 CHAPTER 4 PORT FUNCTIONS Figure 4-16. Block Diagram of P42 PU42 P-ch Alternate function PORT Output latch P42/TI04/TO04 (P42) PM42 Alternate function Port register 4 PU4: Pull-up resistor option register 4 PM4: Port mode register 4 Read signal WR××: Write signal User’s Manual U17893EJ8V0UD...
Page 117 CHAPTER 4 PORT FUNCTIONS Figure 4-17. Block Diagram of P43 PIM4 PIM43 PU43 P-ch Alternate function CMOS PORT Output latch P43/SCK01 (P43) POM4 POM43 PM43 Alternate function Port register 4 PU4: Pull-up resistor option register 4 PM4: Port mode register 4 PIM4: Port input mode register 4 POM4: Port output mode register 4...
Page 118 CHAPTER 4 PORT FUNCTIONS Figure 4-18. Block Diagram of P44 PIM4 PIM44 PU44 P-ch Alternate function CMOS PORT Output latch P44/SI01 (P44) PM44 Port register 4 PU4: Pull-up resistor option register 4 PM4: Port mode register 4 PIM4: Port input mode register 4 Read signal WR××: Write signal User’s Manual U17893EJ8V0UD...
Page 119 CHAPTER 4 PORT FUNCTIONS Figure 4-19. Block Diagram of P45 PU45 P-ch PORT Output latch P45/SO01 (P45) POM4 POM45 PM45 Alternate function Port register 4 PU4: Pull-up resistor option register 4 PM4: Port mode register 4 POM4: Port output mode register 4 Read signal WR××: Write signal User’s Manual U17893EJ8V0UD...
Page 120 CHAPTER 4 PORT FUNCTIONS Figure 4-20. Block Diagram of P46 and P47 PU46, PU47 P-ch PORT Output latch P46, P47 (P46, P47) PM46, PM47 Port register 4 PU4: Pull-up resistor option register 4 PM4: Port mode register 4 Read signal WR××: Write signal User’s Manual U17893EJ8V0UD...
Page 121: Port 5
CHAPTER 4 PORT FUNCTIONS 4.2.6 Port 5 Port 5 is an 8-bit I/O port with an output latch. Port 5 can be set to the input mode or output mode in 1-bit units using port mode register 5 (PM5). When the P50 to P55 pins are used as an input port, use of an on-chip pull-up resistor can be specified in 1-bit units by pull-up resistor option register 5 (PU5).
Page 122 CHAPTER 4 PORT FUNCTIONS Figure 4-22. Block Diagram of P52 to P55 PU52 to PU55 P-ch PORT Output latch P52 to P55 (P52 to P55) PM52 to PM55 Port register 5 PU5: Pull-up resistor option register 5 PM5: Port mode register 5 Read signal WR××: Write signal User’s Manual U17893EJ8V0UD...
Page 123: Port 6
CHAPTER 4 PORT FUNCTIONS 4.2.7 Port 6 Port 6 is an 8-bit I/O port with an output latch. Port 6 can be set to the input mode or output mode in 1-bit units using port mode register 6 (PM6). When the P64 to P67 pins are used as an input port, use of an on-chip pull-up resistor can be specified in 1-bit units by pull-up resistor option register 6 (PU6).
Page 124 CHAPTER 4 PORT FUNCTIONS Figure 4-24. Block Diagram of P62 and P63 PORT Output latch P62, P63 (P62, P63) PM62, PM63 Port register 6 PM6: Port mode register 6 Read signal WR××: Write signal User’s Manual U17893EJ8V0UD...
Page 125 CHAPTER 4 PORT FUNCTIONS Figure 4-25. Block Diagram of P64 to P67 PU64 to PU67 P-ch PORT Output latch P64 to P67 (P64 to P67) PM64to PM67 Port register 6 PU6: Pull-up resistor option register 6 PM6: Port mode register 6 Read signal WR××: Write signal User’s Manual U17893EJ8V0UD...
Page 126: Port 7
CHAPTER 4 PORT FUNCTIONS 4.2.8 Port 7 Port 7 is an 8-bit I/O port with an output latch. Port 7 can be set to the input mode or output mode in 1-bit units using port mode register 7 (PM7). When used as an input port, use of an on-chip pull-up resistor can be specified in 1-bit units by pull-up resistor option register 7 (PU7).
Page 127: Port 9
CHAPTER 4 PORT FUNCTIONS 4.2.9 Port 9 Port 9 is a 1-bit I/O port with an output latch. Port 9 can be set to the input mode or output mode in 1-bit units using port mode register 9 (PM9). When the P90 pin is used as an input port, use of an on-chip pull-up resistor can be specified in 1-bit units by pull-up resistor option register 9 (PU9).
Page 128: Port 11
CHAPTER 4 PORT FUNCTIONS 4.2.10 Port 11 Port 11 is a 2-bit I/O port with an output latch. Port 11 can be set to the input mode or output mode in 1-bit units using port mode register 11 (PM11). This port can also be used for D/A converter analog output. Reset signal generation sets port 11 to input mode.
Page 129 CHAPTER 4 PORT FUNCTIONS 4.2.11 Port 12 P120 is a 1-bit I/O port with an output latch. Port 12 can be set to the input mode or output mode in 1-bit units using port mode register 12 (PM12). When used as an input port, use of an on-chip pull-up resistor can be specified by pull-up resistor option register 12 (PU12).
Page 130 CHAPTER 4 PORT FUNCTIONS Figure 4-30. Block Diagram of P121 and P122 Clock generator OSCSEL P122/X2/EXCLK EXCLK, OSCSEL P121/X1 CMC: Clock operation mode control register Read signal User’s Manual U17893EJ8V0UD...
Page 131 CHAPTER 4 PORT FUNCTIONS Figure 4-31. Block Diagram of P123 and P124 Clock generator OSCSELS P124/XT2 OSCSELS P123/XT1 CMC: Clock operation mode control register Read signal User’s Manual U17893EJ8V0UD...
Page 132: Port 13
CHAPTER 4 PORT FUNCTIONS 4.2.12 Port 13 P130 is a 1-bit output-only port with an output latch. Figure 4-32 shows block diagrams of port 13. Figure 4-32. Block Diagram of P130 PORT Output latch P130 (P130) P13: Port register 13 Read signal WR××: Write signal Remark When reset is effected, P130 outputs a low level.
Page 133: Port 14
CHAPTER 4 PORT FUNCTIONS 4.2.13 Port 14 Port 14 is a 6-bit I/O port with an output latch. Port 14 can be set to the input mode or output mode in 1-bit units using port mode register 14 (PM14). When the P140 to P145 pins are used as an input port, use of an on-chip pull-up resistor can be specified in 1-bit units by pull-up resistor option register 14 (PU14).
Page 134 CHAPTER 4 PORT FUNCTIONS Figure 4-33. Block Diagram of P140, P141, and P145 PU14 PU140, PU141, PU145 P-ch Alternate function PORT Output latch P140/PCLBUZ0/INTP6, (P140, P141, P145) P141/PCLBUZ1/INTP7, P145/TI07/TO07 PM14 PM140, PM141, P145 Alternate function P14: Port register 14 PU14: Pull-up resistor option register 14 PM14: Port mode register 14...
Page 135 CHAPTER 4 PORT FUNCTIONS Figure 4-34. Block Diagram of P142 and P143 PIM14 PIM142, PIM143 PU14 PU142, PU143 P-ch Alternate function CMOS PORT Output latch P142/SCK20/SCL20, (P142, P143) P143/SI20/RxD2/SDA20 POM14 POM142, POM143 PM14 PM142, PM143 Alternate function P14: Port register 14 PU14: Pull-up resistor option register 14 PM14:...
Page 136 CHAPTER 4 PORT FUNCTIONS Figure 4-35. Block Diagram of P144 PU14 PU144 P-ch PORT Output latch (P144) P144/SO20/TxD2 POM14 POM144 PM14 PM144 Alternate function P14: Port register 14 PU14: Pull-up resistor option register 14 PM14: Port mode register 14 POM14: Port output mode register 14 Read signal WR××: Write signal User’s Manual U17893EJ8V0UD...
Page 137: Registers Controlling Port Function
CHAPTER 4 PORT FUNCTIONS 4.3 Registers Controlling Port Function Port functions are controlled by the following six types of registers. • Port mode registers (PM0 to PM7, PM9, PM11, PM12, PM14) • Port registers (P0 to P7, P9, P11 to P14) •...
Page 138 CHAPTER 4 PORT FUNCTIONS Figure 4-36. Format of Port Mode Register Symbol Address After reset PM06 PM05 PM04 PM03 PM02 PM01 PM00 FFF20H PM17 PM16 PM15 PM14 PM13 PM12 PM11 PM10 FFF21H PM27 PM26 PM25 PM24 PM23 PM22 PM21 PM20 FFF22H PM31 PM30...
Page 139 CHAPTER 4 PORT FUNCTIONS (2) Port registers (P0 to P7, P9, P11 to P14) These registers write the data that is output from the chip when data is output from a port. If the data is read in the input mode, the pin level is read. If it is read in the output mode, the output latch value is Note read These registers can be set by a 1-bit or 8-bit memory manipulation instruction.
Page 140 CHAPTER 4 PORT FUNCTIONS Figure 4-37. Format of Port Register Symbol Address After reset FFF00H 00H (output latch) R/W FFF01H 00H (output latch) R/W FFF02H 00H (output latch) R/W FFF03H 00H (output latch) R/W FFF04H 00H (output latch) R/W FFF05H 00H (output latch) R/W FFF06H 00H (output latch) R/W...
Page 141 CHAPTER 4 PORT FUNCTIONS (3) Pull-up resistor option registers (PU0, PU1, PU3 to PU7, PU9, PU12, PU14) These registers specify whether the on-chip pull-up resistors of P00 to P06, P10 to P17, P30, P31, P40 to P47, P50 to P55, P64 to P67, P70 to P77, P90, P120, or P140 to P145 are to be used or not. On-chip pull-up resistors can be used in 1-bit units only for the bits set to input mode of the pins to which the use of an on-chip pull-up resistor has been specified in PU0, PU1, PU3 to PU7, PU9, PU12, and PU14.
Page 142 CHAPTER 4 PORT FUNCTIONS (4) Port input mode registers (PIM0, PIM4, PIM14) These registers set the input buffer of P03, P04, P43, P44, P142, or P143 in 1-bit units. TTL input buffer can be selected during serial communication with an external device of the different potential. These registers can be set by a 1-bit or 8-bit memory manipulation instruction.
Page 143 CHAPTER 4 PORT FUNCTIONS (6) A/D port configuration register (ADPC) This register switches the P20/ANI0 to P27/ANI7 pins to digital I/O of port or analog input of A/D converter. ADPC can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation sets this register to 10H.
Page 144: Port Function Operations
CHAPTER 4 PORT FUNCTIONS 4.4 Port Function Operations Port operations differ depending on whether the input or output mode is set, as shown below. 4.4.1 Writing to I/O port (1) Output mode A value is written to the output latch by a transfer instruction, and the output latch contents are output from the pin. Once data is written to the output latch, it is retained until data is written to the output latch again.
Page 145: Connecting To External Device With Different Power Potential (2.5 V, 3 V)
CHAPTER 4 PORT FUNCTIONS 4.4.4 Connecting to external device with different power potential (2.5 V, 3 V) When parts of ports 0, 4, and 14 operate with V = 4.0 V to 5.5 V, I/O connections with an external device that operates on a 2.5 V or 3 V power supply voltage are possible.
Page 146 CHAPTER 4 PORT FUNCTIONS (2) Setting procedure when using I/O pins of simplified IIC10 and IIC20 functions <1> After reset release, the port mode is the input mode (Hi-Z). <2> Externally pull up the pin to be used (on-chip pull-up resistor cannot be used). In case of simplified IIC10: P03, P04 In case of simplified IIC20: P142, P143 <3>...
Page 147: Settings Of Port Mode Register And Output Latch When Using Alternate Function
CHAPTER 4 PORT FUNCTIONS 4.5 Settings of Port Mode Register and Output Latch When Using Alternate Function To use the alternate function of a port pin, set the port mode register and output latch as shown in Table 4-5. Table 4-5. Settings of Port Mode Register and Output Latch When Using Alternate Function (1/3) PM××...
Page 148 CHAPTER 4 PORT FUNCTIONS Table 4-5. Settings of Port Mode Register and Output Latch When Using Alternate Function (2/3) Pin Name Alternate Function PM×× P×× Function Name Note 1 Note 1 × P20 to P27 ANI0 to ANI7 Input RTC1HZ Output ×...
Page 149 CHAPTER 4 PORT FUNCTIONS Table 4-5. Settings of Port Mode Register and Output Latch When Using Alternate Function (3/3) Pin Name Alternate Function PM×× P×× Function Name × P143 SI20 Input × RxD2 Input SDA20 P144 SO20 Output TxD2 Output ×...
Page 150: Cautions On 1-Bit Manipulation Instruction For Port Register N (Pn)
The targets of writing to and reading from the Pn register of a port whose PMnm bit is 1 are the output latch and pin status, respectively. A 1-bit manipulation instruction is executed in the following order in the 78K0R/KF3. <1> The Pn register is read in 8-bit units.
Page 151: Chapter 5 Clock Generator
CHAPTER 5 CLOCK GENERATOR 5.1 Functions of Clock Generator The clock generator generates the clock to be supplied to the CPU and peripheral hardware. The following three kinds of system clocks and clock oscillators are selectable. (1) Main system clock <1>...
Page 152: Configuration Of Clock Generator
CHAPTER 5 CLOCK GENERATOR 5.2 Configuration of Clock Generator The clock generator includes the following hardware. Table 5-1. Configuration of Clock Generator Item Configuration Control registers Clock operation mode control register (CMC) Clock operation status control register (CSC) Oscillation stabilization time counter status register (OSTC) Oscillation stabilization time select register (OSTS) System clock control register (CKC) Peripheral enable register 0 (PER0)
Page 153 <R> Figure 5-1. Block Diagram of Clock Generator Internal bus Clock operation mode Clock operation status Oscillation stabilization System clock control control register control register time select register (OSTS) register (CKC) (CMC) (CSC) AMPH EXCLK OSCSEL MSTOP MCM0 OSTS2 OSTS1 OSTS0 X1 oscillation stabilization time counter STOP...
Page 154: Registers Controlling Clock Generator
CHAPTER 5 CLOCK GENERATOR Remark f X1 clock oscillation frequency Internal high-speed oscillation clock frequency External main system clock frequency High-speed system clock frequency : Main system clock frequency MAIN <R> : Main system select clock frequency MAINC XT1 clock oscillation frequency : Subsystem clock frequency CPU/peripheral hardware clock frequency Internal low-speed oscillation clock frequency...
Page 155 CHAPTER 5 CLOCK GENERATOR (1) Clock operation mode control register (CMC) This register is used to set the operation mode of the X1/P121, X2/EXCLK/P122, XT1/P123, and XT2/P124 pins, and to select a gain of the oscillator. CMC can be written only once by an 8-bit memory manipulation instruction after reset release. This register can be read by a 1-bit or 8-bit memory manipulation instruction.
Page 156 CHAPTER 5 CLOCK GENERATOR (2) Clock operation status control register (CSC) This register is used to control the operations of the high-speed system clock, internal high-speed oscillation clock, and subsystem clock (except the internal low-speed oscillation clock). CSC can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation sets this register to C0H.
Page 157 CHAPTER 5 CLOCK GENERATOR Table 5-2. Condition Before Stopping Clock Oscillation and Flag Setting Clock Condition Before Stopping Clock Setting of CSC (Invalidating External Clock Input) Register Flags • CLS = 0 and MCS = 0 X1 clock MSTOP = 1 •...
Page 158 CHAPTER 5 CLOCK GENERATOR Figure 5-4. Format of Oscillation Stabilization Time Counter Status Register (OSTC) Address: FFFA2H After reset: 00H Symbol OSTC MOST MOST MOST MOST MOST MOST MOST MOST MOST MOST MOST MOST MOST MOST MOST MOST Oscillation stabilization time status = 10 MHz = 20 MHz μ...
Page 159 CHAPTER 5 CLOCK GENERATOR (4) Oscillation stabilization time select register (OSTS) This register is used to select the X1 clock oscillation stabilization wait time when the STOP mode is released. When the X1 clock is selected as the CPU clock, the operation automatically waits for the time set using OSTS after the STOP mode is released.
Page 160 CHAPTER 5 CLOCK GENERATOR Figure 5-5. Format of Oscillation Stabilization Time Select Register (OSTS) Address: FFFA3H After reset: 07H Symbol OSTS OSTS2 OSTS1 OSTS0 OSTS2 OSTS1 OSTS0 Oscillation stabilization time selection = 10 MHz = 20 MHz μ 25.6 Setting prohibited μ...
Page 161 CHAPTER 5 CLOCK GENERATOR (5) System clock control register (CKC) This register is used to select a CPU/peripheral hardware clock and a division ratio. CKC can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation sets this register to 09H. Figure 5-6.
Page 162 ELECTRICAL SPECIFICATIONS ((A) GRADE PRODUCTS). The fastest instruction can be executed in 1 clock of the CPU clock in the 78K0R/KF3. Therefore, the relationship between the CPU clock (f ) and the minimum instruction execution time is as shown in Table 5-3.
Page 163 CHAPTER 5 CLOCK GENERATOR (6) Peripheral enable registers 0 (PER0) These registers are used to enable or disable use of each peripheral hardware macro. Clock supply to the hardware that is not used is also stopped so as to decrease the power consumption and noise. PER0 can be set by a 1-bit or 8-bit memory manipulation instruction.
Page 164 CHAPTER 5 CLOCK GENERATOR Figure 5-7. Format of Peripheral Enable Register (2/2) SAU1EN Control of serial array unit 1 input clock Stops input clock supply. • SFR used by the serial array unit 1 cannot be written. • The serial array unit 1 is in the reset status. Supplies input clock.
Page 165 CHAPTER 5 CLOCK GENERATOR (7) Operation speed mode control register (OSMC) This register is used to control the step-up circuit of the flash memory for high-speed operation. If the microcontroller operates at a low speed with a system clock of 10 MHz or less, the power consumption can be lowered by setting this register to the default value, 00H.
Page 166 CHAPTER 5 CLOCK GENERATOR (8) Internal high-speed oscillator trimming register (HIOTRM) This register is used to adjust the accuracy of the internal high-speed oscillator. With self-measurement of the internal high-speed oscillator frequency via a subsystem clock using a crystal resonator, a timer using high-accuracy external clock input (real-time counter or timer array unit), and so on, the register can adjust the accuracy.
Page 167 CHAPTER 5 CLOCK GENERATOR Figure 5-9. Format of Internal High-Speed Oscillator Trimming Register (HIOTRM) Address: F00F2H After reset: 10H Symbol HIOTRM TTRM4 TTRM3 TTRM2 TTRM1 TTRM0 TTRM4 TTRM3 TTRM2 TTRM1 TTRM0 Clock correction value (2.7 V ≤ V ≤ 5.5 V) MIN.
Page 168: System Clock Oscillator
CHAPTER 5 CLOCK GENERATOR 5.4 System Clock Oscillator 5.4.1 X1 oscillator The X1 oscillator oscillates with a crystal resonator or ceramic resonator (2 to 20 MHz) connected to the X1 and X2 pins. An external clock can also be input. In this case, input the clock signal to the EXCLK pin. To use the X1 oscillator, set bits 7 and 6 (EXCLK, OSCSEL) of the clock operation mode control register (CMC) as follows.
Page 169 CHAPTER 5 CLOCK GENERATOR Caution When using the X1 oscillator and XT1 oscillator, wire as follows in the area enclosed by the broken lines in the Figures 5-10 and 5-11 to avoid an adverse effect from wiring capacitance. • Keep the wiring length as short as possible. •...
Page 170 CHAPTER 5 CLOCK GENERATOR Figure 5-12. Examples of Incorrect Resonator Connection (2/2) (c) Wiring near high alternating current (d) Current flowing through ground line of oscillator (potential at points A, B, and C fluctuates) High current (e) Signals are fetched Remark When using the subsystem clock, replace X1 and X2 with XT1 and XT2, respectively.
Page 171: Internal High-Speed Oscillator
CHAPTER 5 CLOCK GENERATOR 5.4.3 Internal high-speed oscillator The internal high-speed oscillator is incorporated in the 78K0R/KF3 (8 MHz (TYP.)). Oscillation can be controlled by bit 0 (HIOSTOP) of the clock operation status control register (CSC). After a reset release, the internal high-speed oscillator automatically starts oscillation.
Page 172: Clock Generator Operation
• CPU/peripheral hardware clock f The CPU starts operation when the internal high-speed oscillator starts outputting after a reset release in the 78K0R/KF3, thus enabling the following. (1) Enhancement of security function When the X1 clock is set as the CPU clock by the default setting, the device cannot operate if the X1 clock is damaged or badly connected and therefore does not operate after reset is released.
Page 173 CHAPTER 5 CLOCK GENERATOR Figure 5-13. Clock Generator Operation When Power Supply Voltage Is Turned On (When LVI Default Start Function Stopped Is Set (Option Byte: LVIOFF = 1)) Power supply 1.8 V voltage (V 1.59 V (TYP.) 0.5 V/ms (MIN.) <1>...
Page 174 CHAPTER 5 CLOCK GENERATOR Cautions 1. If the voltage rises with a slope of less than 0.5 V/ms (MIN.) from power application until the voltage reaches 1.8 V, input a low level to the RESET pin from power application until the voltage reaches 1.8 V, or set the LVI default start function stopped by using the option byte (LVIOFF = 0) (see Figure 5-14).
Page 175 CHAPTER 5 CLOCK GENERATOR Notes 1. The internal reset processing time includes the oscillation accuracy stabilization time of the internal high-speed oscillation clock. When releasing a reset (above figure) or releasing STOP mode while the CPU is operating on the internal high-speed oscillation clock, confirm the oscillation stabilization time for the X1 clock using the oscillation stabilization time counter status register (OSTC).
Page 176: Controlling Clock
CHAPTER 5 CLOCK GENERATOR 5.6 Controlling Clock 5.6.1 Example of controlling high-speed system clock The following two types of high-speed system clocks are available. • X1 clock: Crystal/ceramic resonator is connected to the X1 and X2 pins. • External main system clock: External clock is input to the EXCLK pin. When the high-speed system clock is not used, the X1/P121 and X2/EXCLK/P122 pins can be used as input port pins.
Page 177 CHAPTER 5 CLOCK GENERATOR (2) Example of setting procedure when using the external main system clock <1> Setting P121/X1 and P122/X2/EXCLK pins (CMC register) EXCLK OSCSEL OSCSELS AMPH × Remarks 1. ×: don’t care 2. For setting of the P123/XT1 and P124/XT2 pins, see 5.6.3 (1) Example of setting procedure when oscillating the subsystem clock.
Page 178 CHAPTER 5 CLOCK GENERATOR <3> If some peripheral hardware macros are not used, supply of the input clock to each hardware macro can be stopped. (PER0 register) RTCEN DACEN ADCEN IIC0EN SAU1EN SAU0EN TAU0EN xxxEN Input clock control Stops input clock supply. Supplies input clock.
Page 179: Example Of Controlling Internal High-Speed Oscillation Clock
CHAPTER 5 CLOCK GENERATOR (b) To stop X1 oscillation (disabling external clock input) by setting MSTOP to 1 <1> Confirming the CPU clock status (CKC register) Confirm with CLS and MCS that the CPU is operating on a clock other than the high-speed system clock.
Page 180 CHAPTER 5 CLOCK GENERATOR <2> Setting the internal high-speed oscillation clock as the source clock of the CPU/peripheral hardware clock and setting the division ratio of the set clock (CKC register) MCM0 MDIV2 MDIV1 MDIV0 Selection of CPU/Peripheral Hardware Clock (f Caution If switching the CPU/peripheral hardware clock from the high-speed system clock to the internal high-speed oscillation clock after restarting the internal high-speed oscillation μ...
Page 181: Example Of Controlling Subsystem Clock
CHAPTER 5 CLOCK GENERATOR <2> Stopping the internal high-speed oscillation clock (CSC register) When HIOSTOP is set to 1, internal high-speed oscillation clock is stopped. Caution Be sure to confirm that MCS = 1 or CLS = 1 when setting HIOSTOP to 1. In addition, stop peripheral hardware that is operating on the internal high-speed oscillation clock.
Page 182 CHAPTER 5 CLOCK GENERATOR (2) Example of setting procedure when using the subsystem clock as the CPU clock Note <1> Setting subsystem clock oscillation (See 5.6.3 (1) Example of setting procedure when oscillating the subsystem clock.) Note The setting of <1> is not necessary when while the subsystem clock is operating. <2>...
Page 183: Example Of Controlling Internal Low-Speed Oscillation Clock
CHAPTER 5 CLOCK GENERATOR 5.6.4 Example of controlling internal low-speed oscillation clock The internal low-speed oscillation clock cannot be used as the CPU clock. Used only as the watchdog timer clock. The internal low-speed oscillator automatically starts oscillation after a reset release, and the watchdog timer is driven (240 kHz (TYP.)) if the watchdog timer operation is enabled by the option byte.
Page 184: Cpu Clock Status Transition Diagram
CHAPTER 5 CLOCK GENERATOR 5.6.5 CPU clock status transition diagram Figure 5-15 shows the CPU clock status transition diagram of this product. Figure 5-15. CPU Clock Status Transition Diagram Internal high-speed oscillation: Woken up Power ON X1 oscillation/EXCLK input: Stops (input port mode) XT1 oscillation: Stops (input port mode) <...
Page 185 CHAPTER 5 CLOCK GENERATOR Table 5-4 shows transition of the CPU clock and examples of setting the SFR registers. Table 5-4. CPU Clock Transition and SFR Register Setting Examples (1/4) (1) CPU operating with internal high-speed oscillation clock (B) after reset release (A) Status Transition SFR Register Setting (A) →...
Page 186 CHAPTER 5 CLOCK GENERATOR Table 5-4. CPU Clock Transition and SFR Register Setting Examples (2/4) (4) CPU clock changing from internal high-speed oscillation clock (B) to high-speed system clock (C) (Setting sequence of SFR registers) OSTS OSMC Note 1 Setting Flag of SFR Register CMC Register OSTC Register...
Page 187 CHAPTER 5 CLOCK GENERATOR Table 5-4. CPU Clock Transition and SFR Register Setting Examples (3/4) (6) CPU clock changing from high-speed system clock (C) to internal high-speed oscillation clock (B) (Setting sequence of SFR registers) Setting Flag of SFR Register CSC Register Oscillation accuracy CKC Register...
Page 188 CHAPTER 5 CLOCK GENERATOR Table 5-4. CPU Clock Transition and SFR Register Setting Examples (4/4) <R> (9) CPU clock changing from subsystem clock (D) to high-speed system clock (C) (Setting sequence of SFR registers) Setting Flag of SFR Register OSTS OSMC OSTC Register...
Page 189: Condition Before Changing Cpu Clock And Processing After Changing Cpu Clock
CHAPTER 5 CLOCK GENERATOR 5.6.6 Condition before changing CPU clock and processing after changing CPU clock Condition before changing the CPU clock and processing after changing the CPU clock are shown below. Table 5-5. Changing CPU Clock (1/2) CPU Clock Condition Before Change Processing After Change Before Change...
Page 190 CHAPTER 5 CLOCK GENERATOR Table 5-5. Changing CPU Clock (2/2) CPU Clock Condition Before Change Processing After Change Before Change After Change Subsystem Internal high- Oscillation of internal high-speed oscillator XT1 oscillation can be stopped (XTSTOP = Note clock speed oscillation and selection of internal high-speed clock oscillation clock as main system clock...
Page 191: Time Required For Switchover Of Cpu Clock And Main System Clock
CHAPTER 5 CLOCK GENERATOR 5.6.7 Time required for switchover of CPU clock and main system clock By setting bits 0 to 2, 4, and 6 (MDIV0 to MDIV2, MCM0, CSS) of the system clock control register (CKC), the CPU clock can be switched (between the main system clock and the subsystem clock), main system clock can be switched (between the internal high-speed oscillation clock and the high-speed system clock), and the division ratio of the main system clock can be changed.
Page 192: Conditions Before Clock Oscillation Is Stopped
CHAPTER 5 CLOCK GENERATOR <R> Table 5-9. Maximum Number of Clocks Required in Type 3 Set Value Before Switchover Set Value After Switchover MAINC 1 + 4 f clock MAINC MAINC 2 + f clock MAINC <R> Remarks 1. f :Internal high-speed oscillation clock frequency :High-speed system clock frequency :Main system clock frequency...
Page 193: Chapter 6 Timer Array Unit
CHAPTER 6 TIMER ARRAY UNIT The timer array unit has eight 16-bit timers per unit. Each 16-bit timer is called a channel and can be used as an independent timer. In addition, two or more “channels” can be used to create a high-accuracy timer. Single-operation Function Combination-operation Function •...
Page 194: Functions Of Each Channel When It Operates With Another Channel
CHAPTER 6 TIMER ARRAY UNIT 6.1.2 Functions of each channel when it operates with another channel Combination-operation functions are those functions that are attained by using the master channel (mostly the reference timer that controls cycles) and the slave channels (timers that operate following the master channel) in combination (for details, refer to 6.6.1 Overview of single-operation function and combination-operation function).
Page 195: Configuration Of Timer Array Unit
CHAPTER 6 TIMER ARRAY UNIT 6.2 Configuration of Timer Array Unit The timer array unit includes the following hardware. Table 6-1. Configuration of Timer Array Unit Item Configuration Timer/counter Timer counter register 0n (TCR0n) Register Timer data register 0n (TDR0n) Timer input TI00 to TI07 pins, RxD3 pin (for LIN-bus) Timer output...
Page 196 CHAPTER 6 TIMER ARRAY UNIT Figure 6-1. Block Diagram of Timer Array Unit Timer clock select register 0 (TPS0) Timer channel TE07 TE02 TE01 TE06 TE05 TE04 TE03 TE00 enable status Peripheral enable register 0 (TE0) TAU0EN PRS013 PRS012 PRS011 PRS010 PRS003 PRS002 PRS001 PRS000 register 0...
Page 197 CHAPTER 6 TIMER ARRAY UNIT (1) Timer/counter register 0n (TCR0n) TCR0n is a 16-bit read-only register and is used to count clocks. The value of this counter is incremented or decremented in synchronization with the rising edge of a count clock.
Page 198 CHAPTER 6 TIMER ARRAY UNIT The TCR0n register read value differs as follows according to operation mode changes and the operating status. Table 6-2. TCR0n Register Read Value in Various Operation Modes Note Operation Mode Count Mode TCR0n Register Read Value Operation mode Operation mode Operation restart...
Page 199 CHAPTER 6 TIMER ARRAY UNIT (2) Timer data register 0n (TDR0n) This is a 16-bit register from which a capture function and a compare function can be selected. The capture or compare function can be switched by selecting an operation mode by using the MD0n3 to MD0n0 bits of TMR0n.
Page 200: Registers Controlling Timer Array Unit
CHAPTER 6 TIMER ARRAY UNIT 6.3 Registers Controlling Timer Array Unit Timer array unit is controlled by the following registers. • Peripheral enable register 0 (PER0) • Timer clock select register 0 (TPS0) • Timer mode register 0n (TMR0n) • Timer status register 0n (TSR0n) •...
Page 201 CHAPTER 6 TIMER ARRAY UNIT (1) Peripheral enable register 0 (PER0) PER0 is used to enable or disable use of each peripheral hardware macro. Clock supply to a hardware macro that is not used is stopped in order to reduce the power consumption and noise. When the timer array unit is used, be sure to set bit 0 (TAU0EN) of this register to 1.
Page 202 CHAPTER 6 TIMER ARRAY UNIT (2) Timer clock select register 0 (TPS0) TPS0 is a 16-bit register that is used to select two types of operation clocks (CK00, CK01) that are commonly supplied to each channel. CK01 is selected by bits 7 to 4 of TPS0, and CK00 is selected by bits 3 to 0. Rewriting of TPS0 during timer operation is possible only in the following cases.
Page 203 CHAPTER 6 TIMER ARRAY UNIT (3) Timer mode register 0n (TMR0n) TMR0n sets an operation mode of channel n. It is used to select an operation clock (MCK), a count clock, whether the timer operates as the master or a slave, a start trigger and a capture trigger, the valid edge of the timer input, and an operation mode (interval, capture, event counter, one-count, or capture &...
Page 204 CHAPTER 6 TIMER ARRAY UNIT Figure 6-6. Format of Timer Mode Register 0n (TMR0n) (2/3) Address: F0190H, F0191H (TMR00) to F019EH, F019FH (TMR07) After reset: 0000H Symbol TMR0n MAST ER0n Setting of start trigger or capture trigger of channel n Only software trigger start is valid (other trigger sources are unselected).
Page 205 CHAPTER 6 TIMER ARRAY UNIT Figure 6-6. Format of Timer Mode Register 0n (TMR0n) (3/3) Address: F0190H, F0191H (TMR00) to F019EH, F019FH (TMR07) After reset: 0000H Symbol TMR0n MAST ER0n Operation mode of channel n Count operation of TCR Independent operation Interval timer mode Counting down Possible...
Page 206 CHAPTER 6 TIMER ARRAY UNIT (4) Timer status register 0n (TSR0n) TSR0n indicates the overflow status of the counter of channel n. TSR0n is valid only in the capture mode (MD0n3 to MD0n1 = 010B) and capture & one-count mode (MD0n3 to MD0n1 = 110B).
Page 207 CHAPTER 6 TIMER ARRAY UNIT (5) Timer channel enable status register 0 (TE0) TE0 is used to enable or stop the timer operation of each channel. When a bit of timer channel start register 0 (TS0) is set to 1, the corresponding bit of this register is set to 1. When a bit of timer channel stop register 0 (TT0) is set to 1, the corresponding bit of this register is cleared to TE0 can be read by a 16-bit memory manipulation instruction.
Page 208 CHAPTER 6 TIMER ARRAY UNIT (6) Timer channel start register 0 (TS0) TS0 is a trigger register that is used to clear a timer counter (TCR0n) and start the counting operation of each channel. When a bit (TS0n) of this register is set to 1, the corresponding bit (TE0n) of timer channel enable status register 0 (TE0) is set to 1.
Page 209 CHAPTER 6 TIMER ARRAY UNIT Table 6-4. Operations from Count Operation Enabled State to TCR0n Count Start (2/2) Timer operation mode Operation when TS0n = 1 is set • One-count mode When TS0n = 0, writing 1 to TS0n bit sets the start trigger wait state. No operation is carried out from start trigger detection until count clock generation.
Page 210 CHAPTER 6 TIMER ARRAY UNIT (b) Start timing in event counter mode <1> While TE0n is set to 0, TCR0n holds the initial value. <2> Writing 1 to TS0n sets 1 to TE0n. <3> As soon as 1 has been written to TS0n and 1 has been set to TE0n, the "TDR0n value" is loaded to TCR0n to start counting.
Page 211 CHAPTER 6 TIMER ARRAY UNIT (d) Start timing in one-count mode <1> Writing 1 to TS0n sets TE0n = 1 <2> Enters the start trigger input wait status, and TCR0n holds the initial value. <3> On start , the “TDR0n value” is loaded to TCR0n and count starts. trigger detection Figure 6-13.
Page 212 CHAPTER 6 TIMER ARRAY UNIT (e) Start timing in capture & one-count mode <1> Writing 1 to TS0n sets TE0n = 1 <2> Enters the start trigger input wait status, and TCR0n holds the initial value. <3> On start , 0000H is loaded to TCR0n and count starts. trigger detection Figure 6-14.
Page 213 CHAPTER 6 TIMER ARRAY UNIT (7) Timer channel stop register 0 (TT0) TT0 is a trigger register that is used to clear a timer counter (TCR0n) and start the counting operation of each channel. When a bit (TT0n) of this register is set to 1, the corresponding bit (TE0n) of timer channel enable status register 0 (TE0) is cleared to 0.
Page 214 CHAPTER 6 TIMER ARRAY UNIT (9) Timer output enable register 0 (TOE0) TOE0 is used to enable or disable timer output of each channel. Channel n for which timer output has been enabled becomes unable to rewrite the value of the TO0n bit of the timer output register (TO0) described later by software, and the value reflecting the setting of the timer output function through the count operation is output from the timer output pin (TO0n).
Page 215 CHAPTER 6 TIMER ARRAY UNIT (10) Timer output register 0 (TO0) TO0 is a buffer register of timer output of each channel. The value of each bit in this register is output from the timer output pin (TO0n) of each channel. This register can be rewritten by software only when timer output is disabled (TOE0n = 0).
Page 216 CHAPTER 6 TIMER ARRAY UNIT (11) Timer output level register 0 (TOL0) TOL0 is a register that controls the timer output level of each channel. The setting of the inverted output of channel n by this register is reflected at the timing of set or reset of the timer output signal while the timer output is enabled (TOE0n = 1) in the combination-operation mode (TOM0n = 1).
Page 217 CHAPTER 6 TIMER ARRAY UNIT (12) Timer output mode register 0 (TOM0) TOM0 is used to control the timer output mode of each channel. When a channel is used for the single-operation function, set the corresponding bit of the channel to be used to 0.
Page 218 CHAPTER 6 TIMER ARRAY UNIT (13) Input switch control register (ISC) ISC is used to implement LIN-bus communication operation with channel 7 in association with serial array unit When bit 1 of this register is set to 1, the input signal of the serial data input pin (RxD3) is selected as a timer input signal.
Page 219 CHAPTER 6 TIMER ARRAY UNIT Figure 6-22. Format of Noise Filter Enable Register 1 (NFEN1) Address: F0061H After reset: 00H Symbol NFEN1 TNFEN07 TNFEN06 TNFEN05 TNFEN04 TNFEN03 TNFEN02 TNFEN01 TNFEN00 Note Enable/disable using noise filter of TI07/TO07/P145 pin or RxD3/P14 pin input signal TNFEN07 Noise filter OFF Noise filter ON...
Page 220 CHAPTER 6 TIMER ARRAY UNIT (15) Port mode registers 0, 1, 3, 4, 14 (PM0, PM1, PM3, PM4, PM14) These registers set input/output of ports 0, 1, 3, 4, and 14 in 1-bit units. When using the P01/TO00, P05/TO05/TI05, P06/TO06/TI06, P16/TO01/TI01/INTP5, P17/TO02/TI02, P31/TO03/TI03/INTP4, P42/TO04/TI04, and P145/TO07/TI07 pins for timer output, set PM01, PM05, PM06, PM16, PM17, PM31, PM42, and PM145 and the output latches of P01, P05, P06, P16, P17, P31, P42, and P145 to 0.
Page 221: Channel Output (To0N Pin) Control
CHAPTER 6 TIMER ARRAY UNIT 6.4 Channel Output (TO0n pin) Control 6.4.1 TO0n pin output circuit configuration Figure 6-24. Output Circuit Configuration <5> TO0n register Interrupt signal of the master channel (INTTM0n) TO0n pin Interrupt signal of the slave channel (INTTM0p) Reset/toggle <1>...
Page 222: To0N Pin Output Setting
CHAPTER 6 TIMER ARRAY UNIT 6.4.2 TO0n Pin Output Setting The following figure shows the procedure and status transition of TO0n out put pin from initial setting to timer operation start. Figure 6-25. Status Transition from Timer Output Setting to Operation Start TCR0n Undefined value (FFFFH after reset) (Counter)
Page 223 CHAPTER 6 TIMER ARRAY UNIT (2) Default level of TO0n pin and output level after timer operation start The following figure shows the TO0n pin output level transition when writing has been done in the state of TOE0n = 0 before port output is enabled and TOE0n = 1 is set after changing the default level. (a) When operation starts with TOM0n = 0 setting (toggle output) The setting of TOL0n is invalid when TOM0n = 0.
Page 224 CHAPTER 6 TIMER ARRAY UNIT (b) When operation starts with TOM0n = 1 setting (Combination-operation mode (PWM output)) When TOM0n = 1, the active level is determined by TOL0n setting. Figure 6-27. TO0n Pin Output Status at PWM Output (TOM0n = 1) TOE0n Default level, TOL0n setting TO0n = 0, TOL0n = 0...
Page 225 CHAPTER 6 TIMER ARRAY UNIT (b) Set/reset timing To realize 0%/100% output at PWM output, the TO0n pin/TO0n set timing at master channel timer interrupt (INTTM0n) generation is delayed by 1 count clock by the slave channel. If the set condition and reset condition are generated at the same time, a higher priority is given to the latter.
Page 226: Collective Manipulation Of To0N Bits
CHAPTER 6 TIMER ARRAY UNIT 6.4.4 Collective manipulation of TO0n bits In the TO0 register, the setting bits for all the channels are located in one register in the same way as the TS0 register (channel start trigger). Therefore, TO0n of all the channels can be manipulated collectively. Only specific bits can also be manipulated by setting the corresponding TOE0n = 0 to a target TO0n (channel output).
Page 227: Timer Interrupt And To0N Pin Output At Operation Start
CHAPTER 6 TIMER ARRAY UNIT Caution When TOE0n = 1, even if the output by timer interrupt of each timer (INTTM0n) contends with writing to TO0n, output is normally done to TO0n pin. Remark n = 0 to 7 6.4.5 Timer Interrupt and TO0n Pin Output at Operation Start In the interval timer mode or capture mode, the MD0n0 bit in the TMR0n register sets whether or not to generate a timer interrupt at count start.
Page 228: Channel Input (Ti0N Pin) Control
CHAPTER 6 TIMER ARRAY UNIT 6.5 Channel Input (TI0n Pin) Control 6.5.1 TI0n edge detection circuit (1) Edge detection basic operation timing Edge detection circuit sampling is done in accordance with the operation clock (MCK). Figure 6-34. Edge Detection Basic Operation Timing Operation clock (MCK) Synchronized (noise filter) internal TI0n signal...
Page 229: Basic Function Of Timer Array Unit
CHAPTER 6 TIMER ARRAY UNIT 6.6 Basic Function of Timer Array Unit 6.6.1 Overview of single-operation function and combination-operation function The timer array unit consists of several channels and has a single-operation function that allows each channel to operate independently, and a combination-operation function that uses two or more channels in combination. The single-operation function can be used for any channel, regardless of the operation mode of the other channels.
Page 230: Applicable Range Of Basic Rules Of Combination-Operation Function
CHAPTER 6 TIMER ARRAY UNIT 6.6.3 Applicable range of basic rules of combination-operation function The rules of the combination-operation function are applied in a channel group (a master channel and slave channels forming one combination-operation function). If two or more channel groups that do not operate in combination are specified, the basic rules of the combination- operation function in 6.6.2 Basic rules of combination-operation function do not apply to the channel groups.
Page 231: Operation Of Timer Array Unit As Independent Channel
CHAPTER 6 TIMER ARRAY UNIT 6.7 Operation of Timer Array Unit as Independent Channel 6.7.1 Operation as interval timer/square wave output (1) Interval timer The timer array unit can be used as a reference timer that generates INTTM0n (timer interrupt) at fixed intervals.
Page 232 CHAPTER 6 TIMER ARRAY UNIT Figure 6-35. Block Diagram of Operation as Interval Timer/Square Wave Output CK01 Operation clock CK00 Timer counter Output TO0n pin (TCR0n) controller Interrupt Data register Interrupt signal TS0n controller (TDR0n) (INTTM0n) Figure 6-36. Example of Basic Timing of Operation as Interval Timer/Square Wave Output (MD0n0 = 1) TS0n TE0n TCR0n...
Page 233 CHAPTER 6 TIMER ARRAY UNIT Figure 6-37. Example of Set Contents of Registers During Operation as Interval Timer/Square Wave Output (1/3) (1) When CK00 or CK01 is selected as count clock (a) Timer mode register 0n (TMR0n) TMR0n CKS0n CCS0n STS0n2 STS0n1 STS0n0...
Page 234 CHAPTER 6 TIMER ARRAY UNIT Figure 6-37. Example of Set Contents of Registers During Operation as Interval Timer/Square Wave Output (2/3) (2) When f /4 is selected as count clock (a) Timer mode register 0n (TMR0n) TMR0n CKS0n CCS0n STS0n2 STS0n1 STS0n0 CIS0n1...
Page 235 CHAPTER 6 TIMER ARRAY UNIT Figure 6-37. Example of Set Contents of Registers During Operation as Interval Timer/Square Wave Output (3/3) (2) When f /4 is selected as count clock (continued) (e) Timer output enable register 0 (TOE0) Bit n TOE0 0: Stops the TO0n output operation by counting operation.
Page 236 CHAPTER 6 TIMER ARRAY UNIT Figure 6-38. Operation Procedure of Interval Timer/Square Wave Output Function Software Operation Hardware Status Power-off status default (Clock supply is stopped and writing to each register is setting disabled.) Sets the TAU0EN bit of the PER0 register to 1. Power-on status.
Page 237: Operation As External Event Counter
CHAPTER 6 TIMER ARRAY UNIT 6.7.2 Operation as external event counter The timer array unit can be used as an external event counter that counts the number of times the valid input edge (external event) is detected in the TI0n pin. When a specified count value is reached, the event counter generates an interrupt.
Page 238 CHAPTER 6 TIMER ARRAY UNIT Figure 6-41. Example of Set Contents of Registers in External Event Counter Mode (a) Timer mode register 0n (TMR0n) TMR0n CKS0n CCS0n STS0n2 STS0n1 STS0n0 CIS0n1 CIS0n0 MD0n3 MD0n2 MD0n1 MD0n0 TER0n Operation mode of channel n 011B: Event count mode Setting of operation when counting is started 0: Neither generates INTTM0n nor inverts...
Page 239 CHAPTER 6 TIMER ARRAY UNIT Figure 6-42. Operation Procedure When External Event Counter Function Is Used Software Operation Hardware Status Power-off status default (Clock supply is stopped and writing to each register is setting disabled.) Sets the TAU0EN bit of the PER0 register to 1. Power-on status.
Page 240: Operation As Frequency Divider (Channel 0 Only)
CHAPTER 6 TIMER ARRAY UNIT 6.7.3 Operation as frequency divider (channel 0 only) The timer array unit can be used as a frequency divider that divides a clock input to the TI00 pin and outputs the result from TO00. The divided clock frequency output from TO00 can be calculated by the following expression. •...
Page 241 CHAPTER 6 TIMER ARRAY UNIT Figure 6-44. Example of Basic Timing of Operation as Frequency Divider (MD000 = 1) TS00 TE00 TI00 TCR00 0000H TDR00 0002H 0001H TO00 INTTM00 Divided Divided by 6 by 4 User’s Manual U17893EJ8V0UD...
Page 242 CHAPTER 6 TIMER ARRAY UNIT Figure 6-45. Example of Set Contents of Registers When Frequency Divider Is Used (a) Timer mode register 00 (TMR00) TMR00 CKS00 CCS00 STS002 STS001 STS000 CIS001 CIS000 MD003 MD002 MD001 MD000 TER00 Operation mode of channel 0 000B: Interval timer Setting of operation when counting is started 0: Neither generates INTTM00 nor inverts...
Page 243 CHAPTER 6 TIMER ARRAY UNIT Figure 6-46. Operation Procedure When Frequency Divider Function Is Used Software Operation Hardware Status Power-off status default (Clock supply is stopped and writing to each register is setting disabled.) Sets the TAU0EN bit of the PER0 register to 1. Power-on status.
Page 244: Operation As Input Pulse Interval Measurement
CHAPTER 6 TIMER ARRAY UNIT 6.7.4 Operation as input pulse interval measurement The count value can be captured at the TI0n valid edge and the interval of the pulse input to TI0n can be measured. The pulse interval can be calculated by the following expression. TI0n input pulse interval = Period of count clock ×...
Page 245 CHAPTER 6 TIMER ARRAY UNIT Figure 6-48. Example of Basic Timing of Operation as Input Pulse Interval Measurement (MD0n0 = 0) TS0n TE0n TI0n FFFFH TCR0n 0000H TDR0n 0000H INTTM0n Remark n = 0 to 7 User’s Manual U17893EJ8V0UD...
Page 246 CHAPTER 6 TIMER ARRAY UNIT Figure 6-49. Example of Set Contents of Registers to Measure Input Pulse Interval (a) Timer mode register 0n (TMR0n) TMR0n CKS0n CCS0n STS0n2 STS0n1 STS0n0 CIS0n1 CIS0n0 MD0n3 MD0n2 MD0n1 MD0n0 TER0n Operation mode of channel n 010B: Capture mode Setting of operation when counting is started 0: Does not generate INTTM0n when...
Page 247 CHAPTER 6 TIMER ARRAY UNIT Figure 6-50. Operation Procedure When Input Pulse Interval Measurement Function Is Used Software Operation Hardware Status Power-off status default (Clock supply is stopped and writing to each register is setting disabled.) Sets the TAU0EN bit of the PER0 register to 1. Power-on status.
Page 248: Operation As Input Signal High-/Low-Level Width Measurement
CHAPTER 6 TIMER ARRAY UNIT 6.7.5 Operation as input signal high-/low-level width measurement By starting counting at one edge of TI0n and capturing the number of counts at another edge, the signal width (high-level width/low-level width) of TI0n can be measured. The signal width of TI0n can be calculated by the following expression.
Page 249 CHAPTER 6 TIMER ARRAY UNIT Figure 6-52. Example of Basic Timing of Operation as Input Signal High-/Low-Level Width Measurement TS0n TE0n TI0n FFFFH TCR0n 0000H TDR0n 0000H INTTM0n Remark n = 0 to 7 User’s Manual U17893EJ8V0UD...
Page 250 CHAPTER 6 TIMER ARRAY UNIT Figure 6-53. Example of Set Contents of Registers to Measure Input Signal High-/Low-Level Width (a) Timer mode register 0n (TMR0n) TMR0n CKS0n CCS0n STS0n2 STS0n1 STS0n0 CIS0n1 CIS0n0 MD0n3 MD0n2 MD0n1 MD0n0 TER0n Operation mode of channel n 110B: Capture &...
Page 251 CHAPTER 6 TIMER ARRAY UNIT Figure 6-54. Operation Procedure When Input Signal High-/Low-Level Width Measurement Function Is Used Software Operation Hardware Status Power-off status default (Clock supply is stopped and writing to each register is setting disabled.) Sets the TAU0EN bit of the PER0 register to 1. Power-on status.
Page 252: Operation Of Plural Channels Of Timer Array Unit
CHAPTER 6 TIMER ARRAY UNIT 6.8 Operation of Plural Channels of Timer Array Unit 6.8.1 Operation as PWM function Two channels can be used as a set to generate a pulse of any period and duty factor. The period and duty factor of the output pulse can be calculated by the following expressions. Pulse period = {Set value of TDR0n (master) + 1} ×...
Page 253 CHAPTER 6 TIMER ARRAY UNIT Figure 6-55. Block Diagram of Operation as PWM Function Master channel (interval timer mode) CK01 Operation clock Timer counter (TCR0n) CK00 Data register Interrupt Interrupt signal TS0n (TDR0n) controller (INTTM0n) Slave channel (one-count mode) CK01 Operation clock Timer counter Output...
Page 254 CHAPTER 6 TIMER ARRAY UNIT Figure 6-56. Example of Basic Timing of Operation as PWM Function TS0n TE0n FFFFH Master TCR0n channel 0000H TDR0n TO0n INTTM0n TS0m TE0m FFFFH TCR0m Slave 0000H channel TDR0m TO0m INTTM0m Remark n = 0, 2, 4, 6 m = n + 1 User’s Manual U17893EJ8V0UD...
Page 255 CHAPTER 6 TIMER ARRAY UNIT Figure 6-57. Example of Set Contents of Registers When PWM Function (Master Channel) Is Used (a) Timer mode register 0n (TMR0n) TMR0n CKS0n CCS0n STS0n2 STS0n1 STS0n0 CIS0n1 CIS0n0 MD0n3 MD0n2 MD0n1 MD0n0 TER0n Operation mode of channel n 000B: Interval timer Setting of operation when counting is started 1: Generates INTTM0n when counting is...
Page 256 CHAPTER 6 TIMER ARRAY UNIT Figure 6-58. Example of Set Contents of Registers When PWM Function (Slave Channel) Is Used (a) Timer mode register 0m (TMR0m) TMR0m CKS0m CCS0m STS0m2 STS0m1 STS0m0 CIS0m1 CIS0m0 MD0m3 MD0m2 MD0m1 MD0m0 TER0 Operation mode of channel m 100B: One-count mode Start trigger during operation 1: Trigger input is valid.
Page 257 CHAPTER 6 TIMER ARRAY UNIT Figure 6-59. Operation Procedure When PWM Function Is Used (1/2) Software Operation Hardware Status Power-off status default (Clock supply is stopped and writing to each register is setting disabled.) Sets the TAU0EN bit of the PER0 register to 1. Power-on status.
Page 258 CHAPTER 6 TIMER ARRAY UNIT Figure 6-59. Operation Procedure When PWM Function Is Used (2/2) Software Operation Hardware Status Operation Sets TOE0m (slave) to 1 (only when operation is start resumed). The TS0n (master) and TS0m (slave) bits of the TS0 TE0n = 1, TE0m = 1 register are set to 1 at the same time.
Page 259: Operation As One-Shot Pulse Output Function
CHAPTER 6 TIMER ARRAY UNIT 6.8.2 Operation as one-shot pulse output function By using two channels as a set, a one-shot pulse having any delay pulse width can be generated from the signal input to the TI0n pin. The delay time and pulse width can be calculated by the following expressions. Delay time = {Set value of TDR0n (master) + 2} ×...
Page 260 CHAPTER 6 TIMER ARRAY UNIT Figure 6-60. Block Diagram of Operation as One-Shot Pulse Output Function Master channel (one-count mode) CK01 Operation clock Timer counter (TCR0n) CK00 TS0n Data register Interrupt Interrupt signal (TDR0n) controller Edge (INTTM0n) TI0n pin detection Slave channel (one-count mode) CK01...
Page 261 CHAPTER 6 TIMER ARRAY UNIT Figure 6-61. Example of Basic Timing of Operation as One-Shot Pulse Output Function TS0n TE0n TI0n Master FFFFH channel TCR0n 0000H TDR0n TO0n INTTM0n TS0m TE0m FFFFH TCR0m Slave 0000H channel TDR0m TO0m INTTM0m Remark n = 0, 2, 4, 6 m = n + 1 User’s Manual U17893EJ8V0UD...
Page 262 CHAPTER 6 TIMER ARRAY UNIT Figure 6-62. Example of Set Contents of Registers When One-Shot Pulse Output Function Is Used (Master Channel) (a) Timer mode register 0n (TMR0n) TMR0n CKS0n CCS0n STS0n2 STS0n1 STS0n0 CIS0n1 CIS0n0 MD0n3 MD0n2 MD0n1 MD0n0 TER0n Operation mode of channel n 100B: One-count mode...
Page 263 CHAPTER 6 TIMER ARRAY UNIT Figure 6-63. Example of Set Contents of Registers When One-Shot Pulse Output Function Is Used (Slave Channel) (a) Timer mode register 0m (TMR0m) TMR0m CKS0m CCS0m STS0m2 STS0m1 STS0m0 CIS0m1 CIS0m0 MD0m3 MD0m2 MD0m1 MD0m0 TER0 Operation mode of channel m 100B: One-count mode...
Page 264 CHAPTER 6 TIMER ARRAY UNIT Figure 6-64. Operation Procedure of One-Shot Pulse Output Function (1/2) Software Operation Hardware Status Power-off status default (Clock supply is stopped and writing to each register is setting disabled.) Sets the TAU0EN bit of the PER0 register to 1. Power-on status.
Page 265 CHAPTER 6 TIMER ARRAY UNIT Figure 6-64. Operation Procedure of One-Shot Pulse Output Function (2/2) Software Operation Hardware Status Operation Sets TOE0m (slave) to 1 (only when operation is start resumed). The TS0n (master) and TS0m (slave) bits of the TS0 register are set to 1 at the same time.
Page 266: Operation As Multiple Pwm Output Function
CHAPTER 6 TIMER ARRAY UNIT 6.8.3 Operation as multiple PWM output function By extending the PWM function and using two or more slave channels, many PWM output signals can be produced. For example, when using two slave channels, the period and duty factor of an output pulse can be calculated by the following expressions.
Page 267 CHAPTER 6 TIMER ARRAY UNIT Figure 6-65. Block Diagram of Operation as Multiple PWM Output Function (output two types of PWMs) Master channel (interval timer mode) CK01 Operation clock Timer counter (TCR0n) CK00 Data register Interrupt Interrupt signal TS0n (TDR0n) controller (INTTM0n) Slave channel 1...
Page 268 CHAPTER 6 TIMER ARRAY UNIT Figure 6-66. Example of Basic Timing of Operation as Multiple PWM Output Function (output two types of PWMs) TS0n TE0n FFFFH Master TCR0n channel 0000H TDR0n TO0n INTTM0n TS0p TE0p FFFFH TCR0p Slave 0000H channel 1 TDR0p TO0p INTTM0p...
Page 269 CHAPTER 6 TIMER ARRAY UNIT Figure 6-67. Example of Set Contents of Registers When Multiple PWM Output Function (Master Channel) Is Used (a) Timer mode register 0n (TMR0n) TMR0n CKS0n CCS0n STS0n2 STS0n1 STS0n0 CIS0n1 CIS0n0 MD0n3 MD0n2 MD0n1 MD0n0 TER0n Operation mode of channel n 000B: Interval timer...
Page 270 CHAPTER 6 TIMER ARRAY UNIT Figure 6-68. Example of Set Contents of Registers When Multiple PWM Output Function (Slave Channel) Is Used (output two types of PWMs) (a) Timer mode register 0p, 0q (TMR0p, TMR0q) TMR0p CKS0p CCS0p STS0p2 STS0p1 STS0p0 CIS0p1 CIS0p0...
Page 271 CHAPTER 6 TIMER ARRAY UNIT Figure 6-69. Operation Procedure When Multiple PWM Output Function Is Used (1/2) Software Operation Hardware Status Power-off status default (Clock supply is stopped and writing to each register is setting disabled.) Sets the TAU0EN bit of the PER0 register to 1. Power-on status.
Page 272 CHAPTER 6 TIMER ARRAY UNIT Figure 6-69. Operation Procedure When Multiple PWM Output Function Is Used (2/2) Software Operation Hardware Status Operation Sets TOE0p and TOE0q (slave) to 1 (only when start operation is resumed). The TS0n bit (master), and TS0p and TS0q (slave) bits of TE0n = 1, TE0p, TE0q = 1 the TS0 register are set to 1 at the same time.
Page 273: Chapter 7 Real-Time Counter
CHAPTER 7 REAL-TIME COUNTER 7.1 Functions of Real-Time Counter The real-time counter has the following features. • Having counters of year, month, week, day, hour, minute, and second, and can count up to 99 years. • Constant-period interrupt function (period: 1 month to 0.5 seconds) •...
Page 274 CHAPTER 7 REAL-TIME COUNTER Figure 7-1. Block Diagram of Real-Time Counter Real-time counter control register 1 Real-time counter control register 0 WALE WALIE WAFG RIFG RWST RWAIT RTCE RCLOE1 RCLOE0 AMPM RTC1HZ/ Alarm week Alarm hour Alarm minute INTP3/P30 register register register (ALARMWW)
Page 275: Registers Controlling Real-Time Counter
CHAPTER 7 REAL-TIME COUNTER 7.3 Registers Controlling Real-Time Counter The real-time counter is controlled by the following 18 registers. • Peripheral enable register 0 (PER0) • Real-time counter control register 0 (RTCC0) • Real-time counter control register 1 (RTCC1) • Real-time counter control register 2 (RTCC2) •...
Page 276 CHAPTER 7 REAL-TIME COUNTER (1) Peripheral enable register 0 (PER0) PER0 is used to enable or disable use of each peripheral hardware macro. Clock supply to a hardware macro that is not used is stopped in order to reduce the power consumption and noise. When the real-time counter is used, be sure to set bit 7 (RTCEN) of this register to 1.
Page 277 CHAPTER 7 REAL-TIME COUNTER Figure 7-3. Format of Real-Time Counter Control Register 0 (RTCC0) Address: FFF9DH After reset: 00H Symbol <7> <5> <4> RTCC0 RTCE RCLOE1 RCLOE0 AMPM RTCE Real-time counter operation control Stops counter operation. Starts counter operation. RCLOE1 RTC1HZ pin output control Disables output of RTC1HZ pin (1 Hz).
Page 278 CHAPTER 7 REAL-TIME COUNTER (3) Real-time counter control register 1 (RTCC1) The RTCC1 register is an 8-bit register that is used to control the alarm interrupt function and the wait time of the counter. RTCC1 can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears this register to 00H.
Page 279 CHAPTER 7 REAL-TIME COUNTER Figure 7-4. Format of Real-Time Counter Control Register 1 (RTCC1) (2/2) RIFG Constant-period interrupt status flag Constant-period interrupt is not generated. Constant-period interrupt is generated. This flag indicates the status of generation of the constant-period interrupt. When the constant-period interrupt is generated, it is set to “1”.
Page 280 CHAPTER 7 REAL-TIME COUNTER (4) Real-time counter control register 2 (RTCC2) The RTCC2 register is an 8-bit register that is used to control the interval interrupt function and the RTCDIV pin. RTCC2 can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears this register to 00H.
Page 281 CHAPTER 7 REAL-TIME COUNTER (5) Sub-count register (RSUBC) The RSUBC register is a 16-bit register that counts the reference time of 1 second of the real-time counter. It takes a value of 0000H to 7FFFH and counts 1 second with a clock of 32.768 kHz. RSUBC can be set by a 16-bit memory manipulation instruction.
Page 282 CHAPTER 7 REAL-TIME COUNTER (7) Minute count register (MIN) The MIN register is an 8-bit register that takes a value of 0 to 59 (decimal) and indicates the count value of minutes. It counts up when the second counter overflows. When data is written to this register, it is written to a buffer and then to the counter up to 2 clocks (32.768 kHz) later.
Page 283 CHAPTER 7 REAL-TIME COUNTER Table 7-2. Displayed Time Digits 24-Hour Display (AMPM Bit = 1) 12-Hour Display (AMPM Bit = 0) Time HOUR Register Time HOUR Register 0 a.m. 1 a.m. 2 a.m. 3 a.m. 4 a.m. 5 a.m. 6 a.m. 7 a.m.
Page 284 CHAPTER 7 REAL-TIME COUNTER (9) Day count register (DAY) The DAY register is an 8-bit register that takes a value of 1 to 31 (decimal) and indicates the count value of days. It counts up when the hour counter overflows. This counter counts as follows.
Page 285 CHAPTER 7 REAL-TIME COUNTER Figure 7-11. Format of Week Count Register (WEEK) Address: FFF95H After reset: 00H Symbol WEEK WEEK4 WEEK2 WEEK1 Caution The value corresponding to the month count register or the day count register is not stored in the week count register automatically. After reset release, set the week count register as follow.
Page 286 CHAPTER 7 REAL-TIME COUNTER (11) Month count register (MONTH) The MONTH register is an 8-bit register that takes a value of 1 to 12 (decimal) and indicates the count value of months. It counts up when the day counter overflows. When data is written to this register, it is written to a buffer and then to the counter up to 2 clocks (32.768 kHz) later.
Page 287 CHAPTER 7 REAL-TIME COUNTER (13) Watch error correction register (SUBCUD) This register is used to correct the watch with high accuracy when it is slow or fast by changing the value (reference value: 7FFFH) that overflows from the sub-count register (RSUBC) to the second count register. SUBCUD can be set by an 8-bit memory manipulation instruction.
Page 288 CHAPTER 7 REAL-TIME COUNTER (14) Alarm minute register (ALARMWM) This register is used to set minutes of alarm. ALARMWM can be set by an 8-bit memory manipulation instruction. Reset signal generation clears this register to 00H. Caution Set a decimal value of 00 to 59 to this register in BCD code. If a value outside the range is set, the alarm is not detected.
Page 289 CHAPTER 7 REAL-TIME COUNTER Here is an example of setting the alarm. Time of Alarm 12-Hour Display 24-Hour Display Sunday Friday Hour Hour Minute Minute Hour Hour Minute Minute Monday Tuesday Thursday Saturday Wednesday Every day, 0:00 a.m. Every day, 1:30 a.m. Every day, 11:59 a.m.
Page 290: Real-Time Counter Operation
CHAPTER 7 REAL-TIME COUNTER 7.4 Real-Time Counter Operation 7.4.1 Starting operation of real-time counter Figure 7-19. Procedure for Starting Operation of Real-Time Counter Start Note 1 Supplies input clock. RTCEN = 1 RTCE = 0 Stops counter operation. Setting AMPM, CT2 to CT0 Selects 12-/24-hour system and interrupt (INTRTC).
Page 291: Shifting To Stop Mode After Starting Operation
CHAPTER 7 REAL-TIME COUNTER 7.4.2 Shifting to STOP mode after starting operation Perform one of the following processing when shifting to STOP mode immediately after setting RTCE to 1. However, after setting RTCE to 1, this processing is not required when shifting to STOP mode after the first INTRTC interrupt has occurred.
Page 292: Reading/Writing Real-Time Counter
CHAPTER 7 REAL-TIME COUNTER 7.4.3 Reading/writing real-time counter Read or write the counter after setting 1 to RWAIT first. Figure 7-21. Procedure for Reading Real-Time Counter Start Stops SEC to YEAR counters. RWAIT = 1 Mode to read and write count values RWST = 1? Checks wait status of counter.
Page 293 CHAPTER 7 REAL-TIME COUNTER Figure 7-22. Procedure for Writing Real-Time Counter Start Stops SEC to YEAR counters. RWAIT = 1 Mode to read and write count values RWST = 1? Checks wait status of counter. Writing SEC Writes second count register. Writing MIN Writes minute count register.
Page 294: Setting Alarm Of Real-Time Counter
CHAPTER 7 REAL-TIME COUNTER 7.4.4 Setting alarm of real-time counter Set time of alarm after setting 0 to WALE first. Figure 7-23. Alarm Setting Procedure Start Match operation of alarm is invalid. WALE = 0 Interrupt is generated when alarm matches. WALIE = 1 Setting ALARMWM Sets alarm minute register.
Page 295: Hz Output Of Real-Time Counter
CHAPTER 7 REAL-TIME COUNTER 7.4.5 1 Hz output of real-time counter Figure 7-24. 1 Hz Output Setting Procedure Start Stops counter operation. RTCE = 0 RCLOE1 = 1 Enables output of RTC1HZ pin (1 Hz). RTCE = 1 Starts counter operation. Output start from RTC1HZ pin <R>...
Page 296: Example Of Watch Error Correction Of Real-Time Counter
CHAPTER 7 REAL-TIME COUNTER 7.4.8 Example of watch error correction of real-time counter The watch can be corrected with high accuracy when it is slow or fast, by setting a value to the watch error correction register. Example of calculating the correction value The correction value used when correcting the count value of the sub-count register (RSUBC) is calculated by using the following expression.
Page 297 CHAPTER 7 REAL-TIME COUNTER Correction example <1> Example of correcting from 32772.3 Hz to 32768 Hz (32772.3 Hz − 131.2 ppm) [Measuring the oscillation frequency] Note The oscillation frequency of each product is measured by outputting about 32 kHz from the RTCCL pin or outputting about 1 Hz from the RTC1HZ pin when the watch error correction register is set to its initial value (00H).
Page 298 Figure 7-27. Operation When (DEV, F6, F5, F4, F3, F2, F1, F0) = (0, 0, 1, 0, 1, 1, 0, 0) 7FFFH + 56H (86) 7FFFH + 56H (86) 7FFFH + 56H (86) 7FFFH+56H (86) Count start RSUBC 0000H 8054H 8055H 0000H 0001H 7FFFH 0000H 0001H...
Page 299 CHAPTER 7 REAL-TIME COUNTER Correction example <2> Example of correcting from 32767.4 Hz to 32768 Hz (32767.4 Hz + 18.3 ppm) [Measuring the oscillation frequency] Note The oscillation frequency of each product is measured by outputting about 32 kHz from the RTCCL pin or outputting about 1 Hz from the RTC1HZ pin when the watch error correction register is set to its initial value (00H).
Page 300 Figure 7-28. Operation When (DEV, F6, F5, F4, F3, F2, F1, F0) = (1, 1, 1, 0, 1, 1, 1, 0) 7FFFH − 24H (36) 7FFFH − 24H (36) Count start RSUBC 0000H 7FDAH 7FDBH 0000H 0001H 7FFFH 0000H 0001H 7FFFH 0000H 0001H 7FFFH 0000H 0001H...
Page 301: Chapter 8 Watchdog Timer
CHAPTER 8 WATCHDOG TIMER 8.1 Functions of Watchdog Timer The watchdog timer operates on the internal low-speed oscillation clock. The watchdog timer is used to detect an inadvertent program loop. If a program loop is detected, an internal reset signal is generated. Program loop is detected in the following cases.
Page 302: Configuration Of Watchdog Timer
CHAPTER 8 WATCHDOG TIMER 8.2 Configuration of Watchdog Timer The watchdog timer includes the following hardware. Table 8-1. Configuration of Watchdog Timer Item Configuration Control register Watchdog timer enable register (WDTE) How the counter operation is controlled, overflow time, window open period, and interval interrupt are set by the option byte.
Page 303: Register Controlling Watchdog Timer
CHAPTER 8 WATCHDOG TIMER 8.3 Register Controlling Watchdog Timer The watchdog timer is controlled by the watchdog timer enable register (WDTE). (1) Watchdog timer enable register (WDTE) Writing “ACH” to WDTE clears the watchdog timer counter and starts counting again. This register can be set by an 8-bit memory manipulation instruction.
Page 304: Operation Of Watchdog Timer
CHAPTER 8 WATCHDOG TIMER 8.4 Operation of Watchdog Timer 8.4.1 Controlling operation of watchdog timer When the watchdog timer is used, its operation is specified by the option byte (000C0H). • Enable counting operation of the watchdog timer by setting bit 4 (WDTON) of the option byte (000C0H) to 1 (the counter starts operating after a reset release) (for details, see CHAPTER 23).
Page 305: Setting Overflow Time Of Watchdog Timer
CHAPTER 8 WATCHDOG TIMER Cautions 4. The operation of the watchdog timer in the HALT and STOP modes differs as follows depending on the set value of bit 0 (WDSTBYON) of the option byte (000C0H). WDSTBYON = 0 WDSTBYON = 1 In HALT mode Watchdog timer operation stops.
Page 306: Setting Window Open Period Of Watchdog Timer
CHAPTER 8 WATCHDOG TIMER 8.4.3 Setting window open period of watchdog timer Set the window open period of the watchdog timer by using bits 6 and 5 (WINDOW1, WINDOW0) of the option byte (000C0H). The outline of the window is as follows. •...
Page 307: Setting Watchdog Timer Interval Interrupt
CHAPTER 8 WATCHDOG TIMER Remarks.1 If the overflow time is set to 2 , the window close time and open time are as follows. Setting of Window Open Period 100% Window close time 0 to 3.56 ms 0 to 2.37 ms 0 to 0.119 ms None Window open time...
Page 308: Chapter 9 Clock Output/Buzzer Output Controller
CHAPTER 9 CLOCK OUTPUT/BUZZER OUTPUT CONTROLLER 9.1 Functions of Clock Output/Buzzer Output Controller The clock output controller is intended for carrier output during remote controlled transmission and clock output for supply to peripheral ICs. Buzzer output is a function to output a square wave of buzzer frequency. One pin can be used to output a clock or buzzer sound.
Page 309: Configuration Of Clock Output/Buzzer Output Controller
CHAPTER 9 CLOCK OUTPUT/BUZZER OUTPUT CONTROLLER 9.2 Configuration of Clock Output/Buzzer Output Controller The clock output/buzzer output controller includes the following hardware. Table 9-1. Configuration of Clock Output/Buzzer Output Controller Item Configuration Control registers Clock output select registers 0, 1 (CKS0, CKS1) Port mode register 14 (PM14) Port register 14 (P14) 9.3 Registers Controlling Clock Output/Buzzer Output Controller...
Page 310 CHAPTER 9 CLOCK OUTPUT/BUZZER OUTPUT CONTROLLER Figure 9-2. Format of Clock Output Select Register n (CKSn) Address: FFFA5H After reset: 00H Symbol <7> CKSn PCLOEn CSELn CCSn2 CCSn1 CCSn0 PCLOEn PCLBUZn output enable/disable specification Output disable (default) Output enable CSELn CCSn2 CCSn1 CCSn0...
Page 311: Operations Of Clock Output/Buzzer Output Controller
CHAPTER 9 CLOCK OUTPUT/BUZZER OUTPUT CONTROLLER (2) Port mode register 14 (PM14) This register sets port 14 input/output in 1-bit units. When using the P140/INTP6/PCLBUZ0 and P141/INTP7/PCLBUZ1 pins for clock output/buzzer output, clear PM140 and PM141 and the output latches of P140 and P141 to 0. PM14 is set by a 1-bit or 8-bit memory manipulation instruction.
Page 312: Chapter 10 A/D Converter
CHAPTER 10 A/D CONVERTER 10.1 Function of A/D Converter The A/D converter converts an analog input signal into a digital value, and consists of up to 8 channels (ANI0 to ANI7) with a resolution of 10 bits. The A/D converter has the following function. •...
Page 313: Configuration Of A/D Converter
CHAPTER 10 A/D CONVERTER 10.2 Configuration of A/D Converter The A/D converter includes the following hardware. (1) ANI0 to ANI7 pins These are the analog input pins of the 8-channel A/D converter. They input analog signals to be converted into digital signals.
Page 314 CHAPTER 10 A/D CONVERTER (8) Controller This circuit controls the conversion time of an input analog signal that is to be converted into a digital signal, as well as starting and stopping of the conversion operation. When A/D conversion has been completed, this controller generates INTAD.
Page 315: Registers Used In A/D Converter
CHAPTER 10 A/D CONVERTER 10.3 Registers Used in A/D Converter The A/D converter uses the following seven registers. • Peripheral enable register 0 (PER0) • A/D converter mode register (ADM) • A/D port configuration register (ADPC) • Analog input channel specification register (ADS) •...
Page 316 CHAPTER 10 A/D CONVERTER (2) A/D converter mode register (ADM) This register sets the conversion time for analog input to be A/D converted, and starts/stops conversion. ADM can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears this register to 00H. Figure 10-4.
Page 317 CHAPTER 10 A/D CONVERTER Table 10-3. A/D Conversion Time Selection (1) 2.7 V ≤ AV ≤ 5.5 V REF0 A/D Converter Mode Register (ADM) Conversion Time Selection Conversion Clock = 2 MHz = 10 MHz = 20 MHz μ μ 264/f 26.4 13.2...
Page 318 CHAPTER 10 A/D CONVERTER (2) 2.3 V ≤ AV ≤ 5.5 V REF0 A/D Converter Mode Register (ADM) Conversion Time Selection Conversion Clock = 2 MHz = 5 MHz 480/f Setting prohibited Setting prohibited μ 320/f 64.0 μ 240/f 48.0 μ...
Page 319 CHAPTER 10 A/D CONVERTER Figure 10-6. A/D Converter Sampling and A/D Conversion Timing ← ADCS 1 or ADS rewrite ADCS Sampling timing INTAD Sampling Successive conversion Sampling Transfer clear to ADCR, clear INTAD generation Conversion time Conversion time User’s Manual U17893EJ8V0UD...
Page 320 CHAPTER 10 A/D CONVERTER (3) 10-bit A/D conversion result register (ADCR) This register is a 16-bit register that stores the A/D conversion result. The lower 6 bits are fixed to 0. Each time A/D conversion ends, the conversion result is loaded from the successive approximation register. The higher 8 bits of the conversion result are stored in FFF1FH and the lower 2 bits are stored in the higher 2 bits of FFF1EH.
Page 321 CHAPTER 10 A/D CONVERTER (5) Analog input channel specification register (ADS) This register specifies the input channel of the analog voltage to be A/D converted. ADS can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears this register to 00H. Figure 10-9.
Page 322 CHAPTER 10 A/D CONVERTER (6) A/D port configuration register (ADPC) This register switches the ANI0/P20 to ANI7/P27 pins to analog input of A/D converter or digital I/O of port. ADPC can be set by an 8-bit memory manipulation instruction. Reset signal generation sets this register to 10H. Figure 10-10.
Page 323 CHAPTER 10 A/D CONVERTER (7) Port mode registers 2 (PM2) When using the ANI0/P20 to ANI7/P27 pins for analog input port, set PM20 to PM27 to 1. The output latches of P20 to P27 at this time may be 0 or 1. If PM20 to PM27 are set to 0, they cannot be used as analog input port pins.
Page 324: A/D Converter Operations
CHAPTER 10 A/D CONVERTER 10.4 A/D Converter Operations 10.4.1 Basic operations of A/D converter <1> Set bit 5 (ADCEN) of peripheral enable register 0 (PER0) to 1 to start the supply of the input clock to the A/D converter. <2> Set bit 0 (ADCE) of the A/D converter mode register (ADM) to 1 to start the operation of the A/D voltage comparator.
Page 325 CHAPTER 10 A/D CONVERTER Figure 10-12. Basic Operation of A/D Converter Conversion time Sampling time A/D converter Sampling A/D conversion operation Conversion Undefined result Conversion ADCR result INTAD A/D conversion operations are performed continuously until bit 7 (ADCS) of the A/D converter mode register (ADM) is reset (0) by software.
Page 326: Input Voltage And Conversion Results
CHAPTER 10 A/D CONVERTER 10.4.2 Input voltage and conversion results The relationship between the analog input voltage input to the analog input pins (ANI0 to ANI7) and the theoretical A/D conversion result (stored in the 10-bit A/D conversion result register (ADCR)) is shown by the following expression.
Page 327: A/D Converter Operation Mode
CHAPTER 10 A/D CONVERTER 10.4.3 A/D converter operation mode The operation mode of the A/D converter is the select mode. One channel of analog input is selected from ANI0 to ANI7 by the analog input channel specification register (ADS) and A/D conversion is executed. (1) A/D conversion operation By setting bit 7 (ADCS) of the A/D converter mode register (ADM) to 1, the A/D conversion operation of the voltage, which is applied to the analog input pin specified by the analog input channel specification register...
Page 328 CHAPTER 10 A/D CONVERTER The setting methods are described below. <1> Set bit 5 (ADCEN) of peripheral enable register 0 (PER0) to 1. <2> Set bit 0 (ADCE) of the A/D converter mode register (ADM) to 1. <3> Set the channel to be used in the analog input mode by using bits 4 to 0 (ADPC4 to ADPC0) of the A/D port configuration register (ADPC) and bits 7 to 0 (PM27 to PM20) of port mode register 2 (PM2).
Page 329: Temperature Sensor Function
CHAPTER 10 A/D CONVERTER μ 10.5 Temperature Sensor Function (Expanded-Specification Products ( PD78F115xA) Only) A temperature sensor performs A/D conversion for two voltages, an internal reference voltage (sensor 0 on the ANI0 side) that depends on the temperature and an internal reference voltage (sensor 1 on the ANI1 side) that does not depend on the temperature, and calculations, so that the temperature is obtained without depending on the AV REF0 ≥...
Page 330: Registers Used By Temperature Sensors
CHAPTER 10 A/D CONVERTER 10.5.2 Registers used by temperature sensors The following four types of registers are used when using a temperature sensor. • Peripheral enable register 0 (PER0) • A/D converter mode register (ADM) • Analog input channel specification register (ADS) •...
Page 331 CHAPTER 10 A/D CONVERTER (3) 10-bit A/D conversion result register (ADCR) Use the ADCR register in the same manner as during A/D converter basic operation (see 10.3 (3) 10-bit A/D conversion result register (ADCR)). Caution When using a temperature sensor, use the result of the second or later A/D conversion for temperature sensor 0 (ANI0 side), and the result of the third or later A/D conversion for temperature sensor 1 (ANI1 side).
Page 332: Temperature Sensor Operation
CHAPTER 10 A/D CONVERTER 10.5.3 Temperature sensor operation (1) Temperature sensor detection value When using a temperature sensor, determine as reference temperatures two points of temperature (high and low) in the temperature range to be used, and measure the result of A/D conversion with temperature sensors 0 and 1 at each reference temperature in advance.
Page 333 CHAPTER 10 A/D CONVERTER (2) How to calculate temperature As shown in Figure 10-17, the temperature sensor detection value makes a characteristics curve that is linear with respect to the temperature. Therefore, the temperature sensor detection value can be expressed with the following expressions.
Page 334: Procedures For Using Temperature Sensors
CHAPTER 10 A/D CONVERTER 10.5.4 Procedures for using temperature sensors (1) Procedure for using temperature sensors <1> Perform the following steps in the same environment as the one in which the temperature sensor is used in a set • When obtaining a temperature through calculation Determine as reference temperatures two points of temperature (high and low) in the temperature range to be used, and measure the result of A/D conversion with temperature sensors 0 and 1 at the reference temperature in advance, before shipment of the set.
Page 335 CHAPTER 10 A/D CONVERTER <Obtaining temperature T > <14> Calculate the temperature by using either of the following methods. • When obtaining a temperature through calculation During measurement at reference temperatures, write ADT0 and ADT1 to the internal flash memory by means such as self programming.
Page 336 CHAPTER 10 A/D CONVERTER Figure 10-18. Flowchart of Procedure for Using Temperature Sensor START ADCEN of PER0 register = 1 <1> Starts the supply of the input clock to A/D converter <2> ADCE of ADM register = 1 Starts the operation of the comparator ADM ←...
Page 337: How To Read A/D Converter Characteristics Table
CHAPTER 10 A/D CONVERTER 10.6 How to Read A/D Converter Characteristics Table Here, special terms unique to the A/D converter are explained. (1) Resolution This is the minimum analog input voltage that can be identified. That is, the percentage of the analog input voltage per bit of digital output is called 1LSB (Least Significant Bit).
Page 338 CHAPTER 10 A/D CONVERTER (5) Full-scale error This shows the difference between the actual measurement value of the analog input voltage and the theoretical value (Full-scale − 3/2LSB) when the digital output changes from 1..110 to 1..111. (6) Integral linearity error This shows the degree to which the conversion characteristics deviate from the ideal linear relationship.
Page 339: Cautions For A/D Converter
CHAPTER 10 A/D CONVERTER 10.7 Cautions for A/D Converter (1) Operating current in STOP mode Shift to STOP mode after clearing the A/D converter (by clearing bit 7 (ADCS) of the A/D converter mode register (ADM) to 0). The operating current can be reduced by clearing bit 0 (ADCE) of the A/D converter mode register (ADM) to 0 at the same time.
Page 340 CHAPTER 10 A/D CONVERTER (3) Input range of ANI0 to ANI7 Observe the rated range of the ANI0 to ANI7 input voltage. If a voltage of AV or higher and AV or lower REF0 (even in the range of absolute maximum ratings) is input to an analog input channel, the converted value of that channel becomes undefined.
Page 341 CHAPTER 10 A/D CONVERTER (6) ANI0/P20 to ANI7/P27 <1> The analog input pins (ANI0 to ANI7) are also used as input port pins (P20 to P27). When A/D conversion is performed with any of ANI0 to ANI7 selected, do not access P20 to P27 while conversion is in progress;...
Page 342 CHAPTER 10 A/D CONVERTER (9) Interrupt request flag (ADIF) The interrupt request flag (ADIF) is not cleared even if the analog input channel specification register (ADS) is changed. Therefore, if an analog input pin is changed during A/D conversion, the A/D conversion result and ADIF for the pre-change analog input may be set just before the ADS rewrite.
Page 343 CHAPTER 10 A/D CONVERTER (12) Internal equivalent circuit The equivalent circuit of the analog input block is shown below. Figure 10-28. Internal Equivalent Circuit of ANIn Pin ANIn Table 10-6. Resistance and Capacitance Values of Equivalent Circuit (Reference Values) REF0 4.0 V ≤...
Page 344: Chapter 11 D/A Converter
CHAPTER 11 D/A CONVERTER 11.1 Function of D/A Converter The D/A converter has a resolution of 8 bits and converts an input digital signal into an analog signal. It is configured so that output analog signals of two channels (ANO0 and ANO1) can be controlled. The D/A converter has the following features.
Page 345 CHAPTER 11 D/A CONVERTER The D/A converter includes the following hardware. Table 11-1. Configuration of D/A Converter Item Configuration Control registers Peripheral enable register 0 (PER0) D/A converter mode register (DAM) 8-bit D/A conversion value setting registers 0, 1 (DACS0, DACS1) (1) AV REF1 This is the D/A converter reference voltage input pin and the positive power supply pin of P110, P111, and the...
Page 346: Registers Used In D/A Converter
CHAPTER 11 D/A CONVERTER 11.3 Registers Used in D/A Converter The D/A converter uses the following three registers. • Peripheral enable register 0 (PER0) • D/A converter mode register (DAM) • 8-bit D/A conversion value setting registers 0, 1 (DACS0, DACS1) •...
Page 347 CHAPTER 11 D/A CONVERTER (2) D/A converter mode register (DAM) This register controls the operation of the D/A converter. DAM can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears this register to 00H. Figure 11-3. Format of D/A Converter Mode Register (DAM) Address: FFF32H After reset: 00H Symbol...
Page 348 CHAPTER 11 D/A CONVERTER (4) Port mode register 11 (PM11) This register sets the input or output of port 11 in 1-bit units. When using the P110/ANO0 and P111/ANO1 pins as the analog output function of the D/A converter, set both PM110 and PM111 to 1.
Page 349: Operation Of D/A Converter
CHAPTER 11 D/A CONVERTER 11.4 Operation of D/A Converter 11.4.1 Operation in normal mode D/A conversion is performed using write operation to the DACSn register as the trigger. The setting method is described below. <1> Set the DAMDn bit of the DAM register to 0 (normal mode). <2>...
Page 350: Operation In Real-Time Output Mode
CHAPTER 11 D/A CONVERTER 11.4.2 Operation in real-time output mode D/A conversion is performed using the interrupt request signals (INTTM04 and INTTM05) of timer channel 4 and timer channel 5 as triggers. The setting method is described below. <1> Set the DAMDn bit of the DAM register to 1 (real-time output mode). <2>...
Page 351: Cautions
CHAPTER 11 D/A CONVERTER 11.4.3 Cautions Observe the following cautions when using the D/A converter of the 78K0R/KF3. (1) The digital port I/O function, which is the alternate function of the ANO0 and ANO1 pins, does not operate during D/A conversion.
Page 352: Chapter 12 Serial Array Unit
The serial array unit has four serial channels per unit and can use two or more of various serial interfaces (3-wire serial (CSI), UART, and simplified I C) in combination. Function assignment of each channel supported by the 78K0R/KF3 is as shown below (channels 2 and 3 of unit 1 are dedicated to UART3 (supporting LIN-bus)). Used as Simplified I...
Page 353: Uart (Uart0, Uart1, Uart2, Uart3)
CHAPTER 12 SERIAL ARRAY UNIT 12.1.2 UART (UART0, UART1, UART2, UART3) This is a start-stop synchronization function using two lines: serial data transmission (T D) and serial data reception (R D) lines. It transmits or receives data in asynchronization with the party of communication (by using an internal baud rate).
Page 354: Simplified I C (Iic10, Iic20)
CHAPTER 12 SERIAL ARRAY UNIT 12.1.3 Simplified I C (IIC10, IIC20) This is a clocked communication function to communicate with two or more devices by using two lines: serial clock (SCL) and serial data (SDA). This simplified I C is designed for single communication with a device such as EEPROM, flash memory, or A/D converter, and therefore, it functions only as a master and does not have a function to detect wait states.
Page 355: Configuration Of Serial Array Unit
CHAPTER 12 SERIAL ARRAY UNIT 12.2 Configuration of Serial Array Unit Serial array unit includes the following hardware. Table 12-1. Configuration of Serial Array Unit Item Configuration Shift register 8 bits Note Buffer register Lower 8 bits of serial data register mn (SDRmn) Serial clock I/O SCK00, SCK01, SCK10, SCK20 pins (for 3-wire serial I/O), SCL10, SCL20 pins (for simplified Serial data input...
Page 356 CHAPTER 12 SERIAL ARRAY UNIT Figure 12-1 shows the block diagram of serial array unit 0. Figure 12-1. Block Diagram of Serial Array Unit 0 Noise filter enable Serial output register 0 (SO0) register 0 (NFEN0) SNFEN SNFEN CKO02 CKO01 CKO00 SO02 SO01 SO00 Peripheral enable...
Page 357 CHAPTER 12 SERIAL ARRAY UNIT Figure 12-2 shows the block diagram of serial array unit 1. Figure 12-2. Block Diagram of Serial Array Unit 1 Noise filter enable Serial output register 1 (SO1) register 0 (NFEN0) SNFEN SNFEN CKO10 SO10 SO12 Peripheral enable Serial channel enable...
Page 358 CHAPTER 12 SERIAL ARRAY UNIT (1) Shift register This is an 8-bit register that converts parallel data into serial data or vice versa. During reception, it converts data input to the serial pin into parallel data. When data is transmitted, the value set to this register is output as serial data from the serial output pin. The shift register cannot be directly manipulated by program.
Page 359 CHAPTER 12 SERIAL ARRAY UNIT Figure 12-3. Format of Serial Data Register mn (SDRmn) Address: FFF10H, FFF11H (SDR00), FFF12H, FFF13H (SDR01), After reset: 0000H FFF44H, FFF45H (SDR02), FFF46H, FFF47H (SDR03), FFF48H, FFF49H (SDR10), FFF4AH, FFF4BH (SDR11), FFF14H, FFF15H (SDR12), FFF16H, FFF17H (SDR13) FFF11H (SDR00) FFF10H (SDR00) SDRmn...
Page 360: Registers Controlling Serial Array Unit
CHAPTER 12 SERIAL ARRAY UNIT 12.3 Registers Controlling Serial Array Unit Serial array unit is controlled by the following registers. • Peripheral enable register 0 (PER0) • Serial clock select register m (SPSm) • Serial mode register mn (SMRmn) • Serial communication operation setting register mn (SCRmn) •...
Page 361 CHAPTER 12 SERIAL ARRAY UNIT (1) Peripheral enable register 0 (PER0) PER0 is used to enable or disable use of each peripheral hardware macro. Clock supply to a hardware macro that is not used is stopped in order to reduce the power consumption and noise. When serial array unit 0 is used, be sure to set bit 2 (SAU0EN) of this register to 1.
Page 362 CHAPTER 12 SERIAL ARRAY UNIT Figure 12-5. Format of Serial Clock Select Register m (SPSm) Address: F0126H, F0127H (SPS0), F0166H, F0167H (SPS1) After reset: 0000H Symbol SPSm Note 1 Section of operation clock (CKmp) = 2 MHz = 5 MHz = 10 MHz = 20 MHz 2 MHz...
Page 363 CHAPTER 12 SERIAL ARRAY UNIT (3) Serial mode register mn (SMRmn) SMRmn is a register that sets an operation mode of channel n. It is also used to select an operation clock (MCK), specify whether the serial clock (SCK) may be input or not, set a start trigger, an operation mode (CSI, UART, or I C), and an interrupt source.
Page 364 CHAPTER 12 SERIAL ARRAY UNIT Figure 12-6. Format of Serial Mode Register mn (SMRmn) (2/2) Address: F0110H, F0111H (SMR00) to F0116H, F0117H (SMR03), After reset: 0020H F0150H, F0151H (SMR10), F0152H, F0153H (SMR11), F0154H, F0155H (SMR12), F0156H, F0157H (SMR13) Symbol SMRmn Controls inversion of level of receive data of channel n in UART mode Falling edge is detected as the start bit.
Page 365 CHAPTER 12 SERIAL ARRAY UNIT (4) Serial communication operation setting register mn (SCRmn) SCRmn is a communication operation setting register of channel n. It is used to set a data transmission/reception mode, phase of data and clock, whether an error signal is to be masked or not, parity bit, start bit, stop bit, and data length.
Page 366 CHAPTER 12 SERIAL ARRAY UNIT Figure 12-7. Format of Serial Communication Operation Setting Register mn (SCRmn) (2/3) Address: F0118H, F0119H (SCR00) to F011EH, F011FH (SCR03), After reset: 0087H F0158H, F0159H (SCR10), F015AH, F015BH (SCR11), F015CH, F015DH (SCR12), F015EH, F015FH (SCR13) Symbol SCRmn Selection of masking of error interrupt signal (INTSREx (x = 0 to 3))
Page 367 CHAPTER 12 SERIAL ARRAY UNIT Figure 12-7. Format of Serial Communication Operation Setting Register mn (SCRmn) (3/3) Address: F0118H, F0119H (SCR00) to F011EH, F011FH (SCR03), After reset: 0087H F0158H, F0159H (SCR10), F015AH, F015BH (SCR11), F015CH, F015DH (SCR12), F015EH, F015FH (SCR13) Symbol SCRmn Setting of data length in CSI and UART modes...
Page 368 CHAPTER 12 SERIAL ARRAY UNIT (5) Higher 7 bits of the serial data register mn (SDRmn) SDRmn is the transmit/receive data register (16 bits) of channel n. Bits 7 to 0 function as a transmit/receive buffer register, and bits 15 to 9 are used as a register that sets the division ratio of the operation clock (MCK). If the CCSmn bit of serial mode register mn (SMRmn) is cleared to 0, the clock set by dividing the operating clock by the higher 7 bits of SDRmn is used as the transfer clock.
Page 369 CHAPTER 12 SERIAL ARRAY UNIT (6) Serial status register mn (SSRmn) SSRmn is a register that indicates the communication status and error occurrence status of channel n. The errors indicated by this register are a framing error, parity error, and overrun error. SSRmn can be read by a 16-bit memory manipulation instruction.
Page 370 CHAPTER 12 SERIAL ARRAY UNIT Figure 12-9. Format of Serial Status Register mn (SSRmn) (2/2) Address: F0100H, F0101H (SSR00) to F0106H, F0107H (SSR03), After reset: 0000H F0140H, F0141H (SSR10), F0142H, F0143H (SSR11), F0144H, F0145H (SSR12), F0146H, F0147H (SSR13) Symbol SSRmn Framing error detection flag of channel n No error occurs.
Page 371 CHAPTER 12 SERIAL ARRAY UNIT (7) Serial flag clear trigger register mn (SIRmn) SIRmn is a trigger register that is used to clear each error flag of channel n. When each bit (FECTmn, PECTmn, OVCTmn) of this register is set to 1, the corresponding bit (FEFmn, PEFmn, OVFmn) of serial status register mn is cleared to 0.
Page 372 CHAPTER 12 SERIAL ARRAY UNIT (8) Serial channel enable status register m (SEm) SEm indicates whether data transmission/reception operation of each channel is enabled or stopped. When 1 is written a bit of serial channel start register m (SSm), the corresponding bit of this register is set to 1. When 1 is written a bit of serial channel stop register m (STm), the corresponding bit is cleared to 0.
Page 373 CHAPTER 12 SERIAL ARRAY UNIT (9) Serial channel start register m (SSm) SSm is a trigger register that is used to enable starting communication/count by each channel. When 1 is written a bit of this register (SSmn), the corresponding bit (SEmn) of serial channel enable status register m (SEm) is set to 1.
Page 374 CHAPTER 12 SERIAL ARRAY UNIT (10) Serial channel stop register m (STm) STm is a trigger register that is used to enable stopping communication/count by each channel. When 1 is written a bit of this register (STmn), the corresponding bit (SEmn) of serial channel enable status register m (SEm) is cleared to 0.
Page 375 CHAPTER 12 SERIAL ARRAY UNIT (11) Serial output enable register m (SOEm) SOEm is a register that is used to enable or stop output of the serial communication operation of each channel. Channel n that enables serial output cannot rewrite by software the value of SOmn of the serial output register m (SOm) to be described below, and a value reflected by a communication operation is output from the serial data output pin.
Page 376 CHAPTER 12 SERIAL ARRAY UNIT (12) Serial output register m (SOm) SOm is a buffer register for serial output of each channel. The value of bit n of this register is output from the serial data output pin of channel n. The value of bit (n + 8) of this register is output from the serial clock output pin of channel n.
Page 377 CHAPTER 12 SERIAL ARRAY UNIT (13) Serial output level register m (SOLm) SOLm is a register that is used to set inversion of the data output level of each channel. This register can be set only in the UART mode. Be sure to set 0000H in the CSI mode and simplifies I mode.
Page 378 CHAPTER 12 SERIAL ARRAY UNIT (14) Input switch control register (ISC) ISC is used to realize a LIN-bus communication operation by UART3 in coordination with an external interrupt and the timer array unit. When bit 0 is set to 1, the input signal of the serial data input (R D3) pin is selected as an external interrupt (INTP0) that can be used to detect a wakeup signal.
Page 379 CHAPTER 12 SERIAL ARRAY UNIT (15) Noise filter enable register 0 (NFEN0) NFEN0 is used to set whether the noise filter can be used for the input signal from the serial data input pin to each channel. Disable the noise filter of the pin used for CSI or simplified I C communication, by clearing the corresponding bit of this register to 0.
Page 380 CHAPTER 12 SERIAL ARRAY UNIT (16) Port input mode registers 0, 4, 14 (PIM0, PIM4, PIM14) These registers set the input buffer of ports 0, 4, and 14 in 1-bit units. PIM0, PIM4, and PIM14 can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears these registers to 00H.
Page 381 CHAPTER 12 SERIAL ARRAY UNIT (18) Port mode registers 0, 1, 4, 14 (PM0, PM1, PM4, PM14) These registers set input/output of ports 0, 1, 4 and 14 in 1-bit units. When using P02/SO10/T P03/SI10/R D1/SDA10, P04/SCK10/SCL10, P10/SCK00/, P12/SO00/T D0/, P13/T D3/, P43/SCK01, P45/SO01, P142/SCK20/SCL20, P143/SI20/R D2/SDA20, and P144/SO20/T...
Page 382: Operation Stop Mode
CHAPTER 12 SERIAL ARRAY UNIT 12.4 Operation stop mode Each serial interface of serial array unit has the operation stop mode. In this mode, serial communication cannot be executed, thus reducing the power consumption. In addition, the P02/SO10/TxD1, P03/SI10/SDA10/RxD1, P04/SCK10/SCL10, P10/SCK00, P11/SI00/RxD0, P12/SO00/TxD0, P13/TxD3, P14/RxD3,...
Page 383: Stopping The Operation By Channels
CHAPTER 12 SERIAL ARRAY UNIT 12.4.2 Stopping the operation by channels The stopping of the operation by channels is set using each of the following registers. Figure 12-23. Each Register Setting When Stopping the Operation by Channels (1/2) (a) Serial Channel Enable Status Register m (SEm) … This register indicates whether data transmission/reception operation of each channel is enabled or stopped.
Page 384 CHAPTER 12 SERIAL ARRAY UNIT Figure 12-23. Each Register Setting When Stopping the Operation by Channels (2/2) (d) Serial output register m (SOm) …This register is a buffer register for serial output of each channel. CKO02 CKO01 CKO00 SO02 SO01 SO00 1: Serial clock output value is “1”...
Page 385: Operation Of 3-Wire Serial I/O (Csi00, Csi01, Csi10, Csi20) Communication
CHAPTER 12 SERIAL ARRAY UNIT 12.5 Operation of 3-Wire Serial I/O (CSI00, CSI01, CSI10, CSI20) Communication This is a clocked communication function that uses three lines: serial clock (SCK) and serial data (SI and SO) lines. [Data transmission/reception] • Data length of 7 or 8 bits •...
Page 386: Master Transmission
CHAPTER 12 SERIAL ARRAY UNIT 12.5.1 Master transmission Master transmission is that the 78K0R/KF3 outputs a transfer clock and transmits data to another device. 3-Wire Serial I/O CSI00 CSI01 CSI10 CSI20 Target channel Channel 0 of SAU0 Channel 1 of SAU0...
Page 387 CHAPTER 12 SERIAL ARRAY UNIT (1) Register setting Figure 12-24. Example of Contents of Registers for Master Transmission of 3-Wire Serial I/O (CSI00, CSI01, CSI10, CSI20) (a) Serial output register m (SOm) … Sets only the bits of the target channel. CKOm2 CKOm1 CKOm0...
Page 388 CHAPTER 12 SERIAL ARRAY UNIT (2) Operation procedure Figure 12-25. Initial Setting Procedure for Master Transmission Starting initial setting Release the serial array unit from the Setting PER0 register reset status and start clock supply. Set the operation clock Setting SPSm register Set an operation mode, etc.
Page 389 CHAPTER 12 SERIAL ARRAY UNIT Figure 12-26. Procedure for Stopping Master Transmission Starting setting to stop Write 1 to the STmn bit of the target Setting STm register channel. Set the SOEm register and stop the Changing setting of SOEm register output of the target channel Stopping communication...
Page 390 CHAPTER 12 SERIAL ARRAY UNIT Figure 12-27. Procedure for Resuming Master Transmission Starting setting for resumption Disable data output and clock output of the target channel by setting a port Port manipulation (Essential) register and a port mode register. Change the setting if an incorrect division Changing setting of SPSm register (Selective) ratio of the operation clock is set.
Page 391 CHAPTER 12 SERIAL ARRAY UNIT (3) Processing flow (in single-transmission mode) Figure 12-28. Timing Chart of Master Transmission (in Single-Transmission Mode) (Type 1: DAPmn = 0, CKPmn = 0) SSmn STmn SEmn SDRmn Transmit data 1 Transmit data 2 Transmit data 3 SCKp pin SOp pin Transmit data 1...
Page 392 CHAPTER 12 SERIAL ARRAY UNIT Figure 12-29. Flowchart of Master Transmission (in Single-Transmission Mode) Starting CSI communication Setting SAU1EN and SAU0EN bits of PER0 register to 1 Setting operation clock by SPSm register SMRmn, SCRmn: Setting communication SDRmn[15:9]: Setting transfer rate Perform initial setting when SEmn = 0.
Page 393 CHAPTER 12 SERIAL ARRAY UNIT (4) Processing flow (in continuous transmission mode) Figure 12-30. Timing Chart of Master Transmission (in Continuous Transmission Mode) (Type 1: DAPmn = 0, CKPmn = 0) SSmn STmn SEmn SDRmn Transmit data 1 Transmit data 2 Transmit data 3 SCKp pin SOp pin...
Page 394 CHAPTER 12 SERIAL ARRAY UNIT Figure 12-31. Flowchart of Master Transmission (in Continuous Transmission Mode) Starting CSI communication Setting SAU1EN and SAU0EN bits of PER0 register to 1 Setting operation clock by SPSm register SMRmn, SCRmn: Setting communication Perform initial setting when SEmn = 0. SDRmn[15:9]: Setting transfer rate <1>...
Page 395: Master Reception
CHAPTER 12 SERIAL ARRAY UNIT 12.5.2 Master reception Master reception is that the 78K0R/KF3 outputs a transfer clock and receives data from other device. 3-Wire Serial I/O CSI00 CSI01 CSI10 CSI20 Target channel Channel 0 of SAU0 Channel 1 of SAU0...
Page 396 CHAPTER 12 SERIAL ARRAY UNIT (1) Register setting Figure 12-32. Example of Contents of Registers for Master Reception of 3-Wire Serial I/O (CSI00, CSI01, CSI10, CSI20) (a) Serial output register m (SOm) … Sets only the bits of the target channel. CKOm2 CKOm1 CKOm0...
Page 397 CHAPTER 12 SERIAL ARRAY UNIT (2) Operation procedure Figure 12-33. Initial Setting Procedure for Master Reception Starting initial setting Release the serial array unit from the Setting PER0 register reset status and start clock supply. Set the operation clock. Setting SPSm register Set an operation mode, etc.
Page 398 CHAPTER 12 SERIAL ARRAY UNIT Figure 12-35. Procedure for Resuming Master Reception Starting setting for resumption Disable clock output of the target channel by setting a port register and a Port manipulation (Essential) port mode register. Change the setting if an incorrect division Changing setting of SPSm register ratio of the operation clock is set.
Page 399 CHAPTER 12 SERIAL ARRAY UNIT (3) Processing flow (in single-reception mode) Figure 12-36. Timing Chart of Master Reception (in Single-Reception Mode) (Type 1: DAPmn = 0, CKPmn = 0) SSmn STmn SEmn Receive data 3 Receive data 1 Receive data 2 SDRmn Dummy data Dummy data for reception...
Page 400 CHAPTER 12 SERIAL ARRAY UNIT Figure 12-37. Flowchart of Master Reception (in Single-Reception Mode) Starting CSI communication Setting SAU1EN and SAU0EN bits of PER0 register to 1 Setting transfer rate by SPSm register SMRmn, SCRmn: Setting communication SDRmn[15:9]: Setting transfer rate Perform initial setting when SEmn = 0.
Page 401 CHAPTER 12 SERIAL ARRAY UNIT <R> (4) Processing flow (in continuous reception mode) Figure 12-38. Timing Chart of Master Reception (in Continuous Reception Mode) (Type 1: DAPmn = 0, CKPmn = 0) SSmn STmn SEmn Receive data 3 SDRmn Dummy data Dummy data Receive data 1 Dummy data...
Page 402 CHAPTER 12 SERIAL ARRAY UNIT Figure 12-39. Flowchart of Master Reception (in Continuous Reception Mode) <R> Starting CSI communication Setting SAU1EN and SAU0EN bits of PER0 register to 1 Setting transfer rate by SPSm register SMRmn, SCRmn: Setting communication Perform initial setting when SEmn = 0. SDRmn[15:9]: Setting transfer rate <1>...
Page 403: Master Transmission/Reception
CHAPTER 12 SERIAL ARRAY UNIT 12.5.3 Master transmission/reception Master transmission/reception is that the 78K0R/KF3 outputs a transfer clock and transmits/receives data to/from other device. 3-Wire Serial I/O CSI00 CSI01 CSI10 CSI20 Target channel Channel 0 of SAU0 Channel 1 of SAU0...
Page 404 CHAPTER 12 SERIAL ARRAY UNIT (1) Register setting Figure 12-40. Example of Contents of Registers for Master Transmission/Reception of 3-Wire Serial I/O (CSI00, CSI01, CSI10, CSI20) (a) Serial output register m (SOm) … Sets only the bits of the target channel. CKOm2 CKOm1 CKOm0...
Page 405 CHAPTER 12 SERIAL ARRAY UNIT (2) Operation procedure Figure 12-41. Initial Setting Procedure for Master Transmission/Reception Starting initial setting Release the serial array unit from the Setting PER0 register reset status and start clock supply. Set the operation clock. Setting SPSm register Set an operation mode, etc.
Page 406 CHAPTER 12 SERIAL ARRAY UNIT Figure 12-43. Procedure for Resuming Master Transmission/Reception Starting setting for resumption Disable data output and clock output of the target channel by setting a port Port manipulation (Essential) register and a port mode register. Change the setting if an incorrect division Changing setting of SPSm register (Selective) ratio of the operation clock is set.
Page 407 CHAPTER 12 SERIAL ARRAY UNIT (3) Processing flow (in single-transmission/reception mode) Figure 12-44. Timing Chart of Master Transmission/Reception (in Single-Transmission/Reception Mode) (Type 1: DAPmn = 0, CKPmn = 0) SSmn STmn SEmn Receive data 1 Receive data 3 Receive data 2 SDRmn Transmit data 1 Transmit data 2...
Page 408 CHAPTER 12 SERIAL ARRAY UNIT Figure 12-45. Flowchart of Master Transmission/Reception (in Single- Transmission/Reception Mode) Starting CSI communication Setting SAU1EN and SAU0EN bits of PER0 register to 1 Setting operation clock by SPSm register SMRmn, SCRmn: Setting communication SDRmn[15:9]: Setting transfer rate Perform initial setting when SEmn = 0.
Page 409 CHAPTER 12 SERIAL ARRAY UNIT (4) Processing flow (in continuous transmission/reception mode) Figure 12-46. Timing Chart of Master Transmission/Reception (in Continuous Transmission/Reception Mode) (Type 1: DAPmn = 0, CKPmn = 0) SSmn STmn SEmn Receive data 3 SDRmn Transmit data 2 Receive data 1 Receive data 2 Transmit data 1...
Page 410 CHAPTER 12 SERIAL ARRAY UNIT Figure 12-47. Flowchart of Master Transmission/Reception (in Continuous Transmission/Reception Mode) Starting CSI communication Setting SAU1EN and SAU0EN bits of PER0 register to 1 Setting operation clock by SPSm register SMRmn, SCRmn: Setting communication Perform initial setting when SEmn = 0. SDRmn[15:9]: Setting transfer rate <1>...
Page 411: Slave Transmission
CHAPTER 12 SERIAL ARRAY UNIT 12.5.4 Slave transmission Slave transmission is that the 78K0R/KF3 transmits data to another device in the state of a transfer clock being input from another device. 3-Wire Serial I/O CSI00 CSI01 CSI10 CSI20 Target channel...
Page 412 CHAPTER 12 SERIAL ARRAY UNIT (1) Register setting Figure 12-48. Example of Contents of Registers for Slave Transmission of 3-Wire Serial I/O (CSI00, CSI01, CSI10, CSI20) (a) Serial output register m (SOm) … Sets only the bits of the target channel. CKOm2 CKOm1 CKOm0...
Page 413 CHAPTER 12 SERIAL ARRAY UNIT (2) Operation procedure Figure 12-49. Initial Setting Procedure for Slave Transmission Starting initial setting Release the serial array unit from the Setting PER0 register reset status and start clock supply. Set the operation clock. Setting SPSm register Set an operation mode, etc.
Page 414 CHAPTER 12 SERIAL ARRAY UNIT Figure 12-50. Procedure for Stopping Slave Transmission Starting setting to stop Write 1 to the STmn bit of the target Setting STm register channel. Set the SOEm register and stop the Changing setting of SOEm register output of the target channel.
Page 415 CHAPTER 12 SERIAL ARRAY UNIT Figure 12-51. Procedure for Resuming Slave Transmission Starting setting for resumption Stop the target for communication or wait Manipulating target for communication (Essential) until the target completes its operation. Disable data output of the target channel by setting a port register and a port Port manipulation (Selective)
Page 416 CHAPTER 12 SERIAL ARRAY UNIT (3) Processing flow (in single-transmission mode) Figure 12-52. Timing Chart of Slave Transmission (in Single-Transmission Mode) (Type 1: DAPmn = 0, CKPmn = 0) SSmn STmn SEmn SDRmn Transmit data 2 Transmit data 1 Transmit data 3 SCKp pin SOp pin Transmit data 1...
Page 417 CHAPTER 12 SERIAL ARRAY UNIT Figure 12-53. Flowchart of Slave Transmission (in Single-Transmission Mode) Starting CSI communication Setting SAU1EN and SAU0EN bits of PER0 register to 1 Setting transfer rate by SPSm register SMRmn, SCRmn: Setting communication <R> SDRmn[15:9]: Setting 0000000B Perform initial setting when SEmn = 0.
Page 418 CHAPTER 12 SERIAL ARRAY UNIT (4) Processing flow (in continuous transmission mode) Figure 12-54. Timing Chart of Slave Transmission (in Continuous Transmission Mode) (Type 1: DAPmn = 0, CKPmn = 0) SSmn STmn SEmn SDRmn Transmit data 1 Transmit data 3 Transmit data 2 SCKp pin SOp pin...
Page 419 CHAPTER 12 SERIAL ARRAY UNIT Figure 12-55. Flowchart of Slave Transmission (in Continuous Transmission Mode) Starting CSI communication Setting SAU1EN and SAU0EN bits of PER0 register to 1 Setting transfer rate by SPSm register SMRmn, SCRmn: Setting communication Perform initial setting when SEmn = 0. <R>...
Page 420: Slave Reception
CHAPTER 12 SERIAL ARRAY UNIT 12.5.5 Slave reception Slave reception is that the 78K0R/KF3 receives data from another device in the state of a transfer clock being input from another device. 3-Wire Serial I/O CSI00 CSI01 CSI10 CSI20 Target channel...
Page 421 CHAPTER 12 SERIAL ARRAY UNIT (1) Register setting Figure 12-56. Example of Contents of Registers for Slave Reception of 3-Wire Serial I/O (CSI00, CSI01, CSI10, CSI20) (a) Serial output register m (SOm) …The register that not used in this mode. CKOm2 CKOm1 CKOm0...
Page 422 CHAPTER 12 SERIAL ARRAY UNIT (2) Operation procedure Figure 12-57. Initial Setting Procedure for Slave Reception Starting initial settings Release the serial array unit from the Setting PER0 register reset status and start clock supply. Set the operation clock. Setting SPSm register Set an operation mode, etc.
Page 423 CHAPTER 12 SERIAL ARRAY UNIT <R> Figure 12-59. Procedure for Resuming Slave Reception Starting setting for resumption Stop the target for communication or wait (Essential) Manipulating target for communication until the target completes its operation. Disable clock output of the target channel by setting a port register and a Port manipulation (Essential)
Page 424 CHAPTER 12 SERIAL ARRAY UNIT (3) Processing flow (in single-reception mode) Figure 12-60. Timing Chart of Slave Reception (in Single-Reception Mode) (Type 1: DAPmn = 0, CKPmn = 0) SSmn STmn SEmn Receive data 3 SDRmn Receive data 1 Receive data 2 Read Read Read...
Page 425 CHAPTER 12 SERIAL ARRAY UNIT Figure 12-61. Flowchart of Slave Reception (in Single-Reception Mode) Starting CSI communication Setting SAU1EN and SAU0EN bits of PER0 register to 1 Setting transfer rate by SPSm register SMRmn, SCRmn: Setting communication Perform initial setting when SEmn = 0. <R>...
Page 426: Slave Transmission/Reception
CHAPTER 12 SERIAL ARRAY UNIT 12.5.6 Slave transmission/reception Slave transmission/reception is that the 78K0R/KF3 transmits/receives data to/from another device in the state of a transfer clock being input from another device. 3-Wire Serial I/O CSI00 CSI01 CSI10 CSI20 Target channel...
Page 427 CHAPTER 12 SERIAL ARRAY UNIT (1) Register setting Figure 12-62. Example of Contents of Registers for Slave Transmission/Reception of 3-Wire Serial I/O (CSI00, CSI01, CSI10, CSI20) (a) Serial output register m (SOm) … Sets only the bits of the target channel. CKOm2 CKOm1 CKOm0...
Page 428 CHAPTER 12 SERIAL ARRAY UNIT (2) Operation procedure Figure 12-63. Initial Setting Procedure for Slave Transmission/Reception Starting initial setting Release the serial array unit from the Setting PER0 register reset status and start clock supply. Set the operation clock. Setting SPSm register Set an operation mode, etc.
Page 429 CHAPTER 12 SERIAL ARRAY UNIT Figure 12-64. Procedure for Stopping Slave Transmission/Reception Starting setting to stop Write 1 to the STmn bit of the target Setting STm register channel. Set the SOEm register and stop the Changing setting of SOEm register output of the target channel.
Page 430 CHAPTER 12 SERIAL ARRAY UNIT Figure 12-65. Procedure for Resuming Slave Transmission/Reception Starting setting for resumption Stop the target for communication or wait Manipulating target for communication (Essential) until the target completes its operation. Disable data output of the target channel by setting a port register and a port Port manipulation (Essential)
Page 431 CHAPTER 12 SERIAL ARRAY UNIT (3) Processing flow (in single-transmission/reception mode) Figure 12-66. Timing Chart of Slave Transmission/Reception (in Single-Transmission/Reception Mode) (Type 1: DAPmn = 0, CKPmn = 0) SSmn STmn SEmn Receive data 2 Receive data 1 Receive data 3 SDRmn Transmit data 1 Transmit data 2...
Page 432 CHAPTER 12 SERIAL ARRAY UNIT Figure 12-67. Flowchart of Slave Transmission/Reception (in Single- Transmission/Reception Mode) Starting CSI communication Setting SAU1EN and SAU0EN bits of PER0 register to 1 Setting transfer rate by SPSm register SMRmn, SCRmn: Setting communication <R> SDRmn[15:9]: Setting 0000000B Perform initial setting when SEmn = 0.
Page 433 CHAPTER 12 SERIAL ARRAY UNIT (4) Processing flow (in continuous transmission/reception mode) Figure 12-68. Timing Chart of Slave Transmission/Reception (in Continuous Transmission/Reception Mode) (Type 1: DAPmn = 0, CKPmn = 0) SSmn STmn SEmn Receive data 3 SDRmn Transmit data 2 Receive data 2 Transmit data 1 Receive data 1...
Page 434 CHAPTER 12 SERIAL ARRAY UNIT Figure 12-69. Flowchart of Slave Transmission/Reception (in Continuous Transmission/Reception Mode) Starting CSI communication Setting SAU1EN and SAU0EN bits of PER0 register to 1 Setting transfer rate by SPSm register SMRmn, SCRmn: Setting communication Perform initial setting when SEmn = 0. <R>...
Page 435: Calculating Transfer Clock Frequency
CHAPTER 12 SERIAL ARRAY UNIT 12.5.7 Calculating transfer clock frequency The transfer clock frequency for 3-wire serial I/O (CSI00, CSI01, CSI10, CSI20) communication can be calculated by the following expressions. (1) Master (Transfer clock frequency) = {Operation clock (MCK) frequency of target channel} ÷ (SDRmn[15:9] + 1) ÷ 2 [Hz] (2) Slave Note (Transfer clock frequency) = {Frequency of serial clock (SCK) supplied by master}...
Page 436 CHAPTER 12 SERIAL ARRAY UNIT Table 12-2. Selection of operation clock Note1 SMRmn SPSm Register Operation Clock (MCK) Register CKSmn = 20 MHz 20 MHz 10 MHz 5 MHz 2.5 MHz 1.25 MHz 625 kHz 313 kHz 156 kHz 78.1 kHz 39.1 kHz 19.5 kHz 9.77 kHz...
Page 437: Procedure For Processing Errors That Occurred During 3-Wire Serial I/O
CHAPTER 12 SERIAL ARRAY UNIT 12.5.8 Procedure for processing errors that occurred during 3-wire serial I/O (CSI00, CSI01, CSI10, CSI20) communication The procedure for processing errors that occurred during 3-wire serial I/O (CSI00, CSI01, CSI10, CSI20) communication is described in Figure 12-70. Figure 12-70.
Page 438: Operation Of Uart (Uart0, Uart1, Uart2, Uart3) Communication
CHAPTER 12 SERIAL ARRAY UNIT 12.6 Operation of UART (UART0, UART1, UART2, UART3) Communication This is a start-stop synchronization function using two lines: serial data transmission (TxD) and serial data reception (RxD) lines. It transmits or receives data in asynchronization with the party of communication (by using an internal baud rate).
Page 439: Uart Transmission
CHAPTER 12 SERIAL ARRAY UNIT 12.6.1 UART transmission UART transmission is an operation to transmit data from the 78K0R/KF3 to another device asynchronously (start- stop synchronization). Of two channels used for UART, the even channel is used for UART transmission.
Page 440 CHAPTER 12 SERIAL ARRAY UNIT (1) Register setting Figure 12-71. Example of Contents of Registers for UART Transmission of UART (UART0, UART1, UART2, UART3) (1/2) (a) Serial output register m (SOm) … Sets only the bits of the target channel to 1. CKOm2 CKOm1 CKOm0...
Page 441 CHAPTER 12 SERIAL ARRAY UNIT Figure 12-71. Example of Contents of Registers for UART Transmission of UART (UART0, UART1, UART2, UART3) (2/2) (f) Serial communication operation setting register mn (SCRmn) SCRmn TXEmn RXEmn DAPmn CKPmn EOCmn PTCmn1 PTCmn0 DIRmn SLCmn1 SLCmn0 DLSmn2 DLSmn1...
Page 442 CHAPTER 12 SERIAL ARRAY UNIT (2) Operation procedure Figure 12-72. Initial Setting Procedure for UART Transmission Starting initial setting Release the serial array unit from the Setting PER0 register reset status and start clock supply. Set the operation clock. Setting SPSm register Set an operation mode, etc.
Page 443 CHAPTER 12 SERIAL ARRAY UNIT Figure 12-73. Procedure for Stopping UART Transmission Starting setting to stop Write 1 to the STmn bit of the target Setting STm register channel. Set the SOEmn bit to 0 and stop the Changing setting of SOEm register output.
Page 444 CHAPTER 12 SERIAL ARRAY UNIT Figure 12-74. Procedure for Resuming UART Transmission Starting setting for resumption Disable data output of the target channel by setting a port register and a port mode Port manipulation (Essential) register. Change the setting if an incorrect division Changing setting of SPSm register (Selective) ratio of the operation clock is set.
Page 445 CHAPTER 12 SERIAL ARRAY UNIT (3) Processing flow (in single-transmission mode) Figure 12-75. Timing Chart of UART Transmission (in Single-Transmission Mode) SSmn STmn SEmn SDRmn Transmit data 1 Transmit data 2 Transmit data 3 TxDq pin Transmit data 1 Transmit data 2 Transmit data 3 P SP P SP...
Page 446 CHAPTER 12 SERIAL ARRAY UNIT Figure 12-76. Flowchart of UART Transmission (in Single-Transmission Mode) Starting UART communication Setting SAU1EN and SAU0EN bits of PER0 register to 1 Setting operation clock by SPSm register SMRmn, SCRmn: Setting communication SDRmn[15:9]: Setting transfer rate Perform initial setting when SEmn = 0.
Page 447 CHAPTER 12 SERIAL ARRAY UNIT (4) Processing flow (in continuous transmission mode) Figure 12-77. Timing Chart of UART Transmission (in Continuous Transmission Mode) SSmn STmn SEmn SDRmn Transmit data 3 Transmit data 1 Transmit data 2 TxDq pin Transmit data 3 Transmit data 1 Transmit data 2 P SP...
Page 448 CHAPTER 12 SERIAL ARRAY UNIT Figure 12-78. Flowchart of UART Transmission (in Continuous Transmission Mode) Starting UART communication Setting SAU1EN and SAU0EN bits of PER0 register to 1 Setting operation clock by SPSm register SMRmn, SCRmn: Setting communication Perform initial setting when SEmn = 0. SDRmn[15:9]: Setting transfer rate SOLmn:...
Page 449: Uart Reception
CHAPTER 12 SERIAL ARRAY UNIT 12.6.2 UART reception UART reception is an operation wherein the 78K0R/KF3 asynchronously receives data from another device (start- stop synchronization). For UART reception, the odd-number channel of the two channels used for UART is used. The SMR register of both the odd- and even-numbered channels must be set.
Page 450 CHAPTER 12 SERIAL ARRAY UNIT (1) Register setting Figure 12-79. Example of Contents of Registers for UART Reception of UART (UART0, UART1, UART2, UART3) (1/2) (a) Serial output register m (SOm) …The register that not used in this mode. CKOm2 CKOm1 CKOm0 SOm2...
Page 451 CHAPTER 12 SERIAL ARRAY UNIT Figure 12-79. Example of Contents of Registers for UART Reception of UART (UART0, UART1, UART2, UART3) (2/2) (g) Serial data register mn (SDRmn) (lower 8 bits: RXDq) SDRmn Baud rate setting Receive data register RXDq Caution For the UART reception, be sure to set SMRmr of channel r that is to be paired with channel m: Unit number (m = 0, 1), n: Channel number (n = 1, 3), r: Channel number (r = n −...
Page 452 CHAPTER 12 SERIAL ARRAY UNIT (2) Operation procedure Figure 12-80. Initial Setting Procedure for UART Reception Starting initial setting Release the serial array unit from the Setting PER0 register reset status and start clock supply. Set the operation clock. Setting SPSm register Set an operation mode, etc.
Page 453 CHAPTER 12 SERIAL ARRAY UNIT Figure 12-82. Procedure for Resuming UART Reception Starting setting for resumption Stop the target for communication or wait (Essential) Manipulating target for communication until the target completes its operation. Change the setting if an incorrect division (Selective) Changing setting of SPSm register ratio of the operation clock is set.
Page 454 CHAPTER 12 SERIAL ARRAY UNIT (3) Processing flow Figure 12-83. Timing Chart of UART Reception SSmn STmn SEmn Receive data 3 SDRmn Receive data 1 Receive data 2 RxDq pin Receive data 1 Receive data 2 Receive data 3 Shift Shift operation Shift operation Shift operation...
Page 455 CHAPTER 12 SERIAL ARRAY UNIT Figure 12-84. Flowchart of UART Reception Starting UART communication Setting SAU1EN and SAU0EN bits of PER0 register to 1 Setting transfer rate by SPSm register SMRmn, SMRmr, SCRmn: Setting communication Perform initial setting when <R> SDRmn[15:9]: Setting transfer rate SEmn = 0.
Page 456: Lin Transmission
CHAPTER 12 SERIAL ARRAY UNIT 12.6.3 LIN transmission Of UART transmission, UART3 supports LIN communication. For LIN transmission, channel 2 of unit 1 (SAU1) is used. UART UART0 UART1 UART2 UART3 Support of LIN communication Not supported Not supported Not supported Supported −...
Page 457 CHAPTER 12 SERIAL ARRAY UNIT Figure 12-85. Transmission Operation of LIN Wakeup signal Sync break Sync field Identification Data field Data field Checksum frame field field field LIN Bus 13-bit SBF Data Data Data Data Note 1 Note 2 8 bits transmission transmission transmission...
Page 458 CHAPTER 12 SERIAL ARRAY UNIT Figure 12-86. Flowchart for LIN Transmission Starting LIN communication Setting baud rate Writing 1 to SS12 Setting transfer data 00H Transmitting wakeup signal frame Wakeup signal frame Transfer end interrupt generated? Setting transfer data 00H Transmitting sync break field Sync break field...
Page 459: Lin Reception
CHAPTER 12 SERIAL ARRAY UNIT 12.6.4 LIN reception Of UART reception, UART3 supports LIN communication. For LIN reception, channel 3 of unit 1 (SAU1) is used. UART UART0 UART1 UART2 UART3 Support of LIN communication Not supported Not supported Not supported Supported −...
Page 460 CHAPTER 12 SERIAL ARRAY UNIT Figure 12-87. Reception Operation of LIN Wakeup signal Sync break Sync field Identification Data filed Data filed Checksum frame field field field LIN Bus 13-bit SBF Data Data Data reception reception reception reception reception reception <5>...
Page 461 CHAPTER 12 SERIAL ARRAY UNIT Figure 12-88 shows the configuration of a port that manipulates reception of LIN. The wakeup signal transmitted from the master of LIN is received by detecting an edge of an external interrupt (INTP0). The length of the sync field transmitted from the master can be measured by using the external event capture operation of the timer array unit (TAU) to calculate a baud-rate error.
Page 462 CHAPTER 12 SERIAL ARRAY UNIT The peripheral functions used for the LIN communication operation are as follows. <Peripheral functions used> • External interrupt (INTP0); Wakeup signal detection Usage: To detect an edge of the wakeup signal and the start of communication •...
Page 463 CHAPTER 12 SERIAL ARRAY UNIT Figure 12-89. Flowchart of LIN Reception Starting LIN communication Setting TAU in capture mode (to measure low-level width) Detecting low-level width Wakeup signal frame Wakeup detected? Detecting low-level width Sync break field SBF detected? INTP0, Stopping operation Setting TAU in capture mode (to measure...
Page 464: Calculating Baud Rate
CHAPTER 12 SERIAL ARRAY UNIT 12.6.5 Calculating baud rate (1) Baud rate calculation expression The baud rate for UART (UART0, UART1, UART2, UART3) communication can be calculated by the following expressions. (Baud rate) = {Operation clock (MCK) frequency of target channel} ÷ (SDRmn[15:9] + 1) ÷ 2 [bps] Caution Setting SDRmn [15:9] = (0000000B, 0000001B) is prohibited.
Page 465 CHAPTER 12 SERIAL ARRAY UNIT Table 12-3. Selection of operation clock Note1 SMRmn SPSm Register Operation Clock (MCK) Register CKSmn = 20 MHz 20 MHz 10 MHz 5 MHz 2.5 MHz 1.25 MHz 625 kHz 313 kHz 156 kHz 78.1 kHz 39.1 kHz 19.5 kHz 9.77 kHz...
Page 466 CHAPTER 12 SERIAL ARRAY UNIT (2) Baud rate error during transmission The baud rate error of UART (UART0, UART1, UART2, UART3) communication during transmission can be calculated by the following expression. Make sure that the baud rate at the transmission side is within the permissible baud rate range at the reception side.
Page 467 CHAPTER 12 SERIAL ARRAY UNIT (3) Permissible baud rate range for reception The permissible baud rate range for reception during UART (UART0, UART1, UART2, UART3) communication can be calculated by the following expression. Make sure that the baud rate at the transmission side is within the permissible baud rate range at the reception side.
Page 468: Procedure For Processing Errors That Occurred During Uart (Uart0, Uart1, Uart2, Uart3) Communication
CHAPTER 12 SERIAL ARRAY UNIT 12.6.6 Procedure for processing errors that occurred during UART (UART0, UART1, UART2, UART3) communication The procedure for processing errors that occurred during UART (UART0, UART1, UART2, UART3) communication is described in Figures 12-91 and 12-92. Figure 12-91.
Page 469: Operation Of Simplified I 2 C (Iic10, Iic20) Communication
CHAPTER 12 SERIAL ARRAY UNIT 12.7 Operation of Simplified I C (IIC10, IIC20) Communication This is a clocked communication function to communicate with two or more devices by using two lines: serial clock (SCL) and serial data (SDA). This communication function is designed to execute single communication with devices such as EEPROM, flash memory, and A/D converter, and therefore, can be used only by the master and does not have a wait detection function.
Page 470: Address Field Transmission
CHAPTER 12 SERIAL ARRAY UNIT 12.7.1 Address field transmission Address field transmission is a transmission operation that first executes in I C communication to identify the target for transfer (slave). After a start condition is generated, an address (7 bits) and a transfer direction (1 bit) are transmitted in one frame.
Page 471 CHAPTER 12 SERIAL ARRAY UNIT (1) Register setting Figure 12-93. Example of Contents of Registers for Address Field Transmission of Simplified I C (IIC10, IIC20) (a) Serial output register m (SOm) … Sets only the bits of the target channel. CKOm2 CKOm1 CKOm0...
Page 472 CHAPTER 12 SERIAL ARRAY UNIT (2) Operation procedure Figure 12-94. Initial Setting Procedure for Address Field Transmission Starting initial setting Release the serial array unit from the Setting PER0 register reset status and start clock supply. Set the operation clock Setting SPSm register Set an operation mode, etc.
Page 473 CHAPTER 12 SERIAL ARRAY UNIT (3) Processing flow Figure 12-95. Timing Chart of Address Field Transmission SSmn SEmn SOEmn SDRmn Address field transmission SCLr output CKOmn bit manipulation SDAr output SOmn bit manipulation Address SDAr input Shift Shift operation register mn INTIICr TSFmn Remark...
Page 474 CHAPTER 12 SERIAL ARRAY UNIT Figure 12-96. Flowchart of Address Field Transmission Starting IIC communication SMRmn, SCRmn: Setting communication SPSm, SDRmn[15:9]: Setting transfer rate Writing 0 to SOmn bit Perform initial setting when SEmn = 0. Writing 0 to CKOmn bit Writing 1 to SOEmn bit Writing 1 to SSmn bit Writing address and R/W...
Page 475: Data Transmission
CHAPTER 12 SERIAL ARRAY UNIT 12.7.2 Data transmission Data transmission is an operation to transmit data to the target for transfer (slave) after transmission of an address field. After all data are transmitted to the slave, a stop condition is generated and the bus is released. Simplified I IIC10 IIC20...
Page 476 CHAPTER 12 SERIAL ARRAY UNIT (1) Register setting Figure 12-97. Example of Contents of Registers for Data Transmission of Simplified I C (IIC10, IIC20) (a) Serial output register m (SOm) … Do not manipulate this register during data transmission/reception. CKOm2 CKOm1 CKOm0 SOm2...
Page 477 CHAPTER 12 SERIAL ARRAY UNIT (2) Processing flow Figure 12-98. Timing Chart of Data Transmission SSmn “L” SEmn “H” SOEmn “H” SDRmn Transmit data 1 SCLr output SDAr output SDAr input Shift Shift operation register mn INTIICr TSFmn Remark m: Unit number (m = 0, 1), n: Channel number (n = 0, 2), r: IIC number (r = 10, 20) Figure 12-99.
Page 478: Data Reception
CHAPTER 12 SERIAL ARRAY UNIT 12.7.3 Data reception Data reception is an operation to receive data to the target for transfer (slave) after transmission of an address field. After all data are received to the slave, a stop condition is generated and the bus is released. Simplified I IIC10 IIC20...
Page 479 CHAPTER 12 SERIAL ARRAY UNIT (1) Register setting Figure 12-100. Example of Contents of Registers for Data Reception of Simplified I C (IIC10, IIC20) (a) Serial output register m (SOm) … Do not manipulate this register during data transmission/reception. CKOm2 CKOm1 CKOm0 SOm2...
Page 480 CHAPTER 12 SERIAL ARRAY UNIT (2) Processing flow Figure 12-101. Timing Chart of Data Reception (a) When starting data reception SSmn STmn SEmn SOEmn “H” TXEmn, TXEmn = 1 / RXEmn = 0 TXEmn = 0 / RXEmn = 1 RXEmn SDRmn Dummy data (FFH)
Page 481 CHAPTER 12 SERIAL ARRAY UNIT Figure 12-102. Flowchart of Data Reception Address field transmission completed Writing 1 to STmn bit Writing 0 to TXEmn bit, and 1 to RXEmn bit Writing 1 to SSmn bit Starting data reception Last byte received? Writing 0 to SOEmn bit (Stopping output by serial communication operation)
Page 482: Stop Condition Generation
CHAPTER 12 SERIAL ARRAY UNIT 12.7.4 Stop condition generation After all data are transmitted to or received from the target slave, a stop condition is generated and the bus is released. (1) Processing flow Figure 12-103. Timing Chart of Stop Condition Generation STmn SEmn SOEmn...
Page 483: Calculating Transfer Rate
CHAPTER 12 SERIAL ARRAY UNIT 12.7.5 Calculating transfer rate The transfer rate for simplified I C (IIC10, IIC20) communication can be calculated by the following expressions. (Transfer rate) = {Operation clock (MCK) frequency of target channel} ÷ (SDRmn[15:9] + 1) ÷ 2 <R>...
Page 484 CHAPTER 12 SERIAL ARRAY UNIT Table 12-4. Selection of operation clock Note1 SMRmn SPSm Register Operation Clock (MCK) Register CKSmn = 20 MHz 20 MHz 10 MHz 5 MHz 2.5 MHz 1.25 MHz 625 kHz 313 kHz 156 kHz 78.1 kHz 39.1 kHz 19.5 kHz 9.77 kHz...
Page 485 CHAPTER 12 SERIAL ARRAY UNIT Here is an example of setting an IIC transfer rate where MCK = f = 20 MHz. IIC Transfer Mode = 20 MHz (Desired Transfer Rate) Operation Clock (MCK) SDRmn[15:9] Calculated Error from Desired Transfer Transfer Rate Rate 100 kHz...
Page 486: Procedure For Processing Errors That Occurred During Simplified I 2 C (Iic10, Iic20) Communication
CHAPTER 12 SERIAL ARRAY UNIT 12.7.6 Procedure for processing errors that occurred during simplified I C (IIC10, IIC20) communication The procedure for processing errors that occurred during simplified I C (IIC10, IIC20) communication is described in Figures 12-105 and 12-106. Figure 12-105.
Page 487: Relationship Between Register Settings And Pins
CHAPTER 12 SERIAL ARRAY UNIT 12.8 Relationship Between Register Settings and Pins Tables 12-5 to 12-12 show the relationship between register settings and pins for each channel of serial array units 0 and 1. Table 12-5. Relationship between register settings and pins (Channel 0 of unit 0: CSI00, UART0 transmission) P10 PM Operation mode Pin Function...
Page 488 CHAPTER 12 SERIAL ARRAY UNIT Table 12-6. Relationship between register settings and pins (Channel 1 of unit 0: CSI01, UART0 reception) SO01 CKO P43 PM44 P44 PM P45 PM Operation Pin Function Note2 mode SCK01/ SI01/P44 SO01/ SI00/ Note1 Note2 RxD0/ Note2 ×...
Page 489 CHAPTER 12 SERIAL ARRAY UNIT Table 12-7. Relationship between register settings and pins (Channel 2 of unit 0: CSI10, UART1 transmission, IIC10) P04 PM03 PM02 P02 Operation mode Pin Function Note2 Note2 SCK10/ SI10/SDA10/ SO10/ Note1 SCL10/P04 RxD1/P03 TxD1/P02 Note2 ×...
Page 490 CHAPTER 12 SERIAL ARRAY UNIT Table 12-8. Relationship between register settings and pins (Channel 3 of unit 0: UART1 reception) Note1 Note2 Note2 SE03 PM03 MD032 MD031 TXE03 RXE03 Operation Pin Function mode SI10/SDA10/RxD1/P03 Note2 Note3 Note3 Note2 × × SI10/SDA10/P03 Operation stop mode...
Page 491 CHAPTER 12 SERIAL ARRAY UNIT Table 12-9. Relationship between register settings and pins (Channel 0 of unit 1: CSI20, UART2 transmission, IIC20) P142 PM P143 P144 Operation mode Pin Function Note2 SCK20/ SI20/SDA20/ SO20/ Note1 Note2 SCL20/P142 RxD2/P143 TxD2/P144 Note2 ×...
Page 492 CHAPTER 12 SERIAL ARRAY UNIT Table 12-10. Relationship between register settings and pins (Channel 1 of unit 1: UART2 reception) Note1 Note2 Note2 SE11 PM143 P143 MD112 MD111 TXE11 RXE11 Operation Pin Function mode SI20/SDA20/RxD2/P143 Note2 Note3 Note3 × × Operation SI20/SDA20/P143 stop mode...
Page 493 CHAPTER 12 SERIAL ARRAY UNIT Table 12-11. Relationship between register settings and pins (Channel 2 of unit 1: UART3 transmission) SE12 MD122 MD121 SOE12 SO12 TXE12 RXE12 PM13 Operation Pin Function Note1 mode TxD3/P13 × × Operation Note2 Note2 stop mode Note3 UART3 TxD3...
Page 494: Chapter 13 Serial Interface Iic0
CHAPTER 13 SERIAL INTERFACE IIC0 13.1 Functions of Serial Interface IIC0 Serial interface IIC0 has the following two modes. (1) Operation stop mode This mode is used when serial transfers are not performed. It can therefore be used to reduce power consumption.
Page 495 CHAPTER 13 SERIAL INTERFACE IIC0 Figure 13-1. Block Diagram of Serial Interface IIC0 Internal bus IIC status register 0 (IICS0) MSTS0 ALD0 EXC0 COI0 TRC0 ACKD0 STD0 SPD0 IIC control register 0 (IICC0) IICE0 LREL0 WREL0 SPIE0 WTIM0 ACKE0 STT0 SPT0 Slave address Start Clear...
Page 496 CHAPTER 13 SERIAL INTERFACE IIC0 Figure 13-2 shows a serial bus configuration example. Figure 13-2. Serial Bus Configuration Example Using I C Bus Serial data bus Master CPU2 Master CPU1 SDA0 SDA0 Slave CPU1 Slave CPU2 Serial clock SCL0 SCL0 Address 0 Address 1 SDA0...
Page 497: Configuration Of Serial Interface Iic0
CHAPTER 13 SERIAL INTERFACE IIC0 13.2 Configuration of Serial Interface IIC0 Serial interface IIC0 includes the following hardware. Table 13-1. Configuration of Serial Interface IIC0 Item Configuration Registers IIC shift register 0 (IIC0) Slave address register 0 (SVA0) Control registers Peripheral enable register 0 (PER0) IIC control register 0 (IICC0) IIC status register 0 (IICS0)
Page 498 CHAPTER 13 SERIAL INTERFACE IIC0 (3) SO latch The SO latch is used to retain the SDA0 pin’s output level. (4) Wakeup controller This circuit generates an interrupt request (INTIIC0) when the address received by this register matches the address value set to slave address register 0 (SVA0) or when an extension code is received. (5) Prescaler This selects the sampling clock to be used.
Page 499 CHAPTER 13 SERIAL INTERFACE IIC0 (14) Bus status detector This circuit detects whether or not the bus is released by detecting start conditions and stop conditions. However, as the bus status cannot be detected immediately following operation, the initial status is set by the STCEN bit.
Page 500: Registers To Controlling Serial Interface Iic0
CHAPTER 13 SERIAL INTERFACE IIC0 13.3 Registers to Controlling Serial Interface IIC0 Serial interface IIC0 is controlled by the following eight registers. • Peripheral enable register 0 (PER0) • IIC control register 0 (IICC0) • IIC flag register 0 (IICF0) •...
Page 501 CHAPTER 13 SERIAL INTERFACE IIC0 Figure 13-6. Format of IIC Control Register 0 (IICC0) (1/4) Address: FFF52H After reset: 00H Symbol <7> <6> <5> <4> <3> <2> <1> <0> IICC0 IICE0 LREL0 WREL0 SPIE0 WTIM0 ACKE0 STT0 SPT0 IICE0 C operation enable Note 1 Stop operation.
Page 502 CHAPTER 13 SERIAL INTERFACE IIC0 Figure 13-6. Format of IIC Control Register 0 (IICC0) (2/4) Note 1 SPIE0 Enable/disable generation of interrupt request when stop condition is detected Disable Enable Condition for clearing (SPIE0 = 0) Condition for setting (SPIE0 = 1) •...
Page 503 CHAPTER 13 SERIAL INTERFACE IIC0 Figure 13-6. Format of IIC Control Register 0 (IICC0) (3/4) Note STT0 Start condition trigger Do not generate a start condition. <R> When bus is released (in standby state, when IICBSY = 0): Generate a start condition (for starting as master). When the SCL0 line is high level, the SDA0 line is changed from high level to low level and then the start condition is generated.
Page 504 CHAPTER 13 SERIAL INTERFACE IIC0 Figure 13-6. Format of IIC Control Register 0 (IICC0) (4/4) SPT0 Stop condition trigger Stop condition is not generated. Stop condition is generated (termination of master device’s transfer). After the SDA0 line goes to low level, either set the SCL0 line to high level or wait until it goes to high level.
Page 505 CHAPTER 13 SERIAL INTERFACE IIC0 (3) IIC status register 0 (IICS0) This register indicates the status of I IICS0 is read by a 1-bit or 8-bit memory manipulation instruction only when STT0 = 1 and during the wait period. Reset signal generation clears this register to 00H. Figure 13-7.
Page 506 CHAPTER 13 SERIAL INTERFACE IIC0 Figure 13-7. Format of IIC Status Register 0 (IICS0) (2/3) COI0 Detection of matching addresses Addresses do not match. Addresses match. Condition for clearing (COI0 = 0) Condition for setting (COI0 = 1) • When a start condition is detected •...
Page 507 CHAPTER 13 SERIAL INTERFACE IIC0 Figure 13-7. Format of IIC Status Register 0 (IICS0) (3/3) ACKD0 Detection of acknowledge (ACK) Acknowledge was not detected. Acknowledge was detected. Condition for clearing (ACKD0 = 0) Condition for setting (ACKD0 = 1) • When a stop condition is detected •...
Page 508 CHAPTER 13 SERIAL INTERFACE IIC0 Figure 13-8. Format of IIC Flag Register 0 (IICF0) Note Address: FFF51H After reset: 00H <7> <6> <1> <0> Symbol IICF0 STCF IICBSY STCEN IICRSV STCF STT0 clear flag Generate start condition Start condition generation unsuccessful: clear STT0 flag Condition for clearing (STCF = 0) Condition for setting (STCF = 1) •...
Page 509 CHAPTER 13 SERIAL INTERFACE IIC0 (5) IIC clock select register 0 (IICCL0) This register is used to set the transfer clock for the I C bus. IICCL0 can be set by a 1-bit or 8-bit memory manipulation instruction. However, the CLD0 and DAD0 bits are read-only.
Page 510 CHAPTER 13 SERIAL INTERFACE IIC0 (6) IIC function expansion register 0 (IICX0) This register sets the function expansion of I IICX0 can be set by a 1-bit or 8-bit memory manipulation instruction. The CLX0 bit is set in combination with bits 3, 1, and 0 (SMC0, CL01, and CL00) of IIC clock select register 0 (IICCL0) (see 13.5.4 Transfer clock setting method).
Page 511 CHAPTER 13 SERIAL INTERFACE IIC0 (7) Port mode register 6 (PM6) This register sets the input/output of port 6 in 1-bit units. When using the P60/SCL0 pin as clock I/O and the P61/SDA0 pin as serial data I/O, clear PM60 and PM61, and the output latches of P60 and P61 to 0.
Page 512: I C Bus Mode Functions
CHAPTER 13 SERIAL INTERFACE IIC0 13.4 I C Bus Mode Functions 13.4.1 Pin configuration The serial clock pin (SCL0) and serial data bus pin (SDA0) are configured as follows. (1) SCL0..This pin is used for serial clock input and output. This pin is an N-ch open-drain output for both master and slave devices.
Page 513: I C Bus Definitions And Control Methods
CHAPTER 13 SERIAL INTERFACE IIC0 13.5 I C Bus Definitions and Control Methods The following section describes the I C bus’s serial data communication format and the signals used by the I C bus. Figure 13-13 shows the transfer timing for the “start condition”, “address”, “data”, and “stop condition” output via the C bus’s serial data bus.
Page 514: Addresses
CHAPTER 13 SERIAL INTERFACE IIC0 13.5.2 Addresses The address is defined by the 7 bits of data that follow the start condition. An address is a 7-bit data segment that is output in order to select one of the slave devices that are connected to the master device via the bus lines.
Page 515: Transfer Clock Setting Method
CHAPTER 13 SERIAL INTERFACE IIC0 13.5.4 Transfer clock setting method (1) Selection clock setting method on the master side The I C transfer clock frequency (f ) is calculated using the following expression. = 1/(m × T + t m = 24, 44, 48, 88, 96, 172, 344 (see Table 13-3 Selection Clock Setting) T: 1/f : SCL0 rise time : SCL0 fall time...
Page 516: Acknowledge (Ack)
CHAPTER 13 SERIAL INTERFACE IIC0 Table 13-3. Selection Clock Setting IICX0 IICCL0 Transfer Clock (f Settable Selection Clock Operation Mode ) Range Bit 0 Bit 3 Bit 1 Bit 0 CLX0 SMC0 CL01 CL00 4.00 MHz to 8.4 MHz Normal mode (SMC0 bit = 0) /172 8.38 MHz to 16.76 MHz /344...
Page 517 CHAPTER 13 SERIAL INTERFACE IIC0 Figure 13-17. ACK SCL0 SDA0 When the local address is received, ACK is automatically generated, regardless of the value of ACKE0. When an address other than that of the local address is received, ACK is not generated (NACK). When an extension code is received, ACK is generated if ACKE0 is set to 1 in advance.
Page 518: Stop Condition
CHAPTER 13 SERIAL INTERFACE IIC0 13.5.6 Stop condition When the SCL0 pin is at high level, changing the SDA0 pin from low level to high level generates a stop condition. A stop condition is a signal that the master device generates to the slave device when serial transfer has been completed.
Page 519: Wait
CHAPTER 13 SERIAL INTERFACE IIC0 13.5.7 Wait The wait is used to notify the communication partner that a device (master or slave) is preparing to transmit or receive data (i.e., is in a wait state). Setting the SCL0 pin to low level notifies the communication partner of the wait state. When wait state has been canceled for both the master and slave devices, the next data transfer can begin.
Page 520 CHAPTER 13 SERIAL INTERFACE IIC0 Figure 13-19. Wait (2/2) (2) When master and slave devices both have a nine-clock wait (master transmits, slave receives, and ACKE0 = 1) Master Master and slave both wait after output of ninth clock IIC0 data write (cancel wait) IIC0 SCL0 Slave...
Page 521: Canceling Wait
CHAPTER 13 SERIAL INTERFACE IIC0 13.5.8 Canceling wait The I C usually cancels a wait state by the following processing. • Writing data to IIC shift register 0 (IIC0) • Setting bit 5 (WREL0) of IIC control register 0 (IICC0) (canceling wait) •...
Page 522: Interrupt Request (Intiic0) Generation Timing And Wait Control
CHAPTER 13 SERIAL INTERFACE IIC0 13.5.9 Interrupt request (INTIIC0) generation timing and wait control The setting of bit 3 (WTIM0) of IIC control register 0 (IICC0) determines the timing by which INTIIC0 is generated and the corresponding wait control, as shown in Table 13-4. Table 13-4.
Page 523: Address Match Detection Method
CHAPTER 13 SERIAL INTERFACE IIC0 13.5.10 Address match detection method In I C bus mode, the master device can select a particular slave device by transmitting the corresponding slave address. Address match can be detected automatically by hardware. An INTIIC0 occurs when the address set to the slave address register 0 (SVA0) matches the slave address sent by the master device, or when an extension code has been received.
Page 524: Arbitration
CHAPTER 13 SERIAL INTERFACE IIC0 13.5.13 Arbitration When several master devices simultaneously generate a start condition (when STT0 is set to 1 before STD0 is set to 1), communication among the master devices is performed as the number of clocks are adjusted until the data differs.
Page 525: Wakeup Function
CHAPTER 13 SERIAL INTERFACE IIC0 Table 13-6. Status During Arbitration and Interrupt Request Generation Timing Status During Arbitration Interrupt Request Generation Timing Note 1 During address transmission At falling edge of eighth or ninth clock following byte transfer Read/write data after address transmission During extension code transmission Read/write data after extension code transmission During data transmission...
Page 526: Communication Reservation
CHAPTER 13 SERIAL INTERFACE IIC0 13.5.15 Communication reservation (1) When communication reservation function is enabled (bit 0 (IICRSV) of IIC flag register 0 (IICF0) = 0) To start master device communications when not currently using a bus, a communication reservation can be made to enable transmission of a start condition when the bus is released.
Page 527 CHAPTER 13 SERIAL INTERFACE IIC0 Figure 13-21. Communication Reservation Timing Write to Program processing STT0 = 1 IIC0 Communi- Set SPD0 cation Hardware processing STD0 reservation INTIIC0 SCL0 SDA0 Generate by master device with bus mastership Remark IIC0: IIC shift register 0 STT0: Bit 1 of IIC control register 0 (IICC0) STD0: Bit 1 of IIC status register 0 (IICS0)
Page 528 CHAPTER 13 SERIAL INTERFACE IIC0 Figure 13-23. Communication Reservation Protocol SET1 STT0 Sets STT0 flag (communication reservation) Defines that communication reservation is in effect Define communication (defines and sets user flag to any part of RAM) reservation Secures wait period set by software (see Table 13-7). Wait Note (Communication reservation)
Page 529 CHAPTER 13 SERIAL INTERFACE IIC0 (2) When communication reservation function is disabled (bit 0 (IICRSV) of IIC flag register 0 (IICF0) = 1) When bit 1 (STT0) of IIC control register 0 (IICC0) is set to 1 when the bus is not used in a communication during bus communication, this request is rejected and a start condition is not generated.
Page 530: Cautions
CHAPTER 13 SERIAL INTERFACE IIC0 13.5.16 Cautions (1) When STCEN (bit 1 of IIC flag register 0 (IICF0)) = 0 Immediately after I C operation is enabled (IICE0 = 1), the bus communication status (IICBSY (bit 6 of IICF0) = 1) is recognized regardless of the actual bus status.
Page 531: Communication Operations
This flowchart is broadly divided into the initial settings, communication waiting, and communication processing. The processing when the 78K0R/KF3 looses in arbitration and is specified as the slave is omitted here, and only the processing as the master is shown.
Page 532 CHAPTER 13 SERIAL INTERFACE IIC0 (1) Master operation in single-master system Figure 13-24. Master Operation in Single-Master System START Note Initializing I C bus Sets the port used alternatively as the pin to be used. Setting port First, set the port to input mode and the output latch to 0 (see 13.3 (7) Port mode register 6 (PM6)). IICX0 ←...
Page 533 CHAPTER 13 SERIAL INTERFACE IIC0 (2) Master operation in multi-master system Figure 13-25. Master Operation in Multi-Master System (1/3) START Sets the port used alternatively as the pin to be used. Setting port First, set the port to input mode and the output latch to 0 (see 13.3 (7) Port mode register 6 (PM6)). IICX0 ←...
Page 534 CHAPTER 13 SERIAL INTERFACE IIC0 Figure 13-25. Master Operation in Multi-Master System (2/3) Enables reserving communication. Prepares for starting communication STT0 = 1 (generates a start condition). Secure wait time by software Wait (see Table 13-7). MSTS0 = 1? INTIIC0 interrupt occurs? Waits for bus release (communication being reserved).
Page 535 CHAPTER 13 SERIAL INTERFACE IIC0 Figure 13-25. Master Operation in Multi-Master System (3/3) Starts communication Writing IIC0 (specifies an address and transfer direction). INTIIC0 interrupt occurs? Waits for detection of ACK. MSTS0 = 1? ACKD0 = 1? TRC0 = 1? ACKE0 = 1 WTIM0 = 0 WTIM0 = 1...
Page 536 CHAPTER 13 SERIAL INTERFACE IIC0 (3) Slave operation The processing procedure of the slave operation is as follows. Basically, the slave operation is event-driven. Therefore, processing by the INTIIC0 interrupt (processing that must substantially change the operation status such as detection of a stop condition during communication) is necessary.
Page 537 CHAPTER 13 SERIAL INTERFACE IIC0 The main processing of the slave operation is explained next. Start serial interface IIC0 and wait until communication is enabled. When communication is enabled, execute communication by using the communication mode flag and ready flag (processing of the stop condition and start condition is performed by an interrupt.
Page 538 CHAPTER 13 SERIAL INTERFACE IIC0 An example of the processing procedure of the slave with the INTIIC0 interrupt is explained below (processing is performed assuming that no extension code is used). The INTIIC0 interrupt checks the status, and the following operations are performed. <1>...
Page 539: Timing Of I 2 C Interrupt Request (Intiic0) Occurrence
CHAPTER 13 SERIAL INTERFACE IIC0 13.5.18 Timing of I C interrupt request (INTIIC0) occurrence The timing of transmitting or receiving data and generation of interrupt request signal INTIIC0, and the value of the IICS0 register when the INTIIC0 signal is generated are shown below. Remark Start condition AD6 to AD0: Address...
Page 540 CHAPTER 13 SERIAL INTERFACE IIC0 (1) Master device operation (a) Start ~ Address ~ Data ~ Data ~ Stop (transmission/reception) (i) When WTIM0 = 0 SPT0 = 1 ↓ AD6 to AD0 R/W ACK D7 to D0 D7 to D0 1: IICS0 = 1000×110B 2: IICS0 = 1000×000B Note...
Page 541 CHAPTER 13 SERIAL INTERFACE IIC0 (b) Start ~ Address ~ Data ~ Start ~ Address ~ Data ~ Stop (restart) (i) When WTIM0 = 0 STT0 = 1 SPT0 = 1 ↓ ↓ AD6 to AD0 R/W ACK D7 to D0 AD6 to AD0 D7 to D0 1: IICS0 = 1000×110B...
Page 542 CHAPTER 13 SERIAL INTERFACE IIC0 (c) Start ~ Code ~ Data ~ Data ~ Stop (extension code transmission) (i) When WTIM0 = 0 SPT0 = 1 ↓ AD6 to AD0 R/W ACK D7 to D0 D7 to D0 1: IICS0 = 1010×110B 2: IICS0 = 1010×000B Note 3: IICS0 = 1010×000B (Sets WTIM0 to 1)
Page 543 CHAPTER 13 SERIAL INTERFACE IIC0 (2) Slave device operation (slave address data reception) (a) Start ~ Address ~ Data ~ Data ~ Stop (i) When WTIM0 = 0 AD6 to AD0 R/W ACK D7 to D0 D7 to D0 1: IICS0 = 0001×110B 2: IICS0 = 0001×000B 3: IICS0 = 0001×000B 4: IICS0 = 00000001B...
Page 544 CHAPTER 13 SERIAL INTERFACE IIC0 (b) Start ~ Address ~ Data ~ Start ~ Address ~ Data ~ Stop (i) When WTIM0 = 0 (after restart, matches with SVA0) AD6 to AD0 R/W ACK D7 to D0 AD6 to AD0 D7 to D0 1: IICS0 = 0001×110B 2: IICS0 = 0001×000B...
Page 545 CHAPTER 13 SERIAL INTERFACE IIC0 (c) Start ~ Address ~ Data ~ Start ~ Code ~ Data ~ Stop (i) When WTIM0 = 0 (after restart, does not match address (= extension code)) AD6 to AD0 R/W ACK D7 to D0 AD6 to AD0 D7 to D0 1: IICS0 = 0001×110B...
Page 546 CHAPTER 13 SERIAL INTERFACE IIC0 (d) Start ~ Address ~ Data ~ Start ~ Address ~ Data ~ Stop (i) When WTIM0 = 0 (after restart, does not match address (= not extension code)) AD6 to AD0 R/W ACK D7 to D0 AD6 to AD0 D7 to D0 1: IICS0 = 0001×110B...
Page 547 CHAPTER 13 SERIAL INTERFACE IIC0 (3) Slave device operation (when receiving extension code) The device is always participating in communication when it receives an extension code. (a) Start ~ Code ~ Data ~ Data ~ Stop (i) When WTIM0 = 0 AD6 to AD0 R/W ACK D7 to D0 D7 to D0...
Page 548 CHAPTER 13 SERIAL INTERFACE IIC0 (b) Start ~ Code ~ Data ~ Start ~ Address ~ Data ~ Stop (i) When WTIM0 = 0 (after restart, matches SVA0) AD6 to AD0 R/W ACK D7 to D0 AD6 to AD0 D7 to D0 1: IICS0 = 0010×010B 2: IICS0 = 0010×000B 3: IICS0 = 0001×110B...
Page 549 CHAPTER 13 SERIAL INTERFACE IIC0 (c) Start ~ Code ~ Data ~ Start ~ Code ~ Data ~ Stop (i) When WTIM0 = 0 (after restart, extension code reception) AD6 to AD0 R/W ACK D7 to D0 AD6 to AD0 D7 to D0 1: IICS0 = 0010×010B 2: IICS0 = 0010×000B...
Page 550 CHAPTER 13 SERIAL INTERFACE IIC0 (d) Start ~ Code ~ Data ~ Start ~ Address ~ Data ~ Stop (i) When WTIM0 = 0 (after restart, does not match address (= not extension code)) AD6 to AD0 R/W ACK D7 to D0 AD6 to AD0 D7 to D0 1: IICS0 = 00100010B...
Page 551 CHAPTER 13 SERIAL INTERFACE IIC0 (4) Operation without communication (a) Start ~ Code ~ Data ~ Data ~ Stop AD6 to AD0 R/W ACK D7 to D0 D7 to D0 1: IICS0 = 00000001B Remark : Generated only when SPIE0 = 1 (5) Arbitration loss operation (operation as slave after arbitration loss) When the device is used as a master in a multi-master system, read the MSTS0 bit each time interrupt request signal INTIIC0 has occurred to check the arbitration result.
Page 552 CHAPTER 13 SERIAL INTERFACE IIC0 (ii) When WTIM0 = 1 AD6 to AD0 R/W ACK D7 to D0 D7 to D0 1: IICS0 = 0101×110B 2: IICS0 = 0001×100B 3: IICS0 = 0001××00B 4: IICS0 = 00000001B Remark : Always generated : Generated only when SPIE0 = 1 ×: Don’t care...
Page 553 CHAPTER 13 SERIAL INTERFACE IIC0 (ii) When WTIM0 = 1 AD6 to AD0 R/W ACK D7 to D0 D7 to D0 1: IICS0 = 0110×010B 2: IICS0 = 0010×110B 3: IICS0 = 0010×100B 4: IICS0 = 0010××00B 5: IICS0 = 00000001B Remark : Always generated : Generated only when SPIE0 = 1...
Page 554 CHAPTER 13 SERIAL INTERFACE IIC0 (b) When arbitration loss occurs during transmission of extension code AD6 to AD0 R/W ACK D7 to D0 D7 to D0 1: IICS0 = 0110×010B Sets LREL0 = 1 by software 2: IICS0 = 00000001B Remark : Always generated : Generated only when SPIE0 = 1...
Page 555 CHAPTER 13 SERIAL INTERFACE IIC0 (ii) When WTIM0 = 1 AD6 to AD0 R/W ACK D7 to D0 D7 to D0 1: IICS0 = 10001110B 2: IICS0 = 01000100B 3: IICS0 = 00000001B Remark : Always generated : Generated only when SPIE0 = 1 (d) When loss occurs due to restart condition during data transfer (i) Not extension code (Example: unmatches with SVA0) AD6 to AD0 R/W ACK...
Page 556 CHAPTER 13 SERIAL INTERFACE IIC0 (ii) Extension code AD6 to AD0 R/W ACK D7 to Dn AD6 to AD0 D7 to D0 1: IICS0 = 1000×110B 2: IICS0 = 01100010B Sets LREL0 = 1 by software 3: IICS0 = 00000001B Remark : Always generated : Generated only when SPIE0 = 1...
Page 557 CHAPTER 13 SERIAL INTERFACE IIC0 (f) When arbitration loss occurs due to low-level data when attempting to generate a restart condition (i) When WTIM0 = 0 STT0 = 1 ↓ AD6 to AD0 R/W ACK D7 to D0 D7 to D0 D7 to D0 1: IICS0 = 1000×110B 2: IICS0 = 1000×000B (Sets WTIM0 to 1)
Page 558 CHAPTER 13 SERIAL INTERFACE IIC0 (g) When arbitration loss occurs due to a stop condition when attempting to generate a restart condition (i) When WTIM0 = 0 STT0 = 1 ↓ AD6 to AD0 R/W ACK D7 to D0 1: IICS0 = 1000×110B 2: IICS0 = 1000×000B (Sets WTIM0 to 1) 3: IICS0 = 1000××00B (Sets STT0 to 1) 4: IICS0 = 01000001B...
Page 559 CHAPTER 13 SERIAL INTERFACE IIC0 (h) When arbitration loss occurs due to low-level data when attempting to generate a stop condition (i) When WTIM0 = 0 SPT0 = 1 ↓ AD6 to AD0 R/W ACK D7 to D0 D7 to D0 D7 to D0 1: IICS0 = 1000×110B 2: IICS0 = 1000×000B (Sets WTIM0 to 1)
Page 560: Timing Charts
CHAPTER 13 SERIAL INTERFACE IIC0 13.6 Timing Charts When using the I C bus mode, the master device outputs an address via the serial bus to select one of several slave devices as its communication partner. After outputting the slave address, the master device transmits the TRC0 bit (bit 3 of IIC status register 0 (IICS0)), which specifies the data transfer direction, and then starts serial communication with the slave device.
Page 561 CHAPTER 13 SERIAL INTERFACE IIC0 Figure 13-28. Example of Master to Slave Communication (When 9-Clock Wait Is Selected for Both Master and Slave) (1/3) (1) Start condition ~ address Processing by master device ← ← IIC0 IIC0 address IIC0 data Note 1 ACKD0 STD0 SPD0...
Page 562 CHAPTER 13 SERIAL INTERFACE IIC0 Figure 13-28. Example of Master to Slave Communication (When 9-Clock Wait Is Selected for Both Master and Slave) (2/3) (2) Data Processing by master device ← ← IIC0 data Note 1 IIC0 data Note 1 IIC0 ACKD0 STD0...
Page 563 CHAPTER 13 SERIAL INTERFACE IIC0 Figure 13-28. Example of Master to Slave Communication (When 9-Clock Wait Is Selected for Both Master and Slave) (3/3) (3) Stop condition Processing by master device ← ← IIC0 IIC0 data Note 1 IIC0 address ACKD0 STD0 SPD0...
Page 564 CHAPTER 13 SERIAL INTERFACE IIC0 Figure 13-29. Example of Slave to Master Communication (When 8-Clock Wait Is Selected for Master, 9-Clock Wait Is Selected for Slave) (1/3) (1) Start condition ~ address Processing by master device ← ← IIC0 IIC0 address IIC0 FFH Note 1...
Page 565 CHAPTER 13 SERIAL INTERFACE IIC0 Figure 13-29. Example of Slave to Master Communication (When 8-Clock Wait Is Selected for Master, 9-Clock Wait Is Selected for Slave) (2/3) (2) Data Processing by master device ← ← IIC0 IIC0 FFH Note 1 IIC0 FFH Note 1 ACKD0...
Page 566 CHAPTER 13 SERIAL INTERFACE IIC0 Figure 13-29. Example of Slave to Master Communication (When 8-Clock and 9-Clock Wait Is Selected for Master, 9-Clock Wait Is Selected for Slave) (3/3) (3) Stop condition Processing by master device ← IIC0 address ← IIC0 IIC0 FFH Note 1...
Page 567: Chapter 14 Multiplier
CHAPTER 14 MULTIPLIER 14.1 Functions of Multiplier The multiplier has the following functions. • Can execute calculation of 16 bits × 16 bits = 32 bits. Figure 14-1 shows the block diagram of the multiplier. Figure 14-1. Block Diagram of Multiplier Internal bus Multiplication input data Multiplication input data...
Page 568: Configuration Of Multiplier
CHAPTER 14 MULTIPLIER 14.2 Configuration of Multiplier (1) 16-bit higher multiplication result storage register and 16-bit lower multiplication result storage register (MULOH, MULOL) These two registers, MULOH and MULOL, are used to store a 32-bit multiplication result. The higher 16 bits of the multiplication result are stored in MULOH and the lower 16 bits, in MULOL, so that a total of 32 bits of the multiplication result can be stored.
Page 569: Operation Of Multiplier
CHAPTER 14 MULTIPLIER 14.3 Operation of Multiplier The result of the multiplication can be obtained by storing the values in the MULA and MULB registers and then reading the MULOH and MULOL registers after waiting for 1 clock. The result can also be obtained after 1 clock or more has elapsed, even when fixing either of MULA or MULB and rewrite the other of these.
Page 570: Chapter 15 Dma Controller
CHAPTER 15 DMA CONTROLLER The 78K0R/KF3 has an internal DMA (Direct Memory Access) controller. Data can be automatically transferred between the peripheral hardware supporting DMA, SFRs, and internal RAM without via CPU. As a result, the normal internal operation of the CPU and data transfer can be executed in parallel with transfer between the SFR and internal RAM, and therefore, a large capacity of data can be processed.
Page 571: Configuration Of Dma Controller
CHAPTER 15 DMA CONTROLLER 15.2 Configuration of DMA Controller The DMA controller includes the following hardware. Table 15-1. Configuration of DMA Controller Item Configuration • DMA SFR address registers 0, 1 (DSA0, DSA1) Address registers • DMA RAM address registers 0, 1 (DRA0, DRA1) •...
Page 572 CHAPTER 15 DMA CONTROLLER (2) DMA RAM address register n (DRAn) This is a 16-bit register that is used to set a RAM address that is the transfer source or destination of DMA channel n. Addresses of the internal RAM area other than the general-purpose registers (FEF00H to FFEDFH in the μ...
Page 573 CHAPTER 15 DMA CONTROLLER (3) DMA byte count register n (DBCn) This is a 10-bit register that is used to set the number of times DMA channel n executes transfer. Be sure to set the number of times of transfer to this DBCn register before executing DMA transfer (up to 1024 times). Each time DMA transfer has been executed, this register is automatically decremented.
Page 574: Registers Controlling Dma Controller
CHAPTER 15 DMA CONTROLLER 15.3 Registers Controlling DMA Controller DMA controller is controlled by the following registers. • DMA mode control register n (DMCn) • DMA operation control register n (DRCn) Remark n: DMA channel number (n = 0, 1) User’s Manual U17893EJ8V0UD...
Page 575 CHAPTER 15 DMA CONTROLLER (1) DMA mode control register n (DMCn) DMCn is a register that is used to set a transfer mode of DMA channel n. It is used to select a transfer direction, data size, setting of pending, and start source. Bit 7 (STGn) is a software trigger that starts DMA. Rewriting bits 6, 5, and 3 to 0 of DMCn is prohibited during operation (when DSTn = 1).
Page 576 CHAPTER 15 DMA CONTROLLER Figure 15-4. Format of DMA Mode Control Register n (DMCn) (2/2) Address: FFFBAH (DMC0), FFFBBH (DMC1) After reset: 00H Symbol <7> <6> <5> <4> DMCn STGn DRSn DWAITn IFCn3 IFCn2 IFCn1 IFCn0 Note IFCn IFCn IFCn IFCn Selection of DMA start source Trigger signal...
Page 577 CHAPTER 15 DMA CONTROLLER (2) DMA operation control register n (DRCn) DRCn is a register that is used to enable or disable transfer of DMA channel n. Rewriting bit 7 (DENn) of this register is prohibited during operation (when DSTn = 1). DRCn can be set by a 1-bit or 8-bit memory manipulation instruction.
Page 578: Operation Of Dma Controller
CHAPTER 15 DMA CONTROLLER 15.4 Operation of DMA Controller 15.4.1 Operation procedure <1> The DMA controller is enabled to operate when DENn = 1. Before writing the other registers, be sure to set DENn to 1. Use 80H to write with an 8-bit manipulation instruction. <2>...
Page 579 CHAPTER 15 DMA CONTROLLER Figure 15-6. Operation Procedure DENn = 1 Set by software program Setting DSAn, DRAn, DBCn, and DMCn DSTn = 1 DMA trigger = 1? Transmitting DMA request Receiving DMA acknowledge Operation by DMA DMA transfer controller (hardware) DRAn = DRAn + 1 (or + 2) DBCn = DBCn −...
Page 580: Transfer Mode
CHAPTER 15 DMA CONTROLLER 15.4.2 Transfer mode The following four modes can be selected for DMA transfer by using bits 6 and 5 (DRSn and DSn) of the DMCn register. DRSn DMA Transfer Mode Transfer from SFR of 1-byte data (fixed address) to RAM (address is incremented by +1) Transfer from SFR of 2-byte data (fixed address) to RAM (address is incremented by +2) Transfer from RAM of 1-byte data (address is incremented by +1) to SFR (fixed address) Transfer from RAM of 2-byte data (address is incremented by +2) to SFR (fixed address)
Page 581: Example Of Setting Of Dma Controller
CHAPTER 15 DMA CONTROLLER 15.5 Example of Setting of DMA Controller 15.5.1 CSI consecutive transmission A flowchart showing an example of setting for CSI consecutive transmission is shown below. • Consecutive transmission (256 KB) of CSI00 • DMA channel 0 is used for DMA transfer. •...
Page 582 CHAPTER 15 DMA CONTROLLER Figure 15-7. Setting Example of CSI Consecutive Transmission Start DEN0 = 1 DSA0 = 10H DRA0 = F100H DBC0 = 0100H DMC0 = 46H Setting for CSI transfer DST0 = 1 DMA is started. STG0 = 1 INTCSI00 occurs.
Page 583: Csi Master Reception
CHAPTER 15 DMA CONTROLLER <R> 15.5.2 CSI master reception A flowchart showing an example of setting for CSI master reception is shown below. • Master reception (256 KB) of CSI00 • DMA channel 0 is used to read received data and DMA channel 1 is used to write dummy data. •...
Page 584 CHAPTER 15 DMA CONTROLLER Figure 15-8. Setting Example of CSI Master Reception Start DEN0 = 1 DEN1 = 1 DSA0 = 10H DRA0 = F100H DBC0 = 0100H DMC0 = 06H DSA1 = 10H DRA1 = F101H DBC1 = 00FFH DMC1 = 46H Setting for CSI transfer DST0 = 1...
Page 585: Csi Transmission/Reception
CHAPTER 15 DMA CONTROLLER <R> 15.5.3 CSI transmission/reception A flowchart showing an example of setting for CSI transmission/reception is shown below. • Transmission/reception (256 KB) of CSI00 • DMA channel 0 is used to read received data and DMA channel 1 is used to write transmit data. •...
Page 586 CHAPTER 15 DMA CONTROLLER Figure 15-9. Setting Example of CSI Transmission/reception Start DEN0 = 1 DEN1 = 1 DSA0 = 10H DRA0 = F100H DBC0 = 0100H DMC0 = 06H DSA1 = 10H DRA1 = F201H DBC1 = 00FFH DMC1 = 46H Setting for CSI transfer DST0 = 1 DST1 = 1...
Page 587: Consecutive Capturing Of A/D Conversion Results
CHAPTER 15 DMA CONTROLLER 15.5.4 Consecutive capturing of A/D conversion results A flowchart of an example of setting for consecutively capturing A/D conversion results is shown below. • Consecutive capturing of A/D conversion results. • DMA channel 1 is used for DMA transfer. •...
Page 588 CHAPTER 15 DMA CONTROLLER Figure 15-10. Setting Example of Consecutively Capturing A/D Conversion Results Start DEN1 = 1 DSA1 = 1EH DRA1 = F380H DBC1 = 0000H DMC1 = 2CH DST1 = 1 Starting A/D conversion INTAD occurs. User program processing DMA1 transfer INTDMA1 occurs.
Page 589: Uart Consecutive Reception + Ack Transmission
CHAPTER 15 DMA CONTROLLER 15.5.5 UART consecutive reception + ACK transmission A flowchart illustrating an example of setting for UART consecutive reception + ACK transmission is shown below. • Consecutively receives data from UART0 and outputs ACK to P10 on completion of reception. •...
Page 590 CHAPTER 15 DMA CONTROLLER Figure 15-11. Setting Example of UART Consecutive Reception + ACK Transmission Start INTSR0 interrupt routine DEN0 = 1 DSA0 = 12H STG0 = 1 DRA0 = FE00H DBC0 = 0040H DMC0 = 00H DMA0 transfer P10 = 1 Setting for UART reception P10 = 0 DST0 = 1...
Page 591: Holding Dma Transfer Pending By Dwaitn
CHAPTER 15 DMA CONTROLLER 15.5.6 Holding DMA transfer pending by DWAITn When DMA transfer is started, transfer is performed while an instruction is executed. At this time, the operation of the CPU is stopped and delayed for the duration of 2 clocks. If this poses a problem to the operation of the set <R>...
Page 592: Forced Termination By Software
CHAPTER 15 DMA CONTROLLER 15.5.7 Forced termination by software After DSTn is set to 0 by software, it takes up to 2 clocks until a DMA transfer is actually stopped and DSTn is set to 0. To forcibly terminate a DMA transfer by software without waiting for occurrence of the interrupt (INTDMAn) of DMAn, therefore, perform either of the following processes.
Page 593 CHAPTER 15 DMA CONTROLLER Figure 15-13. Forced Termination of DMA Transfer (2/2) Example 3 • Procedure for forcibly terminating the DMA • Procedure for forcibly terminating the DMA transfer for one channel if both channels are used transfer for both channels if both channels are used DWAIT0 = 1 DWAIT0 = 1 DWAIT1 = 1...
Page 594: Cautions On Using Dma Controller
CHAPTER 15 DMA CONTROLLER 15.6 Cautions on Using DMA Controller <R> (1) Priority of DMA During DMA transfer, a request from the other DMA channel is held pending even if generated. The pending DMA transfer is started after the ongoing DMA transfer is completed. If two DMA requests are generated at the same time, however, DMA channel 0 takes priority over DMA channel 1.
Page 595 CHAPTER 15 DMA CONTROLLER <R> (2) DMA response time The response time of DMA transfer is as follows. Table 15-2. Response Time of DMA Transfer Minimum Time Maximum Time Note Response time 3 clocks 10 clocks Note The maximum time necessary to execute an instruction from internal RAM is 16 clock cycles. Cautions 1.
Page 596 CHAPTER 15 DMA CONTROLLER (4) DMA pending instruction Even if a DMA request is generated, DMA transfer is held pending immediately after the following instructions. • CALL !addr16 • CALL <R> $!addr20 • CALL !!addr20 • CALL • CALLT [addr5] •...
Page 597: Chapter 16 Interrupt Functions
16.2 Interrupt Sources and Configuration The 78K0R/KF3 has a total of 42 interrupt sources including maskable interrupts and software interrupts. In addition, they also have up to five reset sources (see Table 16-1). The vector codes that store the program start address when branching due to the generation of a reset or various interrupt requests are two bytes each, so interrupts jump to a 64 K address of 00000H to 0FFFFH.
Page 598 CHAPTER 16 INTERRUPT FUNCTIONS Table 16-1. Interrupt Source List (1/2) Interrupt Default Interrupt Source Internal/ Vector Basic Note 1 Type Priority External Table Configuration Name Trigger Note 2 Address Type Note 3 Maskable INTWDTI Watchdog timer interval Internal 0004H (75% of overflow time) Note 4 INTLVI Low-voltage detection...
Page 599 CHAPTER 16 INTERRUPT FUNCTIONS Table 16-1. Interrupt Source List (2/2) Interrupt Default Interrupt Source Internal/ Vector Basic Note 1 Type Priority External Table Configuration Name Trigger Note 2 Address Type Maskable INTAD End of A/D conversion Internal 0034H INTRTC Fixed-cycle signal of real-time counter/alarm 0036H match detection INTRTCI...
Page 600 CHAPTER 16 INTERRUPT FUNCTIONS Figure 16-1. Basic Configuration of Interrupt Function (1/2) (A) Internal maskable interrupt Internal bus ISP1 ISP0 Vector table Interrupt Priority controller address generator request Standby release signal <R> (B) External maskable interrupt (INTPn) Internal bus External interrupt edge enable register ISP1 ISP0...
Page 601 CHAPTER 16 INTERRUPT FUNCTIONS Figure 16-1. Basic Configuration of Interrupt Function (2/2) <R> (C) External maskable interrupt (INTKR) Internal bus Key return mode register ISP1 ISP0 (KRM) KRMm Vector table Key Interrupt Priority controller address generator KRm pin detector input Standby release signal (D) Software interrupt...
Page 602: Registers Controlling Interrupt Functions
CHAPTER 16 INTERRUPT FUNCTIONS 16.3 Registers Controlling Interrupt Functions The following 6 types of registers are used to control the interrupt functions. • Interrupt request flag registers (IF0L, IF0H, IF1L, IF1H, IF2L, IF2H) • Interrupt mask flag registers (MK0L, MK0H, MK1L, MK1H, MK2L, MK2H) •...
Page 603 CHAPTER 16 INTERRUPT FUNCTIONS Table 16-2. Flags Corresponding to Interrupt Request Sources (2/2) Interrupt Interrupt Request Flag Interrupt Mask Flag Priority Specification Flag Source Register Register Register Note 1 Note 1 Note 1 Note 1 INTST1 STIF1 IF1L STMK1 MK1L STPR01, STPR11 PR01L, PR11L...
Page 604 CHAPTER 16 INTERRUPT FUNCTIONS (1) Interrupt request flag registers (IF0L, IF0H, IF1L, IF1H, IF2L, IF2H) The interrupt request flags are set to 1 when the corresponding interrupt request is generated or an instruction is executed. They are cleared to 0 when an instruction is executed upon acknowledgment of an interrupt request or upon reset signal generation.
Page 605 CHAPTER 16 INTERRUPT FUNCTIONS Figure 16-2. Format of Interrupt Request Flag Registers (IF0L, IF0H, IF1L, IF1H, IF2L, IF2H) (2/2) Address: FFFD1H After reset: 00H Symbol <0> IF2H PIF11 XXIFX Interrupt request flag No interrupt request signal is generated Interrupt request is generated, interrupt request status Cautions 1.
Page 606 CHAPTER 16 INTERRUPT FUNCTIONS Figure 16-3. Format of Interrupt Mask Flag Registers (MK0L, MK0H, MK1L, MK1H, MK2L, MK2H) Address: FFFE4H After reset: FFH Symbol <7> <6> <5> <4> <3> <2> <1> <0> MK0L PMK5 PMK4 PMK3 PMK2 PMK1 PMK0 LVIMK WDTIMK Address: FFFE5H After reset: FFH...
Page 607 CHAPTER 16 INTERRUPT FUNCTIONS (3) Priority specification flag registers (PR00L, PR00H, PR01L, PR01H, PR02L, PR02H, PR10L, PR10H, PR11L, PR11H, PR12L, PR12H) The priority specification flag registers are used to set the corresponding maskable interrupt priority level. A priority level is set by using the PR0xy and PR1xy registers in combination (xy = 0L, 0H, 1L, 1H, 2L, or 2H). PR00L, PR00H, PR01L, PR01H, PR02L, PR02H, PR10L, PR10H, PR11L, PR11H, PR12L, and PR12H can be set by a 1-bit or 8-bit memory manipulation instruction.
Page 608 CHAPTER 16 INTERRUPT FUNCTIONS Figure 16-4. Format of Priority Specification Flag Registers (PR00L, PR00H, PR01L, PR01H, PR02L, PR02H, PR10L, PR10H, PR11L, PR11H, PR12L, PR12H) (2/2) Address: FFFEBH After reset: FFH Symbol <7> <6> <5> <4> <3> <2> <1> <0> PR01H TMPR004 SREPR02 SRPR02...
Page 609 CHAPTER 16 INTERRUPT FUNCTIONS (4) External interrupt rising edge enable registers (EGP0, EGP1), external interrupt falling edge enable registers (EGN0, EGN1) These registers specify the valid edge for INTP0 to INTP11. EGP0, EGP1, EGN0, and EGN1 can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears these registers to 00H.
Page 610 CHAPTER 16 INTERRUPT FUNCTIONS Table 16-3. Ports Corresponding to EGPn and EGNn Detection Enable Register Edge Detection Port Interrupt Request Signal EGP0 EGN0 P120 INTP0 EGP1 EGN1 INTP1 EGP2 EGN2 INTP2 EGP3 EGN3 INTP3 EGP4 EGN4 INTP4 EGP5 EGN5 INTP5 EGP6 EGN6 P140...
Page 611 CHAPTER 16 INTERRUPT FUNCTIONS (5) Program status word (PSW) The program status word is a register used to hold the instruction execution result and the current status for an interrupt request. The IE flag that sets maskable interrupt enable/disable and the ISP0 and ISP1 flags that controls multiple interrupt servicing are mapped to the PSW.
Page 612: Interrupt Servicing Operations
CHAPTER 16 INTERRUPT FUNCTIONS 16.4 Interrupt Servicing Operations 16.4.1 Maskable interrupt acknowledgment A maskable interrupt becomes acknowledgeable when the interrupt request flag is set to 1 and the mask (MK) flag corresponding to that interrupt request is cleared to 0. A vectored interrupt request is acknowledged if interrupts are in the interrupt enabled state (when the IE flag is set to 1).
Page 613 CHAPTER 16 INTERRUPT FUNCTIONS Figure 16-7. Interrupt Request Acknowledgment Processing Algorithm Start ××IF = 1? Yes (interrupt request generation) ××MK = 0? Interrupt request held pending ××PR No (Low priority) (××PR ≥ (ISP1, ISP0) Interrupt request held pending Higher priority than other interrupt requests simultaneously generated?
Page 614: Software Interrupt Request Acknowledgment
CHAPTER 16 INTERRUPT FUNCTIONS Figure 16-8. Interrupt Request Acknowledgment Timing (Minimum Time) 6 clocks PSW and PC saved, Interrupt servicing CPU processing Instruction Instruction jump to interrupt program servicing ××IF 9 clocks Remark 1 clock: 1/f : CPU clock) Figure 16-9. Interrupt Request Acknowledgment Timing (Maximum Time) 6 clocks 6 clocks PSW and PC saved,...
Page 615: Multiple Interrupt Servicing
CHAPTER 16 INTERRUPT FUNCTIONS 16.4.3 Multiple interrupt servicing Multiple interrupt servicing occurs when another interrupt request is acknowledged during execution of an interrupt. Multiple interrupt servicing does not occur unless the interrupt request acknowledgment enabled state is selected (IE = 1). When an interrupt request is acknowledged, interrupt request acknowledgment becomes disabled (IE = 0). Therefore, to enable multiple interrupt servicing, it is necessary to set (1) the IE flag with the EI instruction during interrupt servicing to enable interrupt acknowledgment.
Page 616 CHAPTER 16 INTERRUPT FUNCTIONS Figure 16-10. Examples of Multiple Interrupt Servicing (1/2) Example 1. Multiple interrupt servicing occurs twice Main processing INTxx servicing INTyy servicing INTzz servicing IE = 0 IE = 0 IE = 0 INTxx INTyy INTzz (PR = 11) (PR = 10) (PR = 01) RETI...
Page 617 CHAPTER 16 INTERRUPT FUNCTIONS Figure 16-10. Examples of Multiple Interrupt Servicing (2/2) Example 3. Multiple interrupt servicing does not occur because interrupts are not enabled Main processing INTxx servicing INTyy servicing IE = 0 INTyy (PR = 00) INTxx RETI (PR = 11) IE = 1 IE = 0...
Page 618: Interrupt Request Hold
CHAPTER 16 INTERRUPT FUNCTIONS 16.4.4 Interrupt request hold There are instructions where, even if an interrupt request is issued while the instruction are being executed, interrupt request acknowledgment is held pending until the end of execution of the next instruction. These instructions (interrupt request hold instructions) are listed below.
Page 619: Chapter 17 Key Interrupt Function
CHAPTER 17 KEY INTERRUPT FUNCTION 17.1 Functions of Key Interrupt A key interrupt (INTKR) can be generated by setting the key return mode register (KRM) and inputting a falling edge to the key interrupt input pins (KR0 to KR7). Table 17-1. Assignment of Key Interrupt Detection Pins Flag Description KRM0...
Page 620: Register Controlling Key Interrupt
CHAPTER 17 KEY INTERRUPT FUNCTION 17.3 Register Controlling Key Interrupt (1) Key return mode register (KRM) This register controls the KRM0 to KRM7 bits using the KR0 to KR7 signals, respectively. KRM can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears this register to 00H.
Page 621: Chapter 18 Standby Function
CHAPTER 18 STANDBY FUNCTION 18.1 Standby Function and Configuration 18.1.1 Standby function The standby function reduces the operating current of the system, and the following two modes are available. (1) HALT mode HALT instruction execution sets the HALT mode. In the HALT mode, the CPU operation clock is stopped. If the high-speed system clock oscillator, internal high-speed oscillator, or subsystem clock oscillator is operating before the HALT mode is set, oscillation of each clock continues.
Page 622 CHAPTER 18 STANDBY FUNCTION (1) Oscillation stabilization time counter status register (OSTC) This is the register that indicates the count status of the X1 clock oscillation stabilization time counter. The X1 clock oscillation stabilization time can be checked in the following case, •...
Page 623 CHAPTER 18 STANDBY FUNCTION (2) Oscillation stabilization time select register (OSTS) This register is used to select the X1 clock oscillation stabilization wait time when the STOP mode is released. When the X1 clock is selected as the CPU clock, the operation waits for the time set using OSTS after the STOP mode is released.
Page 624: Standby Function Operation
CHAPTER 18 STANDBY FUNCTION 18.2 Standby Function Operation 18.2.1 HALT mode (1) HALT mode The HALT mode is set by executing the HALT instruction. HALT mode can be set regardless of whether the CPU clock before the setting was the high-speed system clock, internal high-speed oscillation clock, or subsystem clock.
Page 625 CHAPTER 18 STANDBY FUNCTION Table 18-1. Operating Statuses in HALT Mode (1/2) HALT Mode Setting When HALT Instruction Is Executed While CPU Is Operating on Main System Clock When CPU Is Operating on When CPU Is Operating on When CPU Is Operating on Internal High-Speed X1 Clock (f External Main System Clock...
Page 626 CHAPTER 18 STANDBY FUNCTION Table 18-1. Operating Statuses in HALT Mode (2/2) HALT Mode Setting When HALT Instruction Is Executed While CPU Is Operating on Subsystem Clock Item When CPU Is Operating on XT1 Clock (f System clock Clock supply to the CPU is stopped Main system clock Status before HALT mode was set is retained Operates or stops by external clock input...
Page 627 CHAPTER 18 STANDBY FUNCTION (2) HALT mode release The HALT mode can be released by the following two sources. (a) Release by unmasked interrupt request When an unmasked interrupt request is generated, the HALT mode is released. If interrupt acknowledgment is enabled, vectored interrupt servicing is carried out.
Page 628 CHAPTER 18 STANDBY FUNCTION (b) Release by reset signal generation When the reset signal is generated, HALT mode is released, and then, as in the case with a normal reset operation, the program is executed after branching to the reset vector address. Figure 18-4.
Page 629: Stop Mode
CHAPTER 18 STANDBY FUNCTION 18.2.2 STOP mode (1) STOP mode setting and operating statuses The STOP mode is set by executing the STOP instruction, and it can be set only when the CPU clock before the setting was the main system clock. Caution Because the interrupt request signal is used to clear the standby mode, if there is an interrupt source with the interrupt request flag set and the interrupt mask flag reset, the standby mode is immediately cleared if set.
Page 630 CHAPTER 18 STANDBY FUNCTION Table 18-2. Operating Statuses in STOP Mode STOP Mode Setting When STOP Instruction Is Executed While CPU Is Operating on Main System Clock When CPU Is Operating on When CPU Is Operating on When CPU Is Operating on Internal High-Speed X1 Clock (f External Main System Clock...
Page 631 CHAPTER 18 STANDBY FUNCTION Cautions 1. To use the peripheral hardware that stops operation in the STOP mode, and the peripheral hardware for which the clock that stops oscillating in the STOP mode after the STOP mode is released, restart the peripheral hardware. 2.
Page 632 CHAPTER 18 STANDBY FUNCTION (2) STOP mode release Figure 18-5. Operation Timing When STOP Mode Is Released (Release by Unmasked Interrupt Request) STOP mode release STOP mode High-speed system clock (X1 oscillation) High-speed system clock (external clock input) Internal high-speed oscillation clock Wait for oscillation accuracy stabilization High-speed system...
Page 633 CHAPTER 18 STANDBY FUNCTION (a) Release by unmasked interrupt request When an unmasked interrupt request is generated, the STOP mode is released. After the oscillation stabilization time has elapsed, if interrupt acknowledgment is enabled, vectored interrupt servicing is carried out. If interrupt acknowledgment is disabled, the next address instruction is executed. Figure 18-6.
Page 634 CHAPTER 18 STANDBY FUNCTION Figure 18-6. STOP Mode Release by Interrupt Request Generation (2/2) (3) When internal high-speed oscillation clock is used as CPU clock Interrupt request STOP instruction Standby release signal Supply of the CPU Normal operation Normal operation clock is stopped (internal high-speed (internal high-speed...
Page 635 CHAPTER 18 STANDBY FUNCTION (b) Release by reset signal generation When the reset signal is generated, STOP mode is released, and then, as in the case with a normal reset operation, the program is executed after branching to the reset vector address. Figure 18-7.
Page 636: Chapter 19 Reset Function
CHAPTER 19 RESET FUNCTION The following five operations are available to generate a reset signal. (1) External reset input via RESET pin (2) Internal reset by watchdog timer program loop detection (3) Internal reset by comparison of supply voltage and detection voltage of power-on-clear (POC) circuit (4) Internal reset by comparison of supply voltage of the low-voltage detector (LVI) or input voltage (EXLVI) from external input pin, and detection voltage Note...
Page 637 Figure 19-1. Block Diagram of Reset Function Internal bus Reset control flag register (RESF) TRAP WDRF LVIRF Watchdog timer reset signal Clear Clear Clear Reset signal by execution of illegal instruction RESF register read signal Reset signal to LVIM/LVIS register RESET Power-on clear circuit reset signal Reset signal...
Page 638 CHAPTER 19 RESET FUNCTION Figure 19-2. Timing of Reset by RESET Input Wait for oscillation accuracy stabilization Internal high-speed oscillation clock Starting X1 oscillation is specified by software. High-speed system clock (when X1 oscillation is selected) Normal operation Reset period CPU status Normal operation (internal high-speed oscillation clock)
Page 639 CHAPTER 19 RESET FUNCTION Figure 19-4. Timing of Reset in STOP Mode by RESET Input Wait for oscillation accuracy stabilization STOP instruction execution Internal high-speed oscillation clock Starting X1 oscillation is specified by software. High-speed system clock (when X1 oscillation is selected) Normal Stop status Reset period...
Page 640 CHAPTER 19 RESET FUNCTION Table 19-1. Operation Statuses During Reset Period Item During Reset Period System clock Clock supply to the CPU is stopped. Main system clock Operation stopped Operation stopped (X1 and X2 pins are input port mode) Clock input invalid (pin is input port mode) Subsystem clock Operation stopped (XT1 and XT2 pins are input port mode) Operation stopped...
Page 641 CHAPTER 19 RESET FUNCTION Table 19-2. Hardware Statuses After Reset Acknowledgment (1/3) Hardware After Reset Note 1 Acknowledgment Program counter (PC) The contents of the reset vector table (0000H, 0001H) are set. Stack pointer (SP) Undefined Program status word (PSW) Note 2 Data memory Undefined...
Page 642 CHAPTER 19 RESET FUNCTION Table 19-2. Hardware Statuses After Reset Acknowledgment (2/3) Hardware Status After Reset Note 1 Acknowledgment Real-time counter Subcount register (RSUBC) 0000H Second count register (SEC) Minute count register (MIN) Hour count register (HOUR) Day count register (DAY) Week count register (WEEK) Month count register (MONTH) Year count register (YEAR)
Page 643 CHAPTER 19 RESET FUNCTION Table 19-2. Hardware Statuses After Reset Acknowledgment (3/3) Hardware Status After Reset Note 1 Acknowledgment Serial interface IIC0 Shift register 0 (IIC0) Control register 0 (IICC0) Slave address register 0 (SVA0) Clock select register 0 (IICCL0) Function expansion register 0 (IICX0) Status register 0 (IICS0) Flag register 0 (IICF0)
Page 644: Register For Confirming Reset Source
CHAPTER 19 RESET FUNCTION 19.1 Register for Confirming Reset Source Many internal reset generation sources exist in the 78K0R/KF3. The reset control flag register (RESF) is used to store which source has generated the reset request. RESF can be read by an 8-bit memory manipulation instruction.
Page 645: Chapter 20 Power-On-Clear Circuit
CHAPTER 20 POWER-ON-CLEAR CIRCUIT 20.1 Functions of Power-on-Clear Circuit The power-on-clear circuit (POC) has the following functions. • Generates internal reset signal at power on. ) exceeds 1.59 V ±0.09 V. The reset signal is released when the supply voltage (V Caution If the low-voltage detector (LVI) is set to ON by an option byte by default, the reset signal is not ) exceeds 2.07 V ±0.2 V.
Page 646: Configuration Of Power-On-Clear Circuit
CHAPTER 20 POWER-ON-CLEAR CIRCUIT 20.2 Configuration of Power-on-Clear Circuit The block diagram of the power-on-clear circuit is shown in Figure 20-1. Figure 20-1. Block Diagram of Power-on-Clear Circuit Internal reset signal − Reference voltage source 20.3 Operation of Power-on-Clear Circuit •...
Page 647 CHAPTER 20 POWER-ON-CLEAR CIRCUIT Figure 20-2. Timing of Generation of Internal Reset Signal by Power-on-Clear Circuit and Low-Voltage Detector (1/2) (1) When LVI is OFF upon power application (option byte: LVIOFF = 1) Set LVI to be Set LVI to be Set LVI to be used for reset used for interrupt...
Page 648 CHAPTER 20 POWER-ON-CLEAR CIRCUIT Figure 20-2. Timing of Generation of Internal Reset Signal by Power-on-Clear Circuit and Low-Voltage Detector (2/2) (2) When LVI is ON upon power application (option byte: LVIOFF = 0) Set LVI Set LVI to be Set LVI Change LVI = 2.07 V) used for interrupt...
Page 649: Cautions For Power-On-Clear Circuit
CHAPTER 20 POWER-ON-CLEAR CIRCUIT 20.4 Cautions for Power-on-Clear Circuit In a system where the supply voltage (V ) fluctuates for a certain period in the vicinity of the POC detection voltage (V ), the system may be repeatedly reset and released from the reset status. In this case, the time from release of reset to the start of the operation of the microcontroller can be arbitrarily set by taking the following action.
Page 650 CHAPTER 20 POWER-ON-CLEAR CIRCUIT Figure 20-3. Example of Software Processing After Reset Release (2/2) • Checking reset source Check reset source TRAP of RESF register = 1? Reset processing by Note illegal instruction execution WDRF of RESF register = 1? Reset processing by watchdog timer LVIRF of RESF...
Page 651: Chapter 21 Low-Voltage Detector
CHAPTER 21 LOW-VOLTAGE DETECTOR 21.1 Functions of Low-Voltage Detector The low-voltage detector (LVI) has the following functions. • The LVI circuit compares the supply voltage (V ) with the detection voltage (V ) or the input voltage from an = 1.21 V ±0.1 V), and generates an internal reset Note external input pin (EXLVI) with the detection voltage (V EXLVI...
Page 652: Configuration Of Low-Voltage Detector
CHAPTER 21 LOW-VOLTAGE DETECTOR 21.2 Configuration of Low-Voltage Detector The block diagram of the low-voltage detector is shown in Figure 21-1. Figure 21-1. Block Diagram of Low-Voltage Detector N-ch Internal reset signal EXLVI/P120/ INTP0 − INTLVI Reference voltage source Low-voltage detection level Low-voltage detection register select register (LVIS) (LVIM)
Page 653 CHAPTER 21 LOW-VOLTAGE DETECTOR Figure 21-2. Format of Low-Voltage Detection Register (LVIM) Note 1 Note 2 Address: FFFA9H After reset: 00H <7> <2> <1> <0> Symbol LVION LVISEL LVIMD LVIF LVIM Notes 3, 4 LVION Enables low-voltage detection operation Disables operation Enables operation Note 3 LVISEL...
Page 654 CHAPTER 21 LOW-VOLTAGE DETECTOR Note When LVION is set to 1, operation of the comparator in the LVI circuit is started. Use software to wait for the following periods of time, between when LVION is set to 1 and when the voltage is confirmed with LVIF.
Page 655 CHAPTER 21 LOW-VOLTAGE DETECTOR (2) Low-voltage detection level select register (LVIS) This register selects the low-voltage detection level. This register can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation input sets this register to 0EH. Figure 21-3.
Page 656 CHAPTER 21 LOW-VOLTAGE DETECTOR Cautions 2. Change the LVIS value with either of the following methods. • When changing the value after stopping LVI <1> Stop LVI (LVION = 0). <2> Change the LVIS register. <3> Set to the mode used as an interrupt (LVIMD = 0). <4>...
Page 657: Operation Of Low-Voltage Detector
CHAPTER 21 LOW-VOLTAGE DETECTOR 21.4 Operation of Low-Voltage Detector The low-voltage detector can be used in the following two modes. (1) Used as reset (LVIMD = 1) • If LVISEL = 0, compares the supply voltage (V ) and detection voltage (V ), generates an internal reset ≥...
Page 658: When Used As Reset
CHAPTER 21 LOW-VOLTAGE DETECTOR 21.4.1 When used as reset (1) When detecting level of supply voltage (V (a) When LVI default start function stopped is set (option byte: LVIOFF = 1) • When starting operation <1> Mask the LVI interrupt (LVIMK = 1). <2>...
Page 659 CHAPTER 21 LOW-VOLTAGE DETECTOR Figure 21-5. Timing of Low-Voltage Detector Internal Reset Signal Generation (Bit: LVISEL = 0, Option Byte: LVIOFF = 1) Set LVI to be used for reset Supply voltage (V = 1.59 V (TYP.) Time LVIMK flag Note 1 (set by software) <1>...
Page 660 CHAPTER 21 LOW-VOLTAGE DETECTOR (b) When LVI default start function enabled is set (option byte: LVIOFF = 0) • When starting operation Start in the following initial setting state. Set bit 7 (LVION) of LVIM to 1 (enables LVI operation) •...
Page 661 CHAPTER 21 LOW-VOLTAGE DETECTOR Figure 21-6. Timing of Low-Voltage Detector Internal Reset Signal Generation (Bit: LVISEL = 0, Option Byte: LVIOFF = 0) Interrupt operation mode is set by setting Change LVI detection Reset mode is set by LVIMD to 0 (LVI interrupt is masked) voltage (VLVI) setting LVIMD to 1 Supply voltage (V...
Page 662 CHAPTER 21 LOW-VOLTAGE DETECTOR (2) When detecting level of input voltage from external input pin (EXLVI) • When starting operation <1> Mask the LVI interrupt (LVIMK = 1). <2> Set bit 2 (LVISEL) of the low-voltage detection register (LVIM) to 1 (detects level of input voltage from external input pin (EXLVI)).
Page 663 CHAPTER 21 LOW-VOLTAGE DETECTOR Figure 21-7. Timing of Low-Voltage Detector Internal Reset Signal Generation (Bit: LVISEL = 1) Set LVI to be used for reset Input voltage from external input pin (EXLVI) EXLVI Time Note 1 LVIMK flag <1> (set by software) LVISEL flag Not cleared Not cleared...
Page 664: When Used As Interrupt
CHAPTER 21 LOW-VOLTAGE DETECTOR 21.4.2 When used as interrupt (1) When detecting level of supply voltage (V (a) When LVI default start function stopped is set (option byte: LVIOFF = 1) • When starting operation <1> Mask the LVI interrupt (LVIMK = 1). <2>...
Page 665 CHAPTER 21 LOW-VOLTAGE DETECTOR Figure 21-8. Timing of Low-Voltage Detector Interrupt Signal Generation (Bit: LVISEL = 0, Option Byte: LVIOFF = 1) Supply voltage (V = 1.59 V (TYP.) Time Note 3 Note 3 LVIMK flag (set by software) <1> <8>...
Page 666 CHAPTER 21 LOW-VOLTAGE DETECTOR (b) When LVI default start function enabled is set (option byte: LVIOFF = 0) • When starting operation <1> Start in the following initial setting state. Set bit 7 (LVION) of LVIM to 1 (enables LVI operation) •...
Page 667 CHAPTER 21 LOW-VOLTAGE DETECTOR Figure 21-9. Timing of Low-Voltage Detector Interrupt Signal Generation (Bit: LVISEL = 0, Option Byte: LVIOFF = 0) Change LVI detection Mask LVI interrupts Cancelling the LVI interrupt voltage (V (LVIMK = 1) mask (LVIMK = 0) Supply voltage (V value after a change = 2.07 V (TYP.)
Page 668 CHAPTER 21 LOW-VOLTAGE DETECTOR (2) When detecting level of input voltage from external input pin (EXLVI) • When starting operation <1> Mask the LVI interrupt (LVIMK = 1). <2> Set bit 2 (LVISEL) of the low-voltage detection register (LVIM) to 1 (detects level of input voltage from external input pin (EXLVI)).
Page 669 CHAPTER 21 LOW-VOLTAGE DETECTOR Figure 21-10. Timing of Low-Voltage Detector Interrupt Signal Generation (Bit: LVISEL = 1) Input voltage from external input pin (EXLVI) EXLVI Time Note 3 Note 3 LVIMK flag (set by software) <1> Note 1 <7> Cleared by software LVISEL flag (set by software) <2>...
Page 670: Cautions For Low-Voltage Detector
CHAPTER 21 LOW-VOLTAGE DETECTOR 21.5 Cautions for Low-Voltage Detector (1) Measures method when supply voltage (V ) frequently fluctuates in the vicinity of the LVI detection voltage (V In a system where the supply voltage (V ) fluctuates for a certain period in the vicinity of the LVI detection voltage (V ), the operation is as follows depending on how the low-voltage detector is used.
Page 671 CHAPTER 21 LOW-VOLTAGE DETECTOR Figure 21-11. Example of Software Processing After Reset Release (1/2) • If supply voltage fluctuation is 50 ms or less in vicinity of LVI detection voltage Reset Note Check the reset source, etc. Initialization processing <1> LVI reset ;...
Page 672 CHAPTER 21 LOW-VOLTAGE DETECTOR Figure 21-11. Example of Software Processing After Reset Release (2/2) • Checking reset source Check reset source TRAP of RESF register = 1? Reset processing by Note illegal instruction execution WDRF of RESF register = 1? Reset processing by watchdog timer LVIRF of RESF...
Page 673 CHAPTER 21 LOW-VOLTAGE DETECTOR Operation example 2: When used as interrupt Interrupt requests may be generated frequently. Take the following action. <Action> ) ≥ detection voltage (V Confirm that “supply voltage (V )” when detecting the falling edge of V , or “supply voltage (V ) <...
Page 674: Chapter 22 Regulator
CHAPTER 22 REGULATOR 22.1 Regulator Overview The 78K0R/KF3 contains a circuit for operating the device with a constant voltage. At this time, in order to stabilize μ the regulator output voltage, connect the REGC pin to V via a capacitor (0.47 to 1 F).
Page 675 CHAPTER 22 REGULATOR Table 22-1. Regulator Output Voltage Conditions Mode Output Voltage Condition Low consumption 1.8 V During system reset current mode In STOP mode (except during OCD mode) When both the high-speed system clock (f ) and the high-speed internal oscillation clock (f ) are stopped during CPU operation with the subsystem clock When both the high-speed system clock (f...
Page 676: Chapter 23 Option Byte
CHAPTER 23 OPTION BYTE 23.1 Functions of Option Bytes Addresses 000C0H to 000C3H of the flash memory of the 78K0R/KF3 form an option byte area. Option bytes consist of user option byte (000C0H to 000C2H) and on-chip debug option byte (000C3H).
Page 677: On-Chip Debug Option Byte (000C3H/ 010C3H)
CHAPTER 23 OPTION BYTE 23.1.2 On-chip debug option byte (000C3H/ 010C3H) Control of on-chip debug operation • On-chip debug operation is disabled or enabled. Handling of data of flash memory in case of failure in on-chip debug security ID authentication •...
Page 678 CHAPTER 23 OPTION BYTE Figure 23-1. Format of User Option Byte (000C0H/010C0H) (2/2) Note 1 Address: 000C0H/010C0H WDTINIT WINDOW1 WINDOW0 WDTON WDCS2 WDCS1 WDCS0 WDSTBYON WDSTBYON Operation control of watchdog timer counter (HALT/STOP mode) Note 2 Counter operation stopped in HALT/STOP mode Counter operation enabled in HALT/STOP mode Notes 1.
Page 679: Format Of On-Chip Debug Option Byte
CHAPTER 23 OPTION BYTE Figure 23-3. Format of Option Byte (000C2H/010C2H) Note Address: 000C2H/010C2H Note Be sure to set FFH to 000C2H, as these addresses are reserved areas. Also set FFH to 010C2H when the boot swap operation is used because 000C2H is replaced by 010C2H. 23.3 Format of On-chip Debug Option Byte The format of on-chip debug option byte is shown below.
Page 680: Setting Of Option Byte
CHAPTER 23 OPTION BYTE 23.4 Setting of Option Byte The user option byte and on-chip debug option byte can be set using the RA78K0R or PM+ linker option, in addition to describing to the source. When doing so, the contents set by using the linker option take precedence, even if descriptions exist in the source, as mentioned below.
Page 681: Chapter 24 Flash Memory
Data can be written to the flash memory on-board or off-board, by using a dedicated flash memory programmer. (1) On-board programming The contents of the flash memory can be rewritten after the 78K0R/KF3 has been mounted on the target system. The connectors that connect the dedicated flash memory programmer must be mounted on the target system.
Page 682 CHAPTER 24 FLASH MEMORY Table 24-1. Wiring Between 78K0R/KF3 and Dedicated Flash Memory Programmer Pin Configuration of Dedicated Flash Memory Programmer Pin Name Pin No. Signal Name Pin Function Notes 1, 2 SI/RxD Input Receive signal TOOL0/P40 Note 2 SO/TxD...
Page 683 CHAPTER 24 FLASH MEMORY Examples of the recommended connection when using the adapter for flash memory writing are shown below. Figure 24-1. Example of Wiring Adapter for Flash Memory Writing (GC/GK Package) (2.7 to 5.5 V) 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 VDD2 Notes 1, 2...
Page 684: Programming Environment
CHAPTER 24 FLASH MEMORY 24.2 Programming Environment The environment required for writing a program to the flash memory of the 78K0R/KF3 is illustrated below. Figure 24-2. Environment for Writing Program to Flash Memory PG-FP5, FL-PR5 QB-MINI2 FLMD0 PG-FP4, FL-PR4 RS-232C...
Page 685: Connection Of Pins On Board
CHAPTER 24 FLASH MEMORY Table 24-2. Pin Connection Dedicated Flash Memory Programmer 78K0R/KF3 Connection Signal Name Pin Function Pin Name FLMD0 Output Mode signal FLMD0 voltage generation/power monitoring , EV , AV , AV REF0 REF1 − Ground , EV , AV −...
Page 686: Tool0 Pin
TOOL0 pin before reset is released (pulling down this pin is prohibited). Remark The SAU and IIC0 pins are not used for communication between the 78K0R/KF3 and dedicated flash memory programmer, because single-line UART is used. 24.4.3 RESET pin Signal conflict will occur if the reset signal of the dedicated flash memory programmer is connected to the RESET pin that is connected to the reset signal generator on the board.
Page 687: Port Pins
CHAPTER 24 FLASH MEMORY 24.4.4 Port pins When the flash memory programming mode is set, all the pins not used for flash memory programming enter the same status as that immediately after reset. If external devices connected to the ports do not recognize the port status immediately after reset, the port pin must be connected to V or V via a resistor.
Page 688: Programming Method
24.6.2 Flash memory programming mode To rewrite the contents of the flash memory by using the dedicated flash memory programmer, set the 78K0R/KF3 in the flash memory programming mode. To set the mode, set the FLMD0 pin and TOOL0 pin to V and clear the reset signal.
Page 689: Selecting Communication Mode
The 78K0R/KF3 communicates with the dedicated flash memory programmer by using commands. The signals sent from the flash memory programmer to the 78K0R/KF3 are called commands, and the signals sent from the 78K0R/KF3 to the dedicated flash memory programmer are called response.
Page 690 Baud Rate Set Sets baud rate when UART communication mode is selected. The 78K0R/KF3 return a response for the command issued by the dedicated flash memory programmer. The response names sent from the 78K0R/KF3 are listed below. Table 24-6. Response Names...
Page 691: Security Settings
CHAPTER 24 FLASH MEMORY 24.7 Security Settings The 78K0R/KF3 supports a security function that prohibits rewriting the user program written to the internal flash memory, so that the program cannot be changed by an unauthorized person. The operations shown below can be performed using the Security Set command. The security setting is valid when the programming mode is set next.
Page 692 CHAPTER 24 FLASH MEMORY Table 24-7. Relationship Between Enabling Security Function and Command (1) During on-board/off-board programming Valid Security Executed Command Batch Erase (Chip Erase) Block Erase Write Note Prohibition of batch erase (chip erase) Cannot be erased in batch Blocks cannot be Can be performed erased.
Page 693: Processing Time Of Each Command When Using Pg-Fp4 Or Pg-Fp5 (Reference Values)
CHAPTER 24 FLASH MEMORY 24.8 Processing Time of Each Command When Using PG-FP4 or PG-FP5 (Reference Values) The processing time of each command (reference values) when using PG-FP4 or PG-FP5 as the dedicated flash memory programmer is shown below. Table 24-9. Processing Time of Each Command When Using PG-FP4 (Reference Values) PG-FP4 Port: UART Command...
Page 694: Flash Memory Programming By Self-Programming
24.9 Flash Memory Programming by Self-Programming The 78K0R/KF3 supports a self-programming function that can be used to rewrite the flash memory via a user program. Because this function allows a user application to rewrite the flash memory by using the 78K0R/KF3 self- programming library, it can be used to upgrade the program in the field.
Page 695 CHAPTER 24 FLASH MEMORY The following figure illustrates a flow of rewriting the flash memory by using a self programming library. Figure 24-10. Flow of Self Programming (Rewriting Flash Memory) Start of self programming FlashStart Setting operating environment FlashEnv CheckFLMD FlashBlockBlankCheck Normal completion? FlashBlockErase...
Page 696: Boot Swap Function
1 in advance. When the program has been correctly written to boot cluster 1, swap this boot cluster 1 and boot cluster 0 by using the set information function of the firmware of the 78K0R/KF3, so that boot cluster 1 is used as a boot area.
Page 697 CHAPTER 24 FLASH MEMORY Figure 24-12. Example of Executing Boot Swapping Block number Erasing block 2 Erasing block 3 Program Program Boot cluster 1 Program 0 1 0 0 0 H Boot program Boot program Boot program Boot cluster 0 Boot program Boot program Boot program...
Page 698: Flash Shield Window Function
CHAPTER 24 FLASH MEMORY 24.9.2 Flash shield window function The flash shield window function is provided as one of the security functions for self programming. It disables writing to and erasing areas outside the range specified as a window only during self programming. The window range can be set by specifying the start and end blocks.
Page 699: Chapter 25 On-Chip Debug Function
(QB-MINI2). Caution The 78K0R/KF3 has an on-chip debug function, which is provided for development and evaluation. Do not use the on-chip debug function in products designated for mass production, because the guaranteed number of rewritable times of the flash memory may be exceeded when this function is used, and product reliability therefore cannot be guaranteed.
Page 700: On-Chip Debug Security Id
25.2 On-Chip Debug Security ID The 78K0R/KF3 has an on-chip debug operation control bit in the flash memory at 000C3H (see CHAPTER 23 OPTION BYTE) and an on-chip debug security ID setting area at 000C4H to 000CDH, to prevent third parties from reading memory content.
Page 701 CHAPTER 25 ON-CHIP DEBUG FUNCTION Figure 25-2. Memory Spaces Where Debug Monitor Programs Are Allocated Internal ROM Internal RAM Note 1 (1 KB) Stack area for debugging Internal RAM Note 3 (6 bytes) area 0 2 0 0 0 H Use prohibited 0 1 0 D 8 H Debug monitor area...
Page 702: Chapter 26 Bcd Correction Circuit
CHAPTER 26 BCD CORRECTION CIRCUIT 26.1 BCD Correction Circuit Function The result of addition/subtraction of the BCD (binary-coded decimal) code and BCD code can be obtained as BCD code with this circuit. The decimal correction operation result is obtained by performing addition/subtraction having the A register as the operand and then adding/ subtracting the BCDADJ register.
Page 703: Bcd Correction Circuit Operation
CHAPTER 26 BCD CORRECTION CIRCUIT 26.3 BCD Correction Circuit Operation The basic operation of the BCD correction circuit is as follows. (1) Addition: Calculating the result of adding a BCD code value and another BCD code value by using a BCD code value <1>...
Page 704 CHAPTER 26 BCD CORRECTION CIRCUIT (2) Subtraction: Calculating the result of subtracting a BCD code value from another BCD code value by using a BCD code value <1> The BCD code value from which subtraction is performed is stored in the A register. <2>...
Page 705: Chapter 27 Instruction Set
CHAPTER 27 INSTRUCTION SET This chapter lists the instructions in the 78K0R microcontroller instruction set. For details of each operation and operation code, refer to the separate document 78K0R Microcontrollers Instructions User’s Manual (U17792E). Remark The shaded parts of the tables in Table 27-5 Operation List indicate the operation or instruction format that is newly added for the 78K0R microcontrollers.
Page 706: Conventions Used In Operation List
CHAPTER 27 INSTRUCTION SET 27.1 Conventions Used in Operation List 27.1.1 Operand identifiers and specification methods Operands are described in the “Operand” column of each instruction in accordance with the description method of the instruction operand identifier (refer to the assembler specifications for details). When there are two or more description methods, select one of them.
Page 707: Description Of Operation Column
CHAPTER 27 INSTRUCTION SET 27.1.2 Description of operation column The operation when the instruction is executed is shown in the “Operation” column using the following symbols. Table 27-2. Symbols in “Operation” Column Symbol Function A register; 8-bit accumulator X register B register C register D register...
Page 708: Description Of Flag Operation Column
CHAPTER 27 INSTRUCTION SET 27.1.3 Description of flag operation column The change of the flag value when the instruction is executed is shown in the “Flag” column using the following symbols. Table 27-3. Symbols in “Flag” Column Symbol Change of Flag Value (Blank) Unchanged Cleared to 0...
Page 709: Operation List
CHAPTER 27 INSTRUCTION SET 27.2 Operation List Table 27-5. Operation List (1/17) Instruction Mnemonic Operands Bytes Clocks Operation Flag Group Note 1 Note 2 Z AC CY r ← byte − 8-bit data r, #byte transfer − (saddr) ← byte saddr, #byte −...
Page 710 CHAPTER 27 INSTRUCTION SET Table 27-5. Operation List (2/17) Instruction Mnemonic Operands Bytes Clocks Operation Flag Group Note 1 Note 2 Z AC CY A ← (HL + byte) 8-bit data A, [HL + byte] transfer − (HL + byte) ← A [HL + byte], A A ←...
Page 711 CHAPTER 27 INSTRUCTION SET Table 27-5. Operation List (3/17) Instruction Mnemonic Operands Bytes Clocks Operation Flag Group Note 1 Note 2 Z AC CY A ← (ES, HL) 8-bit data A, ES:[HL] transfer − (ES, HL) ← A ES:[HL], A −...
Page 712 CHAPTER 27 INSTRUCTION SET Table 27-5. Operation List (4/17) Instruction Mnemonic Operands Bytes Clocks Operation Flag Group Note 1 Note 2 Z AC CY − A ←→ (ES, addr16) 8-bit data A, ES:!addr16 transfer − A ←→ (ES, DE) A, ES:[DE] −...
Page 713 CHAPTER 27 INSTRUCTION SET Table 27-5. Operation List (5/17) Instruction Mnemonic Operands Bytes Clocks Operation Flag Group Note 1 Note 2 Z AC CY AX ← (addr16) 16-bit MOVW AX, !addr16 data − (addr16) ← AX !addr16, AX transfer AX ← (DE) AX, [DE] −...
Page 714 CHAPTER 27 INSTRUCTION SET Table 27-5. Operation List (6/17) Instruction Mnemonic Operands Bytes Clocks Operation Flag Group Note 1 Note 2 Z AC CY AX ← ((ES, HL) + byte) 16-bit MOVW AX, ES:[HL + byte] data − ((ES, HL) + byte) ← AX ES:[HL + byte], AX transfer AX ←...
Page 715 CHAPTER 27 INSTRUCTION SET Table 27-5. Operation List (7/17) Instruction Mnemonic Operands Bytes Clocks Operation Flag Group Note 1 Note 2 Z AC CY − A, CY ← A + byte + CY × × × 8-bit ADDC A, #byte operation −...
Page 716 CHAPTER 27 INSTRUCTION SET Table 27-5. Operation List (8/17) Instruction Mnemonic Operands Bytes Clocks Operation Flag Group Note 1 Note 2 Z AC CY − A, CY ← A − byte − CY × × × 8-bit SUBC A, #byte operation −...
Page 717 CHAPTER 27 INSTRUCTION SET Table 27-5. Operation List (9/17) Instruction Mnemonic Operands Bytes Clocks Operation Flag Group Note 1 Note 2 Z AC CY − A ← A ∨ byte × 8-bit A, #byte operation − (saddr) ← (saddr) ∨ byte ×...
Page 718 CHAPTER 27 INSTRUCTION SET Table 27-5. Operation List (10/17) Instruction Mnemonic Operands Bytes Clocks Operation Flag Group Note 1 Note 2 Z AC CY − A − byte × × × 8-bit A, #byte operation − (saddr) − byte × ×...
Page 719 CHAPTER 27 INSTRUCTION SET Table 27-5. Operation List (11/17) Instruction Mnemonic Operands Bytes Clocks Operation Flag Group Note 1 Note 2 Z AC CY − AX, CY ← AX + word × × × 16-bit ADDW AX, #word operation − AX, CY ←...
Page 720 CHAPTER 27 INSTRUCTION SET Table 27-5. Operation List (12/17) Instruction Mnemonic Operands Bytes Clocks Operation Flag Group Note 1 Note 2 Z AC CY − r ← r + 1 × × Increment/ decrement − (saddr) ← (saddr) + 1 ×...
Page 721 CHAPTER 27 INSTRUCTION SET Table 27-5. Operation List (13/17) Instruction Mnemonic Operands Bytes Clocks Operation Flag Group Note 1 Note 2 Z AC CY − ← A ← A ) × 1 × Rotate A, 1 (CY, A m−1 − ←...
Page 722 CHAPTER 27 INSTRUCTION SET Table 27-5. Operation List (14/17) Instruction Mnemonic Operands Bytes Clocks Operation Flag Group Note 1 Note 2 Z AC CY − CY ← CY ∨ (saddr).bit × XOR1 CY, saddr.bit manipulate − CY ← CY ∨ sfr.bit ×...
Page 723 CHAPTER 27 INSTRUCTION SET Table 27-5. Operation List (15/17) Instruction Mnemonic Operands Bytes Clocks Operation Flag Group Note 1 Note 2 Z AC CY − (SP − 2) ← (PC + 2) , (SP − 3) ← (PC + 2) Call/ CALL (SP −...
Page 724 CHAPTER 27 INSTRUCTION SET Table 27-5. Operation List (16/17) Instruction Mnemonic Operands Bytes Clocks Operation Flag Group Note 1 Note 2 Z AC CY − (SP − 1) ← PSW, (SP − 2) ← 00H, Stack PUSH SP ← SP − 2 manipulate (SP −...
Page 725 CHAPTER 27 INSTRUCTION SET Table 27-5. Operation List (17/17) Instruction Mnemonic Operands Bytes Clocks Operation Flag Group Note 1 Note 2 Z AC CY − PC ← PC + 4 + jdisp8 if (saddr).bit = 0 Note 3 Condition saddr.bit, $addr20 al branch −...
Page 726: Chapter 28 Electrical Specifications (Standard Products)
PD78F1152A, 78F1153A, 78F1154A, 78F1155A, 78F1156A Caution The 78K0R/KF3 has an on-chip debug function, which is provided for development and evaluation. Do not use the on-chip debug function in products designated for mass production, because the guaranteed number of rewritable times of the flash memory may be exceeded when this function is used, and product reliability therefore cannot be guaranteed.
Page 727 CHAPTER 28 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS) Standard Products Absolute Maximum Ratings (T = 25°C) (2/2) Parameter Symbols Conditions Ratings Unit −10 Output current, high Per pin P00 to P06, P10 to P17, P30, P31, P40 to P47, P50 to P55, P64 to P67, P70 to P77, P90, P120, P130, P140 to P145 −25...
Page 728 CHAPTER 28 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS) Standard Products X1 Oscillator Characteristics <R> = −40 to +85°C, 1.8 V ≤ V ≤ 5.5 V, V = EV = EV = AV = 0 V) Recommended Resonator Parameter Conditions MIN. TYP. MAX. Unit Circuit 2.7 V ≤...
Page 729 CHAPTER 28 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS) Standard Products Internal Oscillator Characteristics = −40 to +85°C, 1.8 V ≤ V ≤ 5.5 V, V = EV = EV = AV = 0 V) Oscillators Parameters Conditions MIN. TYP. MAX. Unit 2.7 V ≤ V ≤...
Page 730 CHAPTER 28 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS) Standard Products <R> XT1 Oscillator Characteristics = −40 to +85°C, 1.8 V ≤ V ≤ 5.5 V, V = EV = EV = AV = 0 V) Recommended Resonator Items Conditions MIN. TYP. MAX. Unit Circuit Crystal resonator...
Page 731 When doing so, check the conditions for using the AMPH bit, RMC register, and whether to enter or exit the STOP mode. The oscillation voltage and oscillation frequency only indicate the oscillator characteristic. Use the 78K0R/KF3 so that the internal operation conditions are within the specifications of the DC and AC characteristics. User’s Manual U17893EJ8V0UD...
Page 732 When doing so, check the conditions for using the AMPH bit, RMC register, and whether to enter or exit the STOP mode. The oscillation voltage and oscillation frequency only indicate the oscillator characteristic. Use the 78K0R/KF3 so that the internal operation conditions are within the specifications of the DC and AC characteristics. User’s Manual U17893EJ8V0UD...
Page 733 When doing so, check the conditions for using the AMPH bit, RMC register, and whether to enter or exit the STOP mode. The oscillation voltage and oscillation frequency only indicate the oscillator characteristic. Use the 78K0R/KF3 so that the internal operation conditions are within the specifications of the DC and AC characteristics. User’s Manual U17893EJ8V0UD...
Page 734 When doing so, check the conditions for using the AMPH bit, RMC register, and whether to enter or exit the STOP mode. The oscillation voltage and oscillation frequency only indicate the oscillator characteristic. Use the 78K0R/KF3 so that the internal operation conditions are within the specifications of the DC and AC characteristics. User’s Manual U17893EJ8V0UD...
Page 735 When doing so, check the conditions for using the RMC register, and whether to enter or exit the STOP mode. The oscillation voltage and oscillation frequency only indicate the oscillator characteristic. Use the 78K0R/KF3 so that the internal operation conditions are within the specifications of the DC and AC characteristics. = −20 to +70°C)
Page 736 CHAPTER 28 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS) Standard Products DC Characteristics (1/12) = −40 to +85°C, 1.8 V ≤ V ≤ 5.5 V, 1.8 V ≤ AV ≤ V , 1.8 V ≤ AV ≤ V = EV = EV REF0 REF1 = AV = 0 V)
Page 737 CHAPTER 28 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS) Standard Products DC Characteristics (2/12) = −40 to +85°C, 1.8 V ≤ V ≤ 5.5 V, 1.8 V ≤ AV ≤ V , 1.8 V ≤ AV ≤ V = EV = EV REF0 REF1 = AV = 0 V)
Page 738 CHAPTER 28 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS) Standard Products DC Characteristics (3/12) = −40 to +85°C, 1.8 V ≤ V ≤ 5.5 V, 1.8 V ≤ AV ≤ V , 1.8 V ≤ AV ≤ V = EV = EV REF0 REF1 = AV = 0 V)
Page 739 CHAPTER 28 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS) Standard Products DC Characteristics (4/12) = −40 to +85°C, 1.8 V ≤ V ≤ 5.5 V, 1.8 V ≤ AV ≤ V , 1.8 V ≤ AV ≤ V = EV = EV REF0 REF1 = AV = 0 V)
Page 740 CHAPTER 28 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS) Standard Products DC Characteristics (5/12) = −40 to +85°C, 1.8 V ≤ V ≤ 5.5 V, 1.8 V ≤ AV ≤ V , 1.8 V ≤ AV ≤ V = EV = EV REF0 REF1 = AV = 0 V)
Page 741 CHAPTER 28 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS) Standard Products DC Characteristics (6/12) = −40 to +85°C, 1.8 V ≤ V ≤ 5.5 V, 1.8 V ≤ AV ≤ V , 1.8 V ≤ AV ≤ V = EV = EV REF0 REF1 = AV = 0 V)
Page 742 It is recommended to leave the FLMD0 pin open. If the pin is required to be pulled down externally, set to 100 kΩ or more. FLMD0 78K0R/KF3 FLMD0 pin FLMD0 Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins.
Page 743 CHAPTER 28 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS) Standard Products DC Characteristics (8/12) = −40 to +85°C, 1.8 V ≤ V ≤ 5.5 V, 1.8 V ≤ AV ≤ V , 1.8 V ≤ AV ≤ V = EV = EV REF0 REF1 = AV = 0 V)
Page 744 CHAPTER 28 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS) Standard Products DC Characteristics (9/12) = −40 to +85°C, 1.8 V ≤ V ≤ 5.5 V, 1.8 V ≤ AV ≤ V , 1.8 V ≤ AV ≤ V = EV = EV REF0 REF1 = AV = 0 V)
Page 745 CHAPTER 28 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS) Standard Products DC Characteristics (10/12) = −40 to +85°C, 1.8 V ≤ V ≤ 5.5 V, 1.8 V ≤ AV ≤ V , 1.8 V ≤ AV ≤ V = EV = EV REF0 REF1 = AV = 0 V)
Page 746 CHAPTER 28 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS) Standard Products DC Characteristics (11/12) = −40 to +85°C, 1.8 V ≤ V ≤ 5.5 V, 1.8 V ≤ AV ≤ V , 1.8 V ≤ AV ≤ V = EV = EV REF0 REF1 = AV = 0 V)
Page 747 I and I when the D/A converter operates in an operation mode or the HALT mode. 6. Current flowing only to the LVI circuit. The current value of the 78K0R/KF3 is the sum of I or I and I when the LVI circuit operates in the Operating, HALT or STOP mode.
Page 748 CHAPTER 28 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS) Standard Products AC Characteristics (1) Basic operation (1/6) = −40 to +85°C, 1.8 V ≤ V ≤ 5.5 V, 1.8 V ≤ AV ≤ V , 1.8 V ≤ AV ≤ V = EV REF0 REF1 = AV...
Page 749 CHAPTER 28 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS) Standard Products (1) Basic operation (2/6) Minimum instruction execution time during main system clock operation (FSEL = 0, RMC = 00H) Guaranteed range of main system clock operation (FSEL = 0, RMC = 00H) The range enclosed in dotted lines applies when the internal high-speed oscillator is selected.
Page 750 CHAPTER 28 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS) Standard Products (1) Basic operation (3/6) Minimum instruction execution time during main system clock operation (FSEL = 1, RMC = 00H) Guaranteed range of main system clock operation (FSEL = 1, RMC = 00H) The range enclosed in dotted lines applies when the internal high-speed oscillator is selected.
Page 751 CHAPTER 28 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS) Standard Products (1) Basic operation (4/6) Minimum instruction execution time during main system clock operation (FSEL = 0, RMC = 5AH) Guaranteed range of main system clock operation (FSEL = 0, RMC = 5AH) The range enclosed in dotted lines applies when the internal high-speed oscillator is selected.
Page 752 CHAPTER 28 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS) Standard Products (1) Basic operation (5/6) Minimum instruction execution time during self programming mode (RMC = 00H) Guaranteed range of self programming mode (RMC = 00H) The range enclosed in dotted lines applies when the internal high-speed oscillator is selected.
Page 753 CHAPTER 28 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS) Standard Products (1) Basic operation (6/6) AC Timing Test Points Test points External Main System Clock Timing 0.8V (MIN.) EXCLK 0.2V (MAX.) TI Timing TI00 to TI07 Interrupt Request Input Timing INTIL INTH INTP0 to INTP11 Key Interrupt Input Timing KR0 to KR7 RESET Input Timing...
Page 754 Unit Transfer rate = 20 MHz, f Mbps UART mode connection diagram (during communication at same potential) TxDq 78K0R/KF3 User's device RxDq UART mode bit width (during communication at same potential) (reference) 1/Transfer rate High-/Low-bit width Baud rate error tolerance...
Page 755 CHAPTER 28 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS) Standard Products (2) Serial interface: Serial array unit (2/18) = −40 to +85°C, 1.8 V ≤ V ≤ 5.5 V, V = EV = EV = AV = 0 V) <R> (b) During communication at same potential (CSI mode) (master mode, SCKp... internal clock output) Parameter Symbol Conditions...
Page 756 CHAPTER 28 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS) Standard Products (2) Serial interface: Serial array unit (3/18) = −40 to +85°C, 1.8 V ≤ V ≤ 5.5 V, V = EV = EV = AV = 0 V) (c) During communication at same potential (CSI mode) (slave mode, SCKp... external clock input) <R>...
Page 757 (2) Serial interface: Serial array unit (4/18) CSI mode connection diagram (during communication at same potential) SCKp 78K0R/KF3 User's device CSI mode serial transfer timing (during communication at same potential) (When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1.)
Page 758 CHAPTER 28 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS) Standard Products (2) Serial interface: Serial array unit (5/18) (d) During communication at same potential (simplified I C mode) μ • Conventional-specification products ( PD78F115x) = −40 to +85°C, 2.7 V ≤ V ≤ 5.5 V, V = EV = EV = AV...
Page 759 CHAPTER 28 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS) Standard Products (2) Serial interface: Serial array unit (6/18) Simplified I C mode mode connection diagram (during communication at same potential) SDAr 78K0R/KF3 User's device SCLr Simplified I C mode serial transfer timing (during communication at same potential) HIGH...
Page 760 CHAPTER 28 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS) Standard Products (2) Serial interface: Serial array unit (7/18) = −40 to +85°C, 2.7 V ≤ V ≤ 5.5 V, V = EV = EV = AV = 0 V) (e) During Communication at different potential (2.5 V, 3 V) (UART mode) (dedicated baud rate generator output) (1/2) Parameter Symbol...
Page 761 CHAPTER 28 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS) Standard Products (2) Serial interface: Serial array unit (8/18) = −40 to +85°C, 2.7 V ≤ V ≤ 5.5 V, V = EV = EV = AV = 0 V) (e) Communication at different potential (2.5 V, 3 V) (UART mode) (dedicated baud rate generator output) (2/2) Parameter Symbol Conditions...
Page 762 CHAPTER 28 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS) Standard Products (2) Serial interface: Serial array unit (9/18) Remarks 1. [Ω]:Communication line (TxDq) pull-up resistance, [F]: Communication line (TxDq) load capacitance, V [V]: Communication line voltage q: UART number (q = 1, 2), g: PIM and POM number (g = 0, 14) : Serial array unit operation clock frequency (Operation clock to be set by the CKSmn bit of the SMRmn register.
Page 763 CHAPTER 28 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS) Standard Products (2) Serial interface: Serial array unit (10/18) UART mode connection diagram (During communication at different potential) TxDq 78K0R/KF3 User's device RxDq UART mode bit width (During communication at different potential) 1/Transfer rate...
Page 764 CHAPTER 28 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS) Standard Products (2) Serial interface: Serial array unit (11/18) = −40 to +85°C, 2.7 V ≤ V ≤ 5.5 V, V = EV = EV = AV = 0 V) <R> (f) During Communication at different potential (2.5 V, 3 V) (CSI mode) (master mode, SCKp... internal clock output) (1/2) Parameter Symbol...
Page 765 When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. CSI mode connection diagram (during communication at different potential) <Master> SCKp 78K0R/KF3 User's device Caution Select the TTL input buffer for SIp and the N-ch open drain output (V tolerance) mode for SOp and SCKp by using the PIMg and POMg registers.
Page 766 CHAPTER 28 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS) Standard Products (2) Serial interface: Serial array unit (13/18) CSI mode serial transfer timing (during communication at different potential) (When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1.) KCY1 SCKp SIK1...
Page 767 “from SCKp↑” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. CSI mode connection diagram (during communication at different potential) <Slave> SCKp 78K0R/KF3 User's device (Caution and Remark are given on the next page.) User’s Manual U17893EJ8V0UD...
Page 768 CHAPTER 28 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS) Standard Products (2) Serial interface: Serial array unit (15/18) Caution Select the TTL input buffer for SIp and SCKp and the N-ch open drain output (V tolerance) mode for SOp by using the PIMg and POMg registers. Remarks 1.
Page 769 CHAPTER 28 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS) Standard Products (2) Serial interface: Serial array unit (16/18) CSI mode serial transfer timing (during communication at different potential) (When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1.) KCY2 SCKp SIK2...
Page 770 CHAPTER 28 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS) Standard Products (2) Serial interface: Serial array unit (17/18) = −40 to +85°C, 2.7 V ≤ V ≤ 5.5 V, V = EV = EV = AV = 0 V) (h) During Communication at different potential (2.5 V, 3 V) (simplified I C mode) Parameter Symbol...
Page 771 CHAPTER 28 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS) Standard Products (2) Serial interface: Serial array unit (18/18) Simplified I C mode connection diagram (during communication at different potential) SDAr 78K0R/KF3 User's device SCLr Simplified I C mode serial transfer timing (during communication at different potential) HIGH...
Page 772 CHAPTER 28 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS) Standard Products (3) Serial interface: IIC0 = −40 to +85°C, 1.8 V ≤ V ≤ 5.5 V, V = EV = EV = AV = 0 V) (a) IIC0 Parameter Symbol Conditions Standard Mode Fast Mode Unit MIN.
Page 773 CHAPTER 28 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS) Standard Products (4) Serial interface: On-chip debug (UART) = −40 to +85°C, 1.8 V ≤ V ≤ 5.5 V, V = EV = EV = AV = 0 V) (a) On-chip debug (UART) Parameter Symbol Conditions MIN.
Page 774 CHAPTER 28 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS) Standard Products A/D Converter Characteristics (1/2) = −40 to +85°C, 2.3 V ≤ V ≤ 5.5 V, 2.3 V ≤ AV ≤ V , 1.8 V ≤ AV ≤ V = EV = EV = AV = 0 V) REF0...
Page 775 CHAPTER 28 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS) Standard Products A/D Converter Characteristics (2/2) = −40 to +85°C, 2.3 V ≤ V ≤ 5.5 V, 2.3 V ≤ AV ≤ V , 1.8 V ≤ AV ≤ V = EV = EV = AV = 0 V) REF0...
Page 776 CHAPTER 28 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS) Standard Products μ Temperature Sensor (Expanded-Specification Products ( PD78F115xA) Only) = −40 to +85°C, 2.7 V ≤ V ≤ 5.5 V, 2.7 V ≤ AV ≤ V = EV = EV = 0 V) REF0 Parameter Symbol...
Page 777 CHAPTER 28 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS) Standard Products = −40 to +85°C, V POC Circuit Characteristics (T = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit Detection voltage 1.59 1.68 POC0 : 0 V → V Power supply voltage rise Change inclination of V V/ms POC0...
Page 778 CHAPTER 28 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS) Standard Products = −40 to +85°C, V ≤ V ≤ 5.5 V, V LVI Circuit Characteristics (T = EV = EV = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit Detection Supply voltage level 4.12 4.22 4.32...
Page 779 CHAPTER 28 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS) Standard Products = −40 to +85°C) Data Memory STOP Mode Low Supply Voltage Data Retention Characteristics (T Parameter Symbol Conditions MIN. TYP. MAX. Unit Note Data retention supply voltage DDDR Note The value depends on the POC detection voltage. When the voltage drops, the data is retained until a POC reset is effected, but data is not retained when a POC reset is effected.
Page 780 CHAPTER 28 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS) Standard Products Flash Memory Programming Characteristics = −40 to +85°C, 2.7 V ≤ V ≤ 5.5 V, V = EV = EV = 0 V) μ (a) Conventional-specification products ( PD78F115x) Parameter Symbol Conditions MIN.
Page 781: Chapter 29 Electrical Specifications ((A) Grade Products)
PD78F1152A(A), 78F1153A(A), 78F1154A(A), 78F1155A(A), 78F1156A(A) Caution The 78K0R/KF3 has an on-chip debug function, which is provided for development and evaluation. Do not use the on-chip debug function in products designated for mass production, because the guaranteed number of rewritable times of the flash memory may be exceeded when this function is used, and product reliability therefore cannot be guaranteed.
Page 782 CHAPTER 29 ELECTRICAL SPECIFICATIONS ((A) GRADE PRODUCTS) (A) Grade Products Absolute Maximum Ratings (T = 25°C) (2/2) Parameter Symbols Conditions Ratings Unit −10 Output current, high Per pin P00 to P06, P10 to P17, P30, P31, P40 to P47, P50 to P55, P64 to P67, P70 to P77, P90, P120, P130, P140 to P145 −25...
Page 783 CHAPTER 29 ELECTRICAL SPECIFICATIONS ((A) GRADE PRODUCTS) (A) Grade Products X1 Oscillator Characteristics <R> = −40 to +85°C, 1.8 V ≤ V ≤ 5.5 V, V = EV = EV = AV = 0 V) Recommended Resonator Parameter Conditions MIN. TYP.
Page 784 CHAPTER 29 ELECTRICAL SPECIFICATIONS ((A) GRADE PRODUCTS) (A) Grade Products Internal Oscillator Characteristics = −40 to +85°C, 1.8 V ≤ V ≤ 5.5 V, V = EV = EV = AV = 0 V) Oscillators Parameters Conditions MIN. TYP. MAX. Unit 2.7 V ≤...
Page 785 CHAPTER 29 ELECTRICAL SPECIFICATIONS ((A) GRADE PRODUCTS) (A) Grade Products <R> XT1 Oscillator Characteristics = −40 to +85°C, 1.8 V ≤ V ≤ 5.5 V, V = EV = EV = AV = 0 V) Recommended Resonator Items Conditions MIN. TYP.
Page 786 When doing so, check the conditions for using the AMPH bit, RMC register, and whether to enter or exit the STOP mode. The oscillation voltage and oscillation frequency only indicate the oscillator characteristic. Use the 78K0R/KF3 so that the internal operation conditions are within the specifications of the DC and AC characteristics. User’s Manual U17893EJ8V0UD...
Page 787 When doing so, check the conditions for using the AMPH bit, RMC register, and whether to enter or exit the STOP mode. The oscillation voltage and oscillation frequency only indicate the oscillator characteristic. Use the 78K0R/KF3 so that the internal operation conditions are within the specifications of the DC and AC characteristics. User’s Manual U17893EJ8V0UD...
Page 788 When doing so, check the conditions for using the AMPH bit, RMC register, and whether to enter or exit the STOP mode. The oscillation voltage and oscillation frequency only indicate the oscillator characteristic. Use the 78K0R/KF3 so that the internal operation conditions are within the specifications of the DC and AC characteristics. User’s Manual U17893EJ8V0UD...
Page 789 When doing so, check the conditions for using the AMPH bit, RMC register, and whether to enter or exit the STOP mode. The oscillation voltage and oscillation frequency only indicate the oscillator characteristic. Use the 78K0R/KF3 so that the internal operation conditions are within the specifications of the DC and AC characteristics. User’s Manual U17893EJ8V0UD...
Page 790 When doing so, check the conditions for using the RMC register, and whether to enter or exit the STOP mode. The oscillation voltage and oscillation frequency only indicate the oscillator characteristic. Use the 78K0R/KF3 so that the internal operation conditions are within the specifications of the DC and AC characteristics. = −20 to +70°C)
Page 791 CHAPTER 29 ELECTRICAL SPECIFICATIONS ((A) GRADE PRODUCTS) (A) Grade Products DC Characteristics (1/12) = −40 to +85°C, 1.8 V ≤ V ≤ 5.5 V, 1.8 V ≤ AV ≤ V , 1.8 V ≤ AV ≤ V = EV = EV REF0 REF1 = AV...
Page 792 CHAPTER 29 ELECTRICAL SPECIFICATIONS ((A) GRADE PRODUCTS) (A) Grade Products DC Characteristics (2/12) = −40 to +85°C, 1.8 V ≤ V ≤ 5.5 V, 1.8 V ≤ AV ≤ V , 1.8 V ≤ AV ≤ V = EV = EV REF0 REF1 = AV...
Page 793 CHAPTER 29 ELECTRICAL SPECIFICATIONS ((A) GRADE PRODUCTS) (A) Grade Products DC Characteristics (3/12) = −40 to +85°C, 1.8 V ≤ V ≤ 5.5 V, 1.8 V ≤ AV ≤ V , 1.8 V ≤ AV ≤ V = EV = EV REF0 REF1 = AV...
Page 794 CHAPTER 29 ELECTRICAL SPECIFICATIONS ((A) GRADE PRODUCTS) (A) Grade Products DC Characteristics (4/12) = −40 to +85°C, 1.8 V ≤ V ≤ 5.5 V, 1.8 V ≤ AV ≤ V , 1.8 V ≤ AV ≤ V = EV = EV REF0 REF1 = AV...
Page 795 CHAPTER 29 ELECTRICAL SPECIFICATIONS ((A) GRADE PRODUCTS) (A) Grade Products DC Characteristics (5/12) = −40 to +85°C, 1.8 V ≤ V ≤ 5.5 V, 1.8 V ≤ AV ≤ V , 1.8 V ≤ AV ≤ V = EV = EV REF0 REF1 = AV...
Page 796 CHAPTER 29 ELECTRICAL SPECIFICATIONS ((A) GRADE PRODUCTS) (A) Grade Products DC Characteristics (6/12) = −40 to +85°C, 1.8 V ≤ V ≤ 5.5 V, 1.8 V ≤ AV ≤ V , 1.8 V ≤ AV ≤ V = EV = EV REF0 REF1 = AV...
Page 797 It is recommended to leave the FLMD0 pin open. If the pin is required to be pulled down externally, set to 100 kΩ or more. FLMD0 78K0R/KF3 FLMD0 pin FLMD0 Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins.
Page 798 CHAPTER 29 ELECTRICAL SPECIFICATIONS ((A) GRADE PRODUCTS) (A) Grade Products DC Characteristics (8/12) = −40 to +85°C, 1.8 V ≤ V ≤ 5.5 V, 1.8 V ≤ AV ≤ V , 1.8 V ≤ AV ≤ V = EV = EV REF0 REF1 = AV...
Page 799 CHAPTER 29 ELECTRICAL SPECIFICATIONS ((A) GRADE PRODUCTS) (A) Grade Products DC Characteristics (9/12) = −40 to +85°C, 1.8 V ≤ V ≤ 5.5 V, 1.8 V ≤ AV ≤ V , 1.8 V ≤ AV ≤ V = EV = EV REF0 REF1 = AV...
Page 800 CHAPTER 29 ELECTRICAL SPECIFICATIONS ((A) GRADE PRODUCTS) (A) Grade Products DC Characteristics (10/12) = −40 to +85°C, 1.8 V ≤ V ≤ 5.5 V, 1.8 V ≤ AV ≤ V , 1.8 V ≤ AV ≤ V = EV = EV REF0 REF1 = AV...
Page 801 CHAPTER 29 ELECTRICAL SPECIFICATIONS ((A) GRADE PRODUCTS) (A) Grade Products DC Characteristics (11/12) = −40 to +85°C, 1.8 V ≤ V ≤ 5.5 V, 1.8 V ≤ AV ≤ V , 1.8 V ≤ AV ≤ V = EV = EV REF0 REF1 = AV...
Page 802 I and I when the D/A converter operates in an operation mode or the HALT mode. 6. Current flowing only to the LVI circuit. The current value of the 78K0R/KF3 is the sum of I or I and I when the LVI circuit operates in the Operating, HALT or STOP mode.
Page 803 CHAPTER 29 ELECTRICAL SPECIFICATIONS ((A) GRADE PRODUCTS) (A) Grade Products AC Characteristics (1) Basic operation (1/6) = −40 to +85°C, 1.8 V ≤ V ≤ 5.5 V, 1.8 V ≤ AV ≤ V , 1.8 V ≤ AV ≤ V = EV REF0 REF1...
Page 804 CHAPTER 29 ELECTRICAL SPECIFICATIONS ((A) GRADE PRODUCTS) (A) Grade Products (1) Basic operation (2/6) Minimum instruction execution time during main system clock operation (FSEL = 0, RMC = 00H) Guaranteed range of main system clock operation (FSEL = 0, RMC = 00H) The range enclosed in dotted lines applies when the internal high-speed oscillator is selected.
Page 805 CHAPTER 29 ELECTRICAL SPECIFICATIONS ((A) GRADE PRODUCTS) (A) Grade Products (1) Basic operation (3/6) Minimum instruction execution time during main system clock operation (FSEL = 1, RMC = 00H) Guaranteed range of main system clock operation (FSEL = 1, RMC = 00H) The range enclosed in dotted lines applies when the internal high-speed oscillator is selected.
Page 806 CHAPTER 29 ELECTRICAL SPECIFICATIONS ((A) GRADE PRODUCTS) (A) Grade Products (1) Basic operation (4/6) Minimum instruction execution time during main system clock operation (FSEL = 0, RMC = 5AH) Guaranteed range of main system clock operation (FSEL = 0, RMC = 5AH) The range enclosed in dotted lines applies when the internal high-speed oscillator is selected.
Page 807 CHAPTER 29 ELECTRICAL SPECIFICATIONS ((A) GRADE PRODUCTS) (A) Grade Products (1) Basic operation (5/6) Minimum instruction execution time during self programming mode (RMC = 00H) Guaranteed range of self programming mode (RMC = 00H) The range enclosed in dotted lines applies when the internal high-speed oscillator is selected.
Page 808 CHAPTER 29 ELECTRICAL SPECIFICATIONS ((A) GRADE PRODUCTS) (A) Grade Products (1) Basic operation (6/6) AC Timing Test Points Test points External Main System Clock Timing 0.8V (MIN.) EXCLK 0.2V (MAX.) TI Timing TI00 to TI07 Interrupt Request Input Timing INTIL INTH INTP0 to INTP11 Key Interrupt Input Timing...
Page 809 Unit Transfer rate = 20 MHz, f Mbps UART mode connection diagram (during communication at same potential) TxDq 78K0R/KF3 User's device RxDq UART mode bit width (during communication at same potential) (reference) 1/Transfer rate High-/Low-bit width Baud rate error tolerance...
Page 810 CHAPTER 29 ELECTRICAL SPECIFICATIONS ((A) GRADE PRODUCTS) (A) Grade Products (2) Serial interface: Serial array unit (2/18) = −40 to +85°C, 1.8 V ≤ V ≤ 5.5 V, V = EV = EV = AV = 0 V) <R> (b) During communication at same potential (CSI mode) (master mode, SCKp... internal clock output) Parameter Symbol Conditions...
Page 811 CHAPTER 29 ELECTRICAL SPECIFICATIONS ((A) GRADE PRODUCTS) (A) Grade Products (2) Serial interface: Serial array unit (3/18) = −40 to +85°C, 1.8 V ≤ V ≤ 5.5 V, V = EV = EV = AV = 0 V) (c) During communication at same potential (CSI mode) (slave mode, SCKp... external clock input) <R>...
Page 812 (2) Serial interface: Serial array unit (4/18) CSI mode connection diagram (during communication at same potential) SCKp 78K0R/KF3 User's device CSI mode serial transfer timing (during communication at same potential) (When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1.)
Page 813 CHAPTER 29 ELECTRICAL SPECIFICATIONS ((A) GRADE PRODUCTS) (A) Grade Products (2) Serial interface: Serial array unit (5/18) = −40 to +85°C, 1.8 V ≤ V ≤ 5.5 V, V = EV = EV = AV = 0 V) (d) During communication at same potential (simplified I C mode) Parameter Symbol...
Page 814 (A) Grade Products (2) Serial interface: Serial array unit (6/18) Simplified I C mode mode connection diagram (during communication at same potential) SDAr 78K0R/KF3 User's device SCLr Simplified I C mode serial transfer timing (during communication at same potential) HIGH...
Page 815 CHAPTER 29 ELECTRICAL SPECIFICATIONS ((A) GRADE PRODUCTS) (A) Grade Products (2) Serial interface: Serial array unit (7/18) = −40 to +85°C, 2.7 V ≤ V ≤ 5.5 V, V = EV = EV = AV = 0 V) (e) During Communication at different potential (2.5 V, 3 V) (UART mode) (dedicated baud rate generator output) (1/2) Parameter Symbol...
Page 816 CHAPTER 29 ELECTRICAL SPECIFICATIONS ((A) GRADE PRODUCTS) (A) Grade Products (2) Serial interface: Serial array unit (8/18) = −40 to +85°C, 2.7 V ≤ V ≤ 5.5 V, V = EV = EV = AV = 0 V) (e) Communication at different potential (2.5 V, 3 V) (UART mode) (dedicated baud rate generator output) (2/2) Parameter Symbol Conditions...
Page 817 CHAPTER 29 ELECTRICAL SPECIFICATIONS ((A) GRADE PRODUCTS) (A) Grade Products (2) Serial interface: Serial array unit (9/18) Remarks 1. [Ω]:Communication line (TxDq) pull-up resistance, [F]: Communication line (TxDq) load capacitance, V [V]: Communication line voltage q: UART number (q = 1, 2), g: PIM and POM number (g = 0, 14) : Serial array unit operation clock frequency (Operation clock to be set by the CKSmn bit of the SMRmn register.
Page 818 CHAPTER 29 ELECTRICAL SPECIFICATIONS ((A) GRADE PRODUCTS) (A) Grade Products (2) Serial interface: Serial array unit (10/18) UART mode connection diagram (During communication at different potential) TxDq 78K0R/KF3 User's device RxDq UART mode bit width (During communication at different potential) 1/Transfer rate...
Page 819 CHAPTER 29 ELECTRICAL SPECIFICATIONS ((A) GRADE PRODUCTS) (A) Grade Products (2) Serial interface: Serial array unit (11/18) = −40 to +85°C, 2.7 V ≤ V ≤ 5.5 V, V = EV = EV = AV = 0 V) <R> (f) During Communication at different potential (2.5 V, 3 V) (CSI mode) (master mode, SCKp... internal clock output) (1/2) Parameter Symbol...
Page 820 When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. CSI mode connection diagram (during communication at different potential) <Master> SCKp 78K0R/KF3 User's device Caution Select the TTL input buffer for SIp and the N-ch open drain output (V tolerance) mode for SOp and SCKp by using the PIMg and POMg registers.
Page 821 CHAPTER 29 ELECTRICAL SPECIFICATIONS ((A) GRADE PRODUCTS) (A) Grade Products (2) Serial interface: Serial array unit (13/18) CSI mode serial transfer timing (during communication at different potential) (When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1.) KCY1 SCKp SIK1...
Page 822 “from SCKp↑” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. CSI mode connection diagram (during communication at different potential) <Slave> SCKp 78K0R/KF3 User's device (Caution and Remark are given on the next page.) User’s Manual U17893EJ8V0UD...
Page 823 CHAPTER 29 ELECTRICAL SPECIFICATIONS ((A) GRADE PRODUCTS) (A) Grade Products (2) Serial interface: Serial array unit (15/18) Caution Select the TTL input buffer for SIp and SCKp and the N-ch open drain output (V tolerance) mode for SOp by using the PIMg and POMg registers. Remarks 1.
Page 824 CHAPTER 29 ELECTRICAL SPECIFICATIONS ((A) GRADE PRODUCTS) (A) Grade Products (2) Serial interface: Serial array unit (16/18) CSI mode serial transfer timing (during communication at different potential) (When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1.) KCY2 SCKp SIK2...
Page 825 CHAPTER 29 ELECTRICAL SPECIFICATIONS ((A) GRADE PRODUCTS) (A) Grade Products (2) Serial interface: Serial array unit (17/18) = −40 to +85°C, 2.7 V ≤ V ≤ 5.5 V, V = EV = EV = AV = 0 V) (h) During Communication at different potential (2.5 V, 3 V) (simplified I C mode) Parameter Symbol...
Page 826 CHAPTER 29 ELECTRICAL SPECIFICATIONS ((A) GRADE PRODUCTS) (A) Grade Products (2) Serial interface: Serial array unit (18/18) Simplified I C mode connection diagram (during communication at different potential) SDAr 78K0R/KF3 User's device SCLr Simplified I C mode serial transfer timing (during communication at different potential) HIGH...
Page 827 CHAPTER 29 ELECTRICAL SPECIFICATIONS ((A) GRADE PRODUCTS) (A) Grade Products (3) Serial interface: IIC0 = −40 to +85°C, 1.8 V ≤ V ≤ 5.5 V, V = EV = EV = AV = 0 V) (a) IIC0 Parameter Symbol Conditions Standard Mode Fast Mode Unit...
Page 828 CHAPTER 29 ELECTRICAL SPECIFICATIONS ((A) GRADE PRODUCTS) (A) Grade Products (4) Serial interface: On-chip debug (UART) = −40 to +85°C, 1.8 V ≤ V ≤ 5.5 V, V = EV = EV = AV = 0 V) (a) On-chip debug (UART) Parameter Symbol Conditions...
Page 829 CHAPTER 29 ELECTRICAL SPECIFICATIONS ((A) GRADE PRODUCTS) (A) Grade Products A/D Converter Characteristics = −40 to +85°C, 2.3 V ≤ V ≤ 5.5 V, 2.3 V ≤ AV ≤ V , 1.8 V ≤ AV ≤ V = EV = EV = AV = 0 V) REF0...
Page 830 CHAPTER 29 ELECTRICAL SPECIFICATIONS ((A) GRADE PRODUCTS) (A) Grade Products μ Temperature Sensor (Expanded-Specification Products ( PD78F115xA) Only) = −40 to +85°C, 2.7 V ≤ V ≤ 5.5 V, 2.7 V ≤ AV ≤ V = EV = EV = 0 V) REF0 Parameter Symbol...
Page 831 CHAPTER 29 ELECTRICAL SPECIFICATIONS ((A) GRADE PRODUCTS) (A) Grade Products = −40 to +85°C, V POC Circuit Characteristics (T = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit Detection voltage 1.59 1.68 POC0 : 0 V → V Power supply voltage rise Change inclination of V V/ms POC0...
Page 832 CHAPTER 29 ELECTRICAL SPECIFICATIONS ((A) GRADE PRODUCTS) (A) Grade Products = −40 to +85°C, V ≤ V ≤ 5.5 V, V LVI Circuit Characteristics (T = EV = EV = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit Detection Supply voltage level 4.12 4.22...
Page 833 CHAPTER 29 ELECTRICAL SPECIFICATIONS ((A) GRADE PRODUCTS) (A) Grade Products = −40 to +85°C) Data Memory STOP Mode Low Supply Voltage Data Retention Characteristics (T Parameter Symbol Conditions MIN. TYP. MAX. Unit Note Data retention supply voltage DDDR Note The value depends on the POC detection voltage. When the voltage drops, the data is retained until a POC reset is effected, but data is not retained when a POC reset is effected.
Page 834 CHAPTER 29 ELECTRICAL SPECIFICATIONS ((A) GRADE PRODUCTS) (A) Grade Products Flash Memory Programming Characteristics = −40 to +85°C, 2.7 V ≤ V ≤ 5.5 V, V = EV = EV = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit supply current TYP.
Page 835: Chapter 30 Package Drawings
CHAPTER 30 PACKAGE DRAWINGS 80-PIN PLASTIC LQFP (14x14) detail of lead end (UNIT:mm) ITEM DIMENSIONS 14.00±0.20 14.00±0.20 17.20±0.20 17.20±0.20 1.70 MAX. 0.125±0.075 1.40±0.05 0.25 0.08 0.30 0.04 0.075 0.125 0.025 0.80 0.886±0.15 1.60±0.20 0.65 0.13 0.10 NOTE Each lead centerline is located within 0.13 mm of 0.825 its true position at maximum material condition.
Page 836 CHAPTER 30 PACKAGE DRAWINGS 80-PIN PLASTIC LQFP (FINE PITCH) (12x12) detail of lead end (UNIT:mm) ITEM DIMENSIONS 12.00±0.20 12.00±0.20 14.00±0.20 14.00±0.20 1.60 MAX. 0.10±0.05 1.40±0.05 0.25 0.07 0.20 0.03 0.075 0.125 0.025 0.50 0.60±0.15 1.00±0.20 0.50 0.08 0.08 1.25 NOTE 1.25 Each lead centerline is located within 0.08 mm of P80GK-50-GAK...
Page 837: Chapter 31 Recommended Soldering Conditions
CHAPTER 31 RECOMMENDED SOLDERING CONDITIONS These products should be soldered and mounted under the following recommended conditions. For soldering methods and conditions other than those recommended below, contact an NEC Electronics sales representative. For technical information, see the following website. Semiconductor Device Mount Manual (http://www.necel.com/pkg/en/mount/index.html) Caution For soldering methods and conditions other than those recommended below, contact an NEC Electronics sales representative.
Page 838 CHAPTER 31 RECOMMENDED SOLDERING CONDITIONS Table 31-1. Surface Mounting Type Soldering Conditions (2/2) • 80-pin plastic LQFP (fine pitch) (12 × 12) μ μ μ PD78F1152GK-GAK-AX, PD78F1152AGK-GAK-AX, PD78F1152AGK(A)-GAK-AX, μ μ μ PD78F1153GK-GAK-AX, PD78F1153AGK-GAK-AX, PD78F1153AGK(A)-GAK-AX, μ μ μ PD78F1154GK-GAK-AX, PD78F1154AGK-GAK-AX, PD78F1154AGK(A)-GAK-AX, μ...
Page 839: Appendix A Development Tools
APPENDIX A DEVELOPMENT TOOLS The following development tools are available for the development of systems that employ the 78K0R/KF3. Figure A-1 shows the development tool configuration. • Support for PC98-NX series Unless otherwise specified, products supported by IBM PC/AT compatibles are compatible with PC98-NX series computers.
Page 840 Flash memory Target system Notes 1. Download the device file for 78K0R/KF3 (DF781188) from the download site for development tools (http://www.necel.com/micro/ods/eng/index.html). The project manager PM+ is included in the assembler package. The PM+ is only used for Windows.
Page 841 Target connector Target system Notes 1. Download the device file for 78K0R/KF3 (DF781188) and the integrated debugger (ID78K0R-QB) from the download site for development tools (http://www.necel.com/micro/ods/eng/index.html). The project manager PM+ is included in the assembler package. The PM+ is only used for Windows.
Page 842: Software Package
APPENDIX A DEVELOPMENT TOOLS A.1 Software Package SP78K0R Development tools (software) common to the 78K0R microcontrollers are combined in 78K0R Series software package this package. μ Part number: S××××SP78K0R Remark ×××× in the part number differs depending on the host machine and OS used. μ...
Page 843: Control Software
APPENDIX A DEVELOPMENT TOOLS Remark ×××× in the part number differs depending on the host machine and OS used. μ S××××RA78K0R μ S××××CC78K0R ×××× Host Machine Supply Medium AB17 PC-9800 series, Windows (Japanese version) CD-ROM IBM PC/AT compatibles BB17 Windows (English version) μ...
Page 844: When Using On-Chip Debug Emulator With Programming Function Qb-Mini2
78K0R. The QB-MINI2 is supplied with a USB interface cable and connection cables (10-pin cable and 16-pin cable), and the 78K0-OCD board. To use 78K0R/KF3, use USB interface cable and 16-pin connection cable.
Page 845: When Using On-Chip Debug Emulator With Programming Function Qb-Mini2
The QB-MINI2 is supplied with a USB interface cable and connection cables (10-pin cable and 16-pin cable), and the 78K0-OCD board. To use 78K0R/KF3, use USB interface cable and 16-pin connection cable.
Page 846: Appendix B List Of Cautions
APPENDIX B LIST OF CAUTIONS This appendix lists the cautions described in this document. “Classification (hard/soft)” in the table is as follows. Hard: Cautions for microcontroller internal/external hardware Soft: Cautions for software such as register settings or programs (1/34) Function Details of Cautions Page...
Page 847 APPENDIX B LIST OF CAUTIONS (2/34) Function Details of Cautions Page Function Memory PMC: Processor Set PMC only once during the initial settings prior to operating the DMA controller. p.58 space mode control Rewriting PMC other than during the initial settings is prohibited. register After setting PMC, wait for at least one instruction and access the mirror area.
Page 848 APPENDIX B LIST OF CAUTIONS (3/34) Function Details of Cautions Page Function Port P10/SCK00, To use P10/SCK00, P11/SI00/RxD0, P12/SO00/TxD0, P13/TxD3, or P14/RxD3 as a p.104 functions P11/SI00/RxD, general-purpose port, note the serial array unit setting. For details, refer to the P12/SO00/TxD0, following tables.
Page 849 APPENDIX B LIST OF CAUTIONS (4/34) Function Details of Cautions Page Function Port P142/SCK20/ To use P142/SCK20/SCL20, P143/SI20/RxD2/SDA20, or P144/SO20/TxD2 as a p.133 functions SCL20, general-purpose port, note the serial array unit 1 setting. For details, refer to the P143/SI20/RxD2 following tables.
Page 850 APPENDIX B LIST OF CAUTIONS (5/34) Function Details of Cautions Page Function Clock CSC: Clock The setting of the flags of the register to stop clock oscillation (invalidate the external p.157 generator operation status clock input) and the condition before clock oscillation is to be stopped are as follows. control register (See Table 5-2.) OSTC:...
Page 851 APPENDIX B LIST OF CAUTIONS (6/34) Function Details of Cautions Page Function Clock PER0: Peripheral Be sure to clear bit 1 of the PER0 register to 0. pp.163, generator enable registers OSMC: OSMC can be written only once after reset release, by an 8-bit memory manipulation p.165 Operation speed instruction.
Page 852 APPENDIX B LIST OF CAUTIONS (7/34) Function Details of Cautions Page Function Clock When LVI A voltage oscillation stabilization time is required after the supply voltage reaches p.175 generator default start 1.59 V (TYP.). If the supply voltage rises from 1.59 V (TYP.) to 2.07 V (TYP.) within operation function enabled the power supply oscillation stabilization time, the power supply oscillation...
Page 853 APPENDIX B LIST OF CAUTIONS (8/34) Function Details of Cautions Page Function Subsystem Subsystem clock The CMC register can be written only once after reset release, by an 8-bit memory p.181 clock manipulation instruction. control Therefore, it is necessary to also set the value of the EXCLK and OSCSEL bits at the same time.
Page 854 APPENDIX B LIST OF CAUTIONS (9/34) Function Details of Cautions Page Function Timer TOL0: Timer Be sure to clear bits 15 to 8 to “0”. p.216 array unit output level register 0 TOM0: Timer Be sure to clear bits 15 to 8 to “0”. p.217 output mode register 0...
Page 855 APPENDIX B LIST OF CAUTIONS (10/34) Function Details of Cautions Page Function Operation of Input pulse The TI0n pin input is sampled using the operating clock selected with the CKS0n bit p.244 timer array interval of the TMR0n register, so an error equal to the number of operating clocks occurs. unit as measurement independent...
Page 856 APPENDIX B LIST OF CAUTIONS (11/34) Function Details of Cautions Page Function Real-time RSUBC: Sub- When a correction is made by using the SUBCUD register, the value may become p.281 counter count register 8000H or more. This register is also cleared by reset effected by writing the second count register. p.281 The value read from this register is not guaranteed if it is read during operation, p.281...
Page 857 APPENDIX B LIST OF CAUTIONS (12/34) Function Details of Cautions Page Function Watchdog Setting overflow The watchdog timer continues its operation during self-programming of the flash p.305 timer time memory and EEPROM emulation. During processing, the interrupt acknowledge time is delayed. Set the overflow time and window size taking this delay into consideration.
Page 858 APPENDIX B LIST OF CAUTIONS (13/34) Function Details of Cautions Page Function A/D conversion Set the conversion times with the following conditions. p.318 • 4.0 V ≤ AV ≤ 5.5 V: f converter time selection = 0.6 to 3.6 MHz REF0 (2.3 V ≤...
Page 859 APPENDIX B LIST OF CAUTIONS (14/34) Function Details of Cautions Page Function Registers used When rewriting FR2 to FR0, LV1, and LV0 to other than the same data, stop A/D p.330 converter by temperature conversion (ADCS = 0) beforehand. sensors The above conversion time does not include clock frequency errors.
Page 860 APPENDIX B LIST OF CAUTIONS (15/34) Function Details of Cautions Page Function Noise To maintain the 10-bit resolution, attention must be paid to noise input to the AV p.340 REF0 converter countermeasures pin and pins ANI0 to ANI7. <1> Connect a capacitor with a low equivalent resistance and a good frequency response to the power supply.
Page 861 APPENDIX B LIST OF CAUTIONS (16/34) Function Details of Cautions Page Function A/D conversion When a write operation is performed to the A/D converter mode register (ADM), p.342 converter result register analog input channel specification register (ADS), and A/D port configuration register (ADCR, (ADPC), the contents of ADCR and ADCRH may become undefined.
Page 862 APPENDIX B LIST OF CAUTIONS (17/34) Function Details of Cautions Page Function Reducing power Because the D/A converter stops operation in the STOP mode, the ANO0 and ANO1 p.351 converter consumption in pins go into a high impedance state, and the power consumption can be reduced. In STOP mode the standby modes other than the STOP mode, however, the operation continues.
Page 863: Appendix C Revision History
APPENDIX B LIST OF CAUTIONS (18/34) Function Details of Cautions Page Function Registers SOEm: Serial Be sure to clear bits 15 to 3 of SOE0, and bits 15 to 3 and 1 of SOE1 to “0”. p.375 controlling output enable serial array register m unit...
Page 864 APPENDIX B LIST OF CAUTIONS (19/34) Function Details of Cautions Page Function 3-wire serial I/O Slave The MDmn0 bit can be rewritten even during operation. p.433 (CSI00, CSI01, transmission/ However, rewrite it before transfer of the last bit is started, so that it will be rewritten CSI10, CSI20) reception (in before the transfer end interrupt of the last transmit data.
Page 865 APPENDIX B LIST OF CAUTIONS (20/34) Function Details of Cautions Page Function Serial IICF0: IIC flag As the bus release status (IICBSY = 0) is recognized regardless of the actual bus p.508 interface register 0 status when STCEN = 1, when generating the first start condition (STT0 = 1), it is IIC0 necessary to verify that no third party communications are in progress in order to prevent such communications from being destroyed.
Page 866 APPENDIX B LIST OF CAUTIONS (21/34) Function Details of Cautions Page Function Serial STT0, SPT0: When transmission is reserved, set SPIE0 (bit 4 of IICL0) to 1 so that an interrupt p.530 interface Bits 1, 0 of IIC request is generated when the stop condition is detected. Transfer is started when IIC0 control register 0 communication data is written to IIC0 after the interrupt request is generated.
Page 867 APPENDIX B LIST OF CAUTIONS (22/34) Function Details of Cautions Page Function Operation if The address indicated by DRA0n is incremented during DMA transfer. If the address p.596 controller address in is incremented to an address in the general-purpose register area or exceeds the general-purpose area of the internal RAM, the following operation is performed.
Page 868 APPENDIX B LIST OF CAUTIONS (23/34) Function Details of Cautions Page Function Interrupt EGP0, EGP1: Select the port mode by clearing EGPn and EGNn to 0 because an edge may be p.610 functions External detected when the external interrupt function is switched to the port function. interrupt rising edge enable registers, EGN0,...
Page 869 APPENDIX B LIST OF CAUTIONS (24/34) Function Details of Cautions Page Function Standby OSTS: To set the STOP mode when the X1 clock is used as the CPU clock, set OSTS p.623 function Oscillation before executing the STOP instruction. μ stabilization time Setting the oscillation stabilization time to 20 s or less is prohibited.
Page 870 APPENDIX B LIST OF CAUTIONS (25/34) Function Details of Cautions Page Function Reset Block diagram of An LVI circuit internal reset does not reset the LVI circuit. p.637 function reset function Watchdog timer A watchdog timer internal reset resets the watchdog timer. p.638 overflow RESF: Reset...
Page 871 APPENDIX B LIST OF CAUTIONS (26/34) Function Details of Cautions Page Function Low- LVIS: Low- Change the LVIS value with either of the following methods. p.656 voltage voltage detection • When changing the value after stopping LVI detector level select <1>...
Page 872 APPENDIX B LIST OF CAUTIONS (27/34) Function Details of Cautions Page Function Low- Used as interrupt Even when the LVI default start function is used, if it is set to LVI operation p.666 voltage (when detecting prohibition by the software, it operates as follows: detector level of supply •...
Page 873 APPENDIX B LIST OF CAUTIONS (28/34) Function Details of Cautions Page Function Low- Cautions for low- There is some delay from the time supply voltage (V ) < LVI detection voltage (V p.673 voltage voltage detector until the time LVI reset has been generated. detector In the same way, there is also some delay from the time LVI detection voltage (V ≤...
Page 874 0 takes priority. On-chip Connecting QB- The 78K0R/KF3 has an on-chip debug function, which is provided for development p.699 debug MINI2 to and evaluation. Do not use the on-chip debug function in products designated for...
Page 875 Cautions Page Function − Electrical The 78K0R/KF3 has an on-chip debug function, which is provided for development p.726 specifications and evaluation. Do not use the on-chip debug function in products designated for (standard mass production, because the guaranteed number of rewritable times of the flash...
Page 876 STOP mode. The oscillation voltage and oscillation frequency only indicate the oscillator characteristic. Use the 78K0R/KF3 so that the internal operation conditions are within the specifications of the DC and AC characteristics. P02 to P04, P43, P45, P142 to P144 do not output high level in N-ch open-drain p.736...
Page 877 (2.5 V, 3 V) (simplified C mode) − Electrical The 78K0R/KF3 has an on-chip debug function, which is provided for development p.781 specifications and evaluation. Do not use the on-chip debug function in products designated for ((A) grade mass production, because the guaranteed number of rewritable times of the flash...
Page 878 The oscillation voltage and oscillation frequency only indicate the oscillator characteristic. Use the 78K0R/KF3 so that the internal operation conditions are within the specifications of the DC and AC characteristics. The oscillator constants shown above are reference values based on evaluation in a p.790...
Page 879 APPENDIX B LIST OF CAUTIONS (34/34) Function Details of Cautions Page Function Electrical During Select the normal input buffer for SIj and SCKj and the normal output mode for SOj p.811 specifications communication by using the PIMg and POMg registers. ((A) grade at same potential products)
Page 880: Major Revisions In This Edition
APPENDIX C REVISION HISTORY C.1 Major Revisions in This Edition (1/5) Page Description Classification Throughout − Change of status of (A) grade products of the expanded-specification products from under development to mass production CHAPTER 1 OUTLINE μ p.17 Change of 1.1 Differences Between Conventional-Specification Products ( PD78F115x) and μ...
Page 881 APPENDIX C REVISION HISTORY (2/5) Page Description Classification CHAPTER 6 TIMER ARRAY UNIT (continuation) p.211 Change of Figure 6-13. Start Timing (In One-count Mode) p.212 Change of Figure 6-14. Start Timing (In Capture & One-count Mode) p.218 Change of description of ISC1 and ISC0 bits in Figure 6-21. Format of Input Switch Control Register (ISC) CHAPTER 7 REAL-TIME COUNTER p.273...
Page 882 APPENDIX C REVISION HISTORY (3/5) Page Description Classification CHAPTER 12 SERIAL ARRAY UNIT (continuation) p.398 Change of Figure 12-35. Procedure for Resuming Master Reception p.400 Change of Figure 12-37. Flowchart of Master Reception (in Single-Reception Mode) p.401 Addition of Figure 12-38. Timing Chart of Master Reception (in Continuous Reception Mode) (Type 1: DAPmn = 0, CKPmn = 0) p.402 Addition of Figure 12-39.
Page 883 APPENDIX C REVISION HISTORY (4/5) Page Description Classification CHAPTER 15 DMA CONTROLLER (continuation) p.591 Addition of Caution to Figure 15-12. Example of Setting for Holding DMA Transfer Pending by DWAITn p.592 Change of 15.5.7 Forced termination by software p.594 Change of (1) Priority of DMA in 15.6 Cautions on Using DMA Controller p.595 Change of (2) DMA response time in 15.6 Cautions on Using DMA Controller p.596...
Page 884 APPENDIX C REVISION HISTORY (5/5) Page Description Classification CHAPTER 28 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS) (continuation) p.770 Addition of Note to (h) During communication at different potential (2.5 V, 3 V) (simplified I mode) in Serial interface: Serial array unit p.780 Change of Number of rewrites of Expanded-specification products in Flash Memory Programming Characteristics CHAPTER 29 ELECTRICAL SPECIFICATIONS ((A) GRADE PRODUCTS)
Page 885: Revision History Of Preceding Editions
APPENDIX C REVISION HISTORY C.2 Revision History of Preceding Editions Here is the revision history of the preceding editions. Chapter indicates the chapter of each edition. (1/20) Edition Description Chapter 2nd edition 1.1 Features CHAPTER 1 OUTLINE μ μ • Change of status indication of PD78F1157 and PD78F1158 to “under planning”...
Page 886 APPENDIX C REVISION HISTORY (2/20) Edition Description Chapter 2nd edition Addition of Cautions 1 and 2 to 4.2.1 Port 0 CHAPTER 4 PORT FUNCTIONS Addition of Cautions 1 and 2 to 4.2.2 Port 1 Addition of Caution to 4.2.4 Port 3 Addition of Cautions 2 and 3 to 4.2.5 Port 4 Modification of Figure 4-28 Block Diagram of P80 to P87 and Figure 4-29 Block Diagram of P110 and P111...
Page 887 APPENDIX C REVISION HISTORY (3/20) Edition Description Chapter 2nd edition Addition of an arrow from (C) to (B) in Figure 6-16 CPU Clock Status Transition CHAPTER 6 CLOCK Diagram GENERATOR Modification of Table 6-4 CPU Clock Transition and SFR Register Setting Examples Addition of description to Table 6-5 Changing CPU Clock Modification of description in 6.6.7 Time required for switchover of CPU clock and...
Page 888 APPENDIX C REVISION HISTORY (4/20) Edition Description Chapter 2nd edition Modification of Caution and addition of Remark in Figure 8-2 Format of Peripheral CHAPTER 8 REAL- Enable Register 0 (PER0) TIME COUNTER Modification of Caution in 8.3 (2) Real-time counter control register 0 (RTCC0) Modification of Caution in 8.3 (3) Real-time counter control register 1 (RTCC1) Addition of Remark in Figure 8-4 Format of Real-Time Counter Control Register 1 (RTCC1) and Figure 8-21 Alarm Setting Procedure...
Page 889 APPENDIX C REVISION HISTORY (5/20) Edition Description Chapter 2nd edition Modification of description in 19.1.2 (1) Oscillation stabilization time counter CHAPTER 19 status register (OSTC). STANDBY FUNCTION Change of reset value of 19.1.2 (2) Oscillation stabilization time select register (OSTS). Modification of setting in Figure 19-2.
Page 890 APPENDIX C REVISION HISTORY (6/20) Edition Description Chapter 2nd edition A/D Converter Characteristics CHAPTER 28 • Modification of condition in upper part of table ELECTRICAL SPECIFICATIONS • Modification of conditions and MAX. value of differential linearity error (DLE) (TARGET) D/A Converter Characteristics •...
Page 891 APPENDIX C REVISION HISTORY (7/20) Edition Description Chapter 3rd edition Addition of Table 6-4 Operations from Count Operation Enabled State to TCR0n CHAPTER 6 TIMER Count Start, and (a) through (e) ARRAY UNIT Addition of description to 6.3 (11) Timer output level register 0 (TOL0) Change of description of 6.3 (12) Timer output mode register 0 (TOM0) Change of Figure 6-20 Format of Timer Output Mode Register 0 (TOM0) and Remark...
Page 892 APPENDIX C REVISION HISTORY (8/20) Edition Description Chapter 3rd edition Changes of setting of (b) Serial output enable register m (SOEm) in Figure 12-74 CHAPTER 12 SERIAL Example of Contents of Registers for UART Reception of UART (UART0, ARRAY UNIT UART1, UART2, UART3) Change of Figure 12-89 Flowchart of Address Field Transmission Change of Figure 12-92 Flowchart of Data Transmission...
Page 893 APPENDIX C REVISION HISTORY (9/20) Edition Description Chapter 3rd edition DC characteristics CHAPTER 28 • Change of Condition and Note 1 in Output current, high (I ELECTRICAL SPECIFICATIONS • Change of Condition and Note 2 in Output current, low (I (TARGET) •...
Page 894 APPENDIX C REVISION HISTORY (10/20) Edition Description Chapter 4th edition Change of description in 6.3 (14) Noise filter enable register 1 (NFEN1) CHAPTER 6 TIMER ARRAY UNIT Change of 6.5.1 TI0n edge detection circuit Change of Figure 7-1 Block Diagram of Real-Time Counter CHAPTER 7 REAL- TIME COUNTER Addition of Caution 3 to Table 8-4 Setting Window Open Period of Watchdog...
Page 895 APPENDIX C REVISION HISTORY (11/20) Edition Description Chapter 4th edition Change of Note 4 in Figure 21-2 Format of Low-Voltage Detection Register CHAPTER 21 LOW- (LVIM) and addition of Caution 3 VOLTAGE DETECTOR Change of Caution 2 in Figure 21-3 Format of Low-Voltage Detection Level Select Register (LVIS) Change of <5>...
Page 896 APPENDIX C REVISION HISTORY (12/20) Edition Description Chapter 5th edition Change of address in Figure 3-16. Configuration of General-Purpose Registers CHAPTER 3 CPU ARCHITECTURE Addition of register and Note in Table 3-5. SFR List Addition of PIM register and POM register in block diagram CHAPTER 4 PORT FUNCTIONS Change of corresponding pins of EV...
Page 897 APPENDIX C REVISION HISTORY (13/20) Edition Description Chapter 5th edition Change of Figure 12-42. Timing Chart of Master Transmission/Reception (in CHAPTER 12 SERIAL Single-Transmission/Reception Mode) ARRAY UNIT Change of Figure 12-44. Timing Chart of Master Transmission/Reception (in Continuous Transmission/Reception Mode) Change of Figure 12-45.
Page 898 APPENDIX C REVISION HISTORY (14/20) Edition Description Chapter 5th edition Change of description in (4) CHAPTER 19 RESET FUNCTION Change of Figure 19-2. Timing of Reset by RESET Input Change of Figure 19-4. Timing of Reset in STOP Mode by RESET Input Change of 24.4.1 FLMD0 pin CHAPTER 24 FLASH MEMORY...
Page 899 APPENDIX C REVISION HISTORY (15/20) Edition Description Chapter 5th edition Change of A.4.1 When using flash memory programmer FG-FP4 and FL-PR4 APPENDIX A DEVELOPMENT Change of A.4.2 When using on-chip debug emulator with programming TOOLS function QB-MINI2 Change of A.5.2 When using on-chip debug emulator with programming function QB-MINI2 μ...
Page 900 APPENDIX C REVISION HISTORY (16/20) Edition Description Chapter 7th edition Change of channel number in 6.1.1 (4) Divider function CHAPTER 6 TIMER ARRAY UNIT Change of Cautions in Figure 6-4. Format of Peripheral Enable Register 0 (PER0) Change of description of CCS0n and MASTER0n bits in Figure 6-6 Format of Timer Mode Register 0n (TMR0n) Change of description in 6.4.3 (1) Changing values set in registers TO0, TOE0, TOL0, and TOM0 during timer operation...
Page 901 APPENDIX C REVISION HISTORY (17/20) Edition Description Chapter 7th edition Addition of 7.4.6 32.768 kHz output of real-time counter CHAPTER 7 REAL- TIME COUNTER Addition of 7.4.7 512 Hz, 16.384 kHz output of real-time counter Addition of 7.4.8 Example of watch error correction of real-time counter Change of Cautions 1 and 2 in Figure 8-2 Format of Watchdog Timer Enable CHAPTER8 Register (WDTE)
Page 902 APPENDIX C REVISION HISTORY (18/20) Edition Description Chapter 7th edition Modification of Figure 12-44 Timing Chart of Master Transmission/Reception (in CHAPTER 12 SERIAL Continuous Transmission/Reception Mode) (Type 1: DAPmn = 0, CKPmn = 0) ARRAY UNIT Change of transfer rate in 12.5.4 Slave transmission Change of Figure 12-48 Procedure for Stopping Slave Transmission Change of Figure 12-49 Procedure for Resuming Slave Transmission Change of Figure 12-50 Timing Chart of Slave Transmission (in Single-...
Page 903 APPENDIX C REVISION HISTORY (19/20) Edition Description Chapter 7th edition Change of Figure 12-93 Timing Chart of Data Transmission CHAPTER 12 SERIAL ARRAY UNIT Addition of Note to 12.7.3 Data reception Change of Figure 12-96 Timing Chart of Data Reception Change of Figure 12-97 Flowchart of Data Reception and change of Caution Change of Figure 12-98 Timing Chart of Stop Condition Generation Change of Note 2 in Table 12-4 Selection of Operation Clock...
Page 904 FP5 (Reference Values) Addition of Caution 5 to 24.9 Flash Memory Programming by Self-Programming Change of description in 24.9.2 Flash shield window function Change of Caution in 25.1 Connecting QB-MINI2 to 78K0R/KF3 CHAPTER 25 ON-CHIP DEBUG FUNCTION Addition of Caution to Figure 25-1 Connection Example of QB-MINI2 and...

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Renesas 78K0R/KF3 User Manual

Chapter 1 Outline

Chapter 2 Pin Functions

Chapter 3 Cpu Architecture

Chapter 4 Port Functions

Chapter 5 Clock Generator

Chapter 6 Timer Array Unit

Chapter 7 Real-Time Counter

Chapter 8 Watchdog Timer

Chapter 9 Clock Output/Buzzer Output Controller

Chapter 10 A/D Converter

Chapter 11 D/A Converter

Chapter 12 Serial Array Unit

Chapter 13 Serial Interface Iic0

Chapter 14 Multiplier

Chapter 15 Dma Controller

Chapter 16 Interrupt Functions

Chapter 17 Key Interrupt Function

Chapter 18 Standby Function

Chapter 19 Reset Function

Chapter 20 Power-On-Clear Circuit

Chapter 21 Low-Voltage Detector

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Summary of Contents for Renesas 78K0R/KF3